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Testing of VLSI Design

Dr Usha Mehta

[email protected]

[email protected]

mailto:[email protected]

mailto:[email protected]

Acknowledgement…..

This presentation has been summarized from various

books, papers, websites and presentations on VLSI

Design and its various topics all over the world. I

couldn’t item-wise mention from where these large

pull of hints and work come. However, I’d like to

thank all professors and scientists who created such

a good work on this emerging field. Without those

efforts in this very emerging technology, these notes

and slides can’t be finished.

22-01-2016 Dr Usha Mehta 2

Does anybody really like

testing?

• Does testing directly generate any

revenue?

• Does designer like testing?

• Does it generate “trust” ?

• Does trust generate “reusability”?

• Does reusability generate “revenue”?

• The relation between yield and

testing?


Bugs are costly!!!!

• “Bugfree Design” does not give any

extra revenue but bugs in design are

very costly!!!! • Pentium bug

• Intel Pentium chip, released in 1994 produced error in floating point division

• Cost : $475 million

• ARIANE Failure

• In December 1996, the Ariane 5 rocket exploded 40 seconds after take off . A software components threw an exception

• Cost : $400 million payload.

• Therac-25 Accident :

• A software failure caused wrong dosages of x-rays.

• Cost: Human Loss. 22-01-2016 Dr Usha Mehta 4

Manufacturing Cost versus Test Cost


[Courtesy: ITRS]

Verification and Testing????


• How many steps are there related to

verification and testing in any ASIC

Design flow?

• Let’s check

Cost Components of Testing

• Test Development Cost – Software process of test

– Test generation and fault simulation

– Test programming and debugging

• Test Application Cost – ATE Cost

– Test Center Operation Cost

– Depends on Test Time per IC

• DFT – Chip Area Overhead and Yield Reduction

– Performance Overhead


Role of Testing in General

• Verification

• Validation

• Detection

• Diagnosis

• Device Characterization

• Failure Mode Analysis (FMA)


Verification

• Verifies the correctness of Design

• Performed once prior to

manufacturing process

• Performed by simulation, hardware

emulation or formal methods

• Responsible for quality of design

• Like sonography used for unborn

baby during pregnancy


Validation

• After the first lot of prototypes are manufactured,

IC goes through, design validation/pilot-run stage.

• It checks that either the fabrication process was

correct and fabricated IC is correct. ( Here it is

assumed that design was error free)

• AC, DC, Functional Test

• Probing internal chip nodes also

• Special tools like scanning electron Microscope, electron beam scanner, artificial intelligent technique etc, are used

• Like Newborn sreening tests for baby


Detection

• Does any of the fault exists?

• Which, why, how, where, when is out of scope here.

• Only YES/NO. Go/No Go test for IC to be shipped to market

or not.

• At fabrication unit

• For all fabricated IC

• Less comprehensive than characterization

• Test should have high fault coverage, low cost and minimum

test time

• Are you completely fit? Does any of the disease

there?

• Like medical test for army ( if fit then go, otherwise

no go)


Verification vs Testing


Diagnosis

• Identify the fault that exists in system.

• Which fault is there (type of fault)?

• Where is that fault (fault location)?

• Like after a set of pathological test,

the doctor diagnosis your disease.


Device Characterization

• Determination and correction of errors

in design and/or test procedure

• So that the next lot of IC will be error

free.

• Like doctor writes a prescription of

medicine to cure your disease.

• Here there is a difference between

man and IC!!!!!!!!!


Failure Mode Analysis

• Why/How/when the fault had

occurred?

• Determine the manufacturing process

errors that may have caused the fault.

• Like determining why that disease

occurred and find the preventive

actions (bad health /food habits) which

created disease


Failure Rate vs Product Life Time

Product Life Time

Fai

lure

Rat

e

Infant

Mortality Working Life Span Wearout

1-20 weeks 10-20 years


Burn-In/Stress Test

• To stress the chip to accelerate the failure mechanism

• Some chip passes the production test but will fail very quickly thereafter

• To increase temp and/or voltage while applying test patterns

• Infant Mortality Failures: 10-30 Hrs

• Freak Failure: 100-1000Hrs


Acceptance Testing/

Incoming Inspection

• Customer performs this test

• Like universal tester to test the IC at

our Digital Electronics Labs


Levels of Testing

:Chip:

Above chip

• Board

• System

• System in field

Below chip

• Unpacked chip

• Architectural

• Behavioural

• RTL

• Gate

• Transistor

• Physical

Cost – Rule of 10 It costs 10 times more to test a device as we move to higher level in the product manufacturing process


Causes of the Defects in IC

• Design Errors – Verification process will catch it

• Fabrication Errors – Wrong component

– Incorrect Wiring

• Fabrication Defects – Imperfect Process Variations

• Physical Failure – During life time of a system


Classifications of the Defects

• Permanent

• Intermittent

– During some intervals

• Transient

– One time only


Test Principal for Digital Circuits


Is it so easy?

For a 64 bit adder circuit, if complete set of input patterns are applied…..

129 inputs, 65 outputs: 2129

=680,564,733,841,876,926,926,749,214,863,536,422,912

Patterns

• Using 1 GHz ATE, would take

2.15 x 1022 years!!!!!!!


Test Plan

• Design House: Design is complete and checked

(verified)

• Fab vendor: How will you test it?

• Design house: I have checked it and …

• Fab vendor: OK. But, how would you test it?

• Design house: Why is that important?

• Complete the story…..

• None of the fab will manufacture your design if you

can not satisfy them with proper test plan.

• That is one reason for design-for testability, test

generation, Bult-In-Self-Test etc.


Test Development Vs

Manufacturing Test


Components of Testing

• Test Development

– How will be the IC tested

– Software process to plan the test process of IC

– Test generation and fault simulation

– Test programming and debugging

– One time process

– Cost involved here is: use of costly automatic test pattern generation and test plan developer

• Test Application

– Actual testing process

– Applied to each fabricated IC

– Done by costly ATE

– Cost involved here is : Test Center Operation Cost and ATE cost, Depends on Test Time per IC

• Worth to use complicated lengthy test development process if it can actually reduce the time for test application


TEST PLAN DRAWING A QUESTION PAPER???


Ideal Test

• Ideal tests detect all defects produced in the manufacturing process.

• Ideal tests pass all functionally good devices.

• Very large numbers and varieties of possible defects need to be tested.

• Difficult to generate tests for some real defects.

• Defect-oriented testing is an open problem.

• Is it practical?

• What to do?

• Philosophy???


Testing Philosophy

• Students-chips

• Course syllabus – specifications

• No one has infinite time

– Test paper – fault model

• Fail: repeat the course, redesign the chip

• Asking teachers the details in advance – DFT

• If too hard question paper: a student of pass category fails –student’s image at risk (manufacturer’s risk) – yield loss

• If too easy question paper: a student of fail category passes – teacher’s image at risk (consumer’s risk) – defect level


How effective your testing is?

• Three Important

Things………

Yield(MONEY)

Yield(MONEY) and

Just Yield…..Just

MONEY!!!!!

• Yield vs Fault

Coverage


Effective testing…..

• It means… now onwards all over

efforts should be more and more

effective testing

It means……

• Less test application time

• More fault coverage

• Less test power

• Less test cost


Some Terminology….

• When is testing performed? – As a separate activity – off line testing

– Concurrent with normal system operation- on line testing

• Where is the source of stimuli? – Within the system itself – self testing

– Applied by an external device/tester – external testing

• What do we test for? – Design Errors – Verification

– Fabrication Errors – Acceptance Testing

– Fabrication Defects- Burn In

– In fancy Physical Failure – Quality Assurance Testing

– Physical Failures – Field Testing/ Maintenance Testing


Terminology……

• How are the stimuli and expected response produced? – Received from storage-Stored pattern testing

– Generated during testing – algorithmic testing ( stimuli), comparison testing (response)

• How are the stimuli applied? – In a fixed order

– Depending upon the result obtained so far – adaptive testing

• How fast are the stimuli applied? – Much slower than the normal speed – DC/Static testing

– At normal operating speed – AC / At speed testing


Some terminology….

• What are the observed results? – The entire output pattern

– Some function of output pattern – compact/signature testing

• Which lines are accessible for testing? – Only the I/O lines –edge pin testing

– I/O and Internal Lines – Guided Probe testing, Bed of nails testing, electron beam testing, In circuit emulation, in-circuit testing ( tester will automatically isolate the IC already mounted on board.

• Who checks the results? – The system itself – Self testing/checking

– An external device/checker – External testing


Thanks……

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