testing of cap-cav 2 llrf development with desy

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Fermilab AAC May 11 th 1 /12 Testing of Cap-Cav 2 LLRF Development with DESY Alexander Brandt, DESY, Hamburg 1. Current and Future LLRF Developments at DESY 2. DESY Low Latency Control Hardware 3. Collaboration with FNAL-A0, –SMTF and –HPTF (present and future)

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Testing of Cap-Cav 2 LLRF Development with DESY. Alexander Brandt, DESY, Hamburg Current and Future LLRF Developments at DESY DESY Low Latency Control Hardware Collaboration with FNAL-A0, –SMTF and –HPTF (present and future). DESY LLRF Contributors. - PowerPoint PPT Presentation

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Fermilab AAC May 11th 1/12

Testing of Cap-Cav 2LLRF Development with DESY

Alexander Brandt, DESY, Hamburg

1. Current and Future LLRF Developments at DESY

2. DESY Low Latency Control Hardware

3. Collaboration with FNAL-A0, –SMTF and –HPTF (present and future)

Fermilab AAC May 11th 2/12

DESY LLRF Contributors

• DESY, Hamburg, Valeri Ayvazyan, Alexander Brandt, Gerhard Grygiel, Thomas Fröhlich, Olaf Hensler, Matthias Hoffmann, Bastian Lorbeer, Frank Ludwig, Günther Möller, Kay Rehlich, Stefan Simrock, Henning Weddig, ...

• WUT-ISE, Warsaw, Tomasz Czarski, Krzystof Czuba, Tomasz Filipek, Wojciech Giergusiewicz, Wojciech Jalmuzna, Pawel Kaleta, Waldemar Koprek, Karol Perkuszewski, Piotr Pucyk, Ryszard Romaniuk, Jaroslaw Szewinski, ...

• TUL-DMCS, Lodz, Wojciech Cichalewski, Piotr Cieciura, Mariusz Grecki, Tomasz Jezynski, Boguslaw Koseda, Dariusz Markowski, Pawel Pawlik, Przemsylaw Sekalski, Bartlomiej Swiercz, Marcin Wojtowski, ...

• IHEP, Protvino, Nikolay Ignashin, Sergej Sytov, ...• INFN, Milano, Angelo Bosotti, Rocco Paparella• KEK, Japan, Shin Michizono, Toshi Matsumoto• Yerewan Institute, Gevorg Petrosyan, Ludwig Petrosyan• ...

Fermilab AAC May 11th 3/12

LLRF Developments at DESY: VUV-FEL

•Running since 2004 (as successor of TTF1, 1997-2003)

•SC linear injector, 6 undulator sections (down to 6nm wavelength)

•Pulsed operation (2ms / 1-10Hz)

•1 nc cathode, 48 sc cavities, 1 transverse deflecting cavity

•5 rf stations (one klystron per 8-32 sc cavities)

•Field stability requirement: 10-3 / 0.1°

•Designed as user facility and for accelerator development

•Ideal testbed for LLRF developments!

Fermilab AAC May 11th 4/12

LLRF Developments at DESY: VUV-FEL

Fermilab AAC May 11th 5/12

LLRF Developments at DESY: XFEL, ILC

• FEL lightsource for sub-nm wavelength, commissioning ~2012 at DESY

• ~1000 cavities, 35 klystrons

• High field stability: 10-4, 0.01°

• User facility (high reliability)

• Demands for a low-maintenance, radiation resistive hardware

• Future project, not yet scheduled (2012-2020?)

• ~20000 cavities

• Collider experiment, therefore relaxed field requirements

• Very high degree of automation needed (e.g. global phase control, recovery automation)

Fermilab AAC May 11th 6/12

Vecor Sum Control Challenges

1.3

VM

ADC

... (32)

DSPDAC

• Latency in control loop limits feedback gain (and therefore field stability) build faster feedback hardware (Current revision: SimCon 3.1 FPGA system, ~200ns)

• Mechanical / electrical detuning limits performance and increases power demand build fast resonance frequency control system (piezo or magnetostrictive tuning)

• Calibration of signals determines precision (nonlinear effects) build transient detection hardware

• Reference and Distribution determines field stability build long range temperature stable reference system

Fermilab AAC May 11th 7/12

Further Projects

8-channel downconverter boards(already in operation)

Bubble Neutron Dosimetry system w/ automatic readout s/w

Piezoelectric tunerinstalled at one cavity

Box equipped with several field detectors for the rf gun

Transient detection hardware (test setup)

Fermilab AAC May 11th 8/12

DESY's Low Latency Control Boards

• SimCon 2.1• 2004• 2xADCs, 2xDACs• Virtex II FPGA• Successfully tested at

DESY 9-cell teststand (single cavity)

• Successfully tested at A0

• Optical Gigalink 2.0GB/s mezzanine card

• Measured latency: 200ns+160ns!

• SimCon 3.0• 2004• 8xADCs, 4xDACs• Virtex II FPGA• Successfully tested at

DESY 9-cell teststand• Vectorsum Test at

VUV-FEL scheduled for May/June

• Optical Gigalink on board (3.125GB/s)

• Measured latency: 200ns+160ns!

• SimCon 3.1• 10xADCs, 4xDACs• Virtex II Pro FPGA

with 2 PPC405• 2x Optical Gigalink• Schematics finished• Prototypes

expected in July

• SimCon x.x• 128xADCs, 64xDACs• Allows complex control

algorithm• Account for additional

signals

SimCon3.1 Block Diagram:

• DSP C-67• Successor of C-40

(1997-2003)• TI C-67 CPU• In Operation for VS

control since 2004• 8 Gigalink channels • No ADCs/DACs on

board• ~3us

C-67 DSP Board:

SimCon3.0 Board:SimCon2.1 Board:

Fermilab AAC May 11th 9/12

LLRF Plans for A0/SMTF (Present / Short Term)

• Refer to Brian Chase talk

• What we have done already– Commision SimCon 2.1 prototype (1 week in March 05) at A0– Achieved high gain (~100) already– Cleaned up DOOCS control system at A0

• What we plan (short term, May '05 until end '05)– Again set up SimCon 2.1 at A0– Improve calibration of system– Test various algorithms– Establish remote connection DESY FNAL – Update DOOCS control system at FNAL

• DESY support by G. Grygiel, O. Hensler, K. Rehlich

• DOOCS has interface to other systems, e.g. EPICS

Fermilab AAC May 11th 10/12

Tests in March '05

Matlab Control Panel:Feedback Gain in the order of 100

Readout Panel:Top: I and Q (blue) resp. Amplitude and Phase (red) of the CavityBottom: I and Q setpoint curves

Fermilab AAC May 11th 11/12

LLRF Plans for A0/SMTF (Medium / Long Term)

• Refer to Brian Chase talk

• What we plan (medium term, starting from end '05)– Continue support on the DOOCS control system at FNAL– Provide further SimCon systems (SimCon 3.1 to arrive by the end of this

year)– Provide signal detection hardware (downconverters)– Collaboration with FNAL-staff on algorithm development

• What we plan (long term)– Provide and support further SimCon systems– Continue support on the DOOCS control system at FNAL

Fermilab AAC May 11th 12/12

Summary and Outlook

• Based on the successful experience of TTF1 (first machine with VS control) and VUV-FEL, DESY is currently in the process of developing the LLRF control for XFEL

• Development of LLRF control for XFEL already accounts for the requirements of ILC (automation, radiation hardness)

• Demonstrated single cavity control at A0 in March '05• Established collaboration with FNAL for FPGA software

development• Plan to equip SMTF with next revisions of SimCon• As a universal digital control system SimCon is applicable to

many accelerators (in principle it is not restricted to LLRF control only)

Fermilab AAC May 11th 13/12