testing integral and differential non-linearity of adc using servo...
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2007. 6. 29. 제 8 회테스트학술대회1
Testing Integral and Differential Non-Linearity of ADC Using
Servo Loop Solution
Jin-Soo Ko
Teradyne
2007. 6. 29. 제 8 회테스트학술대회2
Overview
• Solution for INL/DNL testing of high-resolution Analog-to-Digital converter (ADC)
• Supported device types– 20-bit parallel – 32-bit serial max.
• Single-ended and differential input signals• Supports multiple data formats
– 1’s Complement, 2’s Complement, Inverted etc.
• Designed for multi-site testing capability– Dedicated Servo Loop Module per DUT – Shared DC Reference Module
2007. 6. 29. 제 8 회테스트학술대회3
Servo Loop Operation
Target Transition
Code 12345
Code 12346
Pedestal level
SAR mode
INT mode
Code Lock and start capture Verror
Verror
Target Level = Pedestal level + Verror
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DC Reference Module:
The DC Reference Module provides – Pedestal Voltage near target code
transition level– Common-Mode voltage for differential
signal– Max +/- 12.5V driving capability
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Common-ModeDAC
PedestalDAC
SCLK_1
PED_DAC
COMMON_DACDIN_2
DIN_1
CS_1
CS_2
SCLK_2
PED_REF
CM_REF
5VReference
5V Reference
DC Reference Module
AGND
+ VS
DGND
-VS
VIN
AGND
+ VS
DGND
-VS
VIN
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DC Reference Stability
DC Reference Module Output over 2 hours
minutes
ΔOutput
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Servo Loop Module:
• The Servo Loop’s makes the main decisions– Updates the input to the ADC based
upon the current output.– Asserts “Code Lock” after the code has
been successfully found.• Driving error voltage between Pedestal
level and SAR DAC through gain amplifier
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Servo Features
• Ability to amplify error voltage and measure it to calculate the transition voltage for the code– Gain of 1, 10, 100, 1000
• Programmable SAR cycles (max. 14)– For initial binary search of transition edge
• Adjustable servo range – +/- (Reference Voltage / 10)– Ref. voltage 1 to 5V
• Programmable integrator step size (max. 15 steps)– Ability to control servo step size during integration
• Ability to “lock on” rising or falling edge
2007. 6. 29. 제 8 회테스트학술대회9
Digitizer
DC Ref. Source Module
SERVO_OUT
SAR/INTDAC
R
R
R
DUT(ADC)
SERVO_ERROR
PGA
MEM_DECR
LOAD_PARAM
TEST_START
CODE_LOCK
DUT_CLOCK
DATA_VALID
Servo Loop & Ref Source
PedestalDAC
SERVO_OUT +
SERVO_OUT -Common-ModeDAC
Target Code
Memory
FPGA
32-bitState
Machine
Servo Loop Module
Max +/- 12.5V
2007. 6. 29. 제 8 회테스트학술대회10
Programming-Software Calibration
• Three calibration factors need to be measured for each code– Pedestal Voltage / Common-Mode Voltage– Composite Offset Error– Composite Gain Error
• The calibration data is stored in a global structure object and written to a file that is later read and accessed when required by the test program.
2007. 6. 29. 제 8 회테스트학술대회11
Calculating code edge voltage
Code transition voltage is calculated from the measured ERROR_OUT voltage and calibration factors as follows.
code transition voltage =
pedestal voltage +
[ (averaged error voltage - offset error) /
{servo error amplifier gain * (1 + gain error)} ]
2007. 6. 29. 제 8 회테스트학술대회12
Test Time Reduction
• Test time reduced by testing a reduced code set– For example, for a 16-bit application 2000 codes are
tested out of a possible 65535 codes• For a 16-bit application test time was reduced to 12
seconds vs. 22 seconds using Ramp INL/DNL• Multi-site test
2007. 6. 29. 제 8 회테스트학술대회13
Typical Performance
Servo Loop Module
Expect code = 33
2007. 6. 29. 제 8 회테스트학술대회14
Linearity Results using Servo Loop Technique
vs.Ramp Histogram Method
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Servo Loop INL
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Ramp Histogram INL
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Servo Loop DNL
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Ramp Histogram DNL
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Code Edge Voltages
16 bits +/- 10v ADC, 2000 codes tested
Zoom in
2007. 6. 29. 제 8 회테스트학술대회20
Code Edge Voltages (Zoomed)
0.3mv /LSB Test 4 codes
Skip 10 LSBs
2007. 6. 29. 제 8 회테스트학술대회21
Application DIB