test set compaction for sequential circuits based on test relaxation

Test Set Compaction for Sequential Circuits

Computer Engineering, KFUPM

Test Set Compaction for Sequential Circuits based on Test Relaxation

M.S Thesis DefenseM.S Thesis DefenseS. Saqib KhursheedS. Saqib Khursheed

Advisor: Dr. Aiman H. El-MalehAdvisor: Dr. Aiman H. El-MalehMembers: Dr. Sadiq M. Sait & Dr. Alaaeldin Members: Dr. Sadiq M. Sait & Dr. Alaaeldin

AminAmin2929thth Dec 04 Dec 04

2



• Motivation

• State of the Art Static Compaction Algorithms

• Test Relaxation Algorithm

• Proposed Algorithms and Experimental Results

• Limitations of Justification algorithm

• Conclusion & Future Work

Outline

3



Motivation

• Compaction is the process of reducing the size of test set while maintaining the fault-coverage.

• To overcome High Complexity of Sequential ATPGs

• To reduce Test Application Time reduced cost!

• To overcome Memory Limitations of the Tester.

4



• Static Compaction Compaction Algorithms are applied as a post-processing step to test generation process.

• Dynamic Compaction Compaction Algorithms are incorporated in test generation process.

• Static Compaction is more useful than Dynamic Compaction in Sequential Circuits.

Types of Compaction Algorithms

5



• Some of the popular algorithms include:– Vector Restoration

• Linear Reverse Order Restoration (LROR)• Radix Reverse Order Restoration (RROR)• SIngle FAult Restoration (SIFAR)• Mixed Mode (MISC)• SECO

– Subsequence Merging– State Traversal based on Relaxed States

State-of-the-art Static Compaction Algorithms

6



LROR

Snapshot of algorithm under execution

Targeting f1 and f2. Restoring vector #6 doesn’t detect the fault

Targeting f1 and f2. Restoring vector # 5 and 6, doesn’t detect the faults

Restoring vector # 4, 5 and 6, detects the fault f1 and f2.

f1 and f2 detected

Restored vector # 4, 5 and 6, are concatenated with previously restored test vectors .

7



State-Traversal

8



Important Attributes of Static Compaction Algorithms

• Test sequences for Hard-to-Detect faults (HTDF) can easily detect Easy-to-Detect faults (ETDF).

• State Traversal eliminates redundant vectors

• Merging of relaxed Subsequences adds another level of freedom to test compaction.

• Increasing the Fault coverage fuels compaction.

9



• Restoration algorithms rely on vector-by-vector fault simulation to extract the test sequence.

• Recently, an efficient Test Relaxation technique has been proposed to extract the necessary assignments for detecting the faults.

• Our algorithms (discussed next) rely on test relaxation algorithm for extracting the self-initializing subsequence.

• A relaxed test set facilitates Subsequence Merging and State Traversal.

Test Relaxation Algorithm

10



Proposed Algorithms

• Following algorithms are proposed:– Linear Reverse Order Restoration

• with State Traversal

• with State Traversal-2

– Merging Restoration– Hybrid Schemes

• Hybrid-I

• Hybrid-II

– Fault-Coverage based Compaction• FC-LROR

• FC-MR

11



Reverse Order Restoration with State Traversal using Relaxed Test Set

After first pass of fault simulation, information is stored

Justification of faults f4, f5. Self-initialized subsequence is found by relaxation algorithm.

f4 and f5 detected

State Traversal may further reduce the size of subsequence

Re-current states, removal of time frames is possible

f4 and f5 detected

Start from last time frame having un-justified fault.

f4 and f5 detected

Reduced subsequence

12



Reverse Order Restoration with State Traversal using Relaxed Test Set

Fault Simulate the subsequence and drop all the faults detected

f4, f5, f1 and f2 are detected

Dropping detected faults leaves f3

The above steps are repeated Fault # 3 is justified.

Concatenation with previously justified test vectors.Test Set after Compaction detecting all the faults.

0/1

1/x

1/0

0/x

1/x

x/0

13



Motivation behind ST-2STRATEGATE Test Sequences

LROR LROR-ST

Ckt TS TS (sec) TS (sec)

s298 194 152 (0.06) 134 (0.06)

s344 86 44 (0.03) 44 (0.09)

s641 166 133 (0.07) 157 (0.11)

s713 176 115 (0.07) 134 (0.1)

s820 590 469 (0.27) 466 (0.39)

s832 701 534 (0.31) 470 (0.42)

s1196 574 268 (0.3) 268 (0.35)

s1238 625 268 (0.33) 268 (0.37)

s1488 593 466 (0.56) 479 (0.71)

s1494 540 453 (0.52) 401 (0.7)

s5378 11481 760 (45.34) 726 (45.34)

s35932 257 131 (20.8) 131 (21.12)

Total (sec) 15983 3793 (68.66) 3678 (69.76)

14



• Merging algorithm follows the same flow as the previous algorithm.

• Instead of concatenation of subsequences, relaxed subsequences are merged with previously restored subsequences.

• Merging towards bottom

• Merging towards top

Merging Restoration

15



11xx

0x01

10x1

xxx0

00x1

11xx

1011

11x0

001x

Compact Test Set Newly Restored Subsequence

XX

11xx

0x01

1011

11x0

0011

11xx

Merged Subsequence

Merging towards Bottom

16



Exp. ResultsSTRATEGATE Test Sequences

ITE ITE

LROR [14] MR LROR LROR-ST LROR_ST2 LROR [14] LROR_ST2

Ckt TS TS (sec) TS (sec) TS (sec) TS (sec) TS (sec) TS (sec) TS (sec)

s298 194 138 (0.14) 154 (0.05) 152 (0.09) 134 (0.06) 152 (0.11) 112 (0.74) 152 (0.15)

s344 86 62 (0.09) 61 (0.04) 44 (0.1) 44 (0.09) 44(0.1) 51 (0.18) 44 (0.13)

s641 166 118 (0.13) 148 (0.59) 133 (0.07) 157 (0.11) 119 (0.17) 117 (0.32) 118 (0.56)

s713 176 139 (0.16) 140 (0.54) 115 (0.07) 134 (0.1) 112 (0.25) 103 (0.61) 111 (0.49)

s820 590 489 (0.79) 531 (3.11) 469 (0.64) 466 (0.39) 456 (0.59) 471 (1.94) 428 (1.96)

s832 701 543 (0.89) 568 (3.31) 534 (0.45) 470 (0.42) 498 (0.6) 443 (4.5) 460 (2.28)

s1196 574 277 (0.28) 242 (1.79) 268 (0.59) 268 (0.35) 268 (1.17) 260 (1.2) 266 (1.21)

s1238 625 285 (0.31) 248 (2.18) 268 (0.62) 268 (0.37) 268 (1.23) 270 (1.09) 266 (1.64)

s1488 593 501 (1.79) 533 (5.38) 466 (0.56) 479 (0.71) 453 (1.01) 474 (14.89) 423 (4.0)

s1494 540 468 (1.71) 501 (4.82) 453 (0.67) 401 (0.7) 434 (0.88) 422 (21.92) 434 (2.39)

s5378 11481 677 (38.71) 1549 (227.57)760

(45.34)726

(45.34) 710 (51.8) 585 (71.55) 703 (74.46)

s35932 257 137 (56.93) 188 (389.7) 131 (20.8)131

(21.12) 131 (22.5) 137 (119.76)125

(128.66)

Total (sec) 15983 3834 (101.9) 4863 (639.1)3793

(68.66)3678

(69.76)3645

(80.41) 3445 (238.7)3530

(217.95)

Better 3 9 10 9 5

17



Merging RestorationNumber of SS restored MR LROR-ST2

Ckts # of SS # of SS

s298 8 6

s344 18 6

s641 65 9

s713 72 15

s820 87 29

s832 88 25

s1196 192 147

s1238 207 150

s1488 65 16

s1494 62 16

s5378 132 49

s35932 35 7

Total 1031 475

18



Hybrid Schemes

• LROR suffers from quick saturation.

• Hybrid schemes are proposed to address this limitation of LROR.

• Hybrid-I uses Test Relaxation and random filling to change the composition of the test.

• This helps moving the algorithm out of local-minima and search space is therefore increased.

19



Hybrid Schemes

LROR-ST2

2+

Test Relaxation

3+Hybrid-I

20



Hybrid Schemes

Hybrid-I

Hybrid-II

MR

1+

21



Hybrid Schemes STRATEGATE Test Sequences ITE ITE ITE ITE ITE

LROR [12] SIFAR [13] MISC [12] Hyb-I Hyb-II

Ckt TS TS (sec) TS (sec) TS (sec) TS (sec) TS (sec)

s298 194 125 (0.6) 112 (0.4) 98 (3.2) 106 (0.96) 89 (1.16)

s344 86 47 (0.1) 48 (0.2) 43 (0.4) 48 (0.26) 48 (0.31)

s641 166 78 (0.5) 87 (0.4) 63 (1.7) 68 (1.48) 68 (1.64)

s713 176 72 (0.6) 94 (1.1) 60 (0.8) 64 (1.37) 64 (1.54)

s820 590 394 (6.4) 388 (6.5) 335 (15.2) 377 (18.1) 376 (22)

s832 701 458 (8.8) 435 (4.5) 368 (14.0) 418 (18.9) 406 (24.3)

s1196 574 221 (1.7) 237 (3.4) 216 (3.2) 213 (37.4) 182 (41.5)

s1238 625 222 (2.6) 251 (1.5) 222 (3.6) 222 (33.1) 196 (36.6)

s1488 593 343 (27.1) 312 (8.8) 364 (39.4) 362 (17.4) 361 (24.5)

s5378 11481 711 (339.4) 597 (89.5) 583 (2148) 637 (307.4) 637 (383.7)

s35932 257 110 (752.3) 152 (290) 101 (1177) 133 (875.76) 133 (1002.7)

Total (sec) 15443 2781 (1140.1) 2713 (406.3) 2453 (3406.5) 2648 (1326.6) 2560 (1539.9)

71

81

21

8 8

1

4 6

5

Better

Equal

22



HITEC Test Sequences ITE ITE ITE ITE

LROR [12] MISC [12] Hyb-I Hyb-II

Ckt TS TS (sec) TS (sec) TS (sec) TS (sec)

s298 322 109 (0.8) 97 (1.1) 161 (0.87) 143 (0.98)

s344 127 47 (0.1) 47 (0.5) 45 (0.5) 45 (0.53)

s641 209 63 (1.0) 72 (1.2) 66 (2.15) 66 (2.28)

s713 173 74 (0.7) 74 (1.0) 71 (1.6) 71 (1.77)

s820 1115 578 (13.8) 432 (28.3) 489 (24) 488 (27.4)

s832 1137 562 (8.3) 383 (64.0) 497 (17.7) 493 (20.5)

s1196 435 226 (2.3) 223 (2.5) 214 (35.6) 187 (38.8)

s1238 475 227 (1.9) 225 (1.9) 218 (42.7) 184 (51.8)

s1488 1170 571 (10.4) 572 (354.6) 650 (40.4) 648 (49.6)

s5378 912 245 (108.1) 271 (189.0) 262 (90.8) 262 (107.3)

s35932 496 142 (227.8) 117 (1158) 187 (1020.8) 145 (1379.6)

s3271 709 555 (24.6) 443 (265.0) 682 (54.6) 369 (103.2)

s3384 161 104 (11.6) 92 (13.1) 104 (17.3) 75 (20.1)

s4863 518 302 (20.5) 315 (25.6) 272 (379.8) 133 (430.1)

Total (sec) 7959 3840 (431.9) 3363 (2105.8) 3918 (1728.9) 3309 (2233.6)

Hybrid Schemes

71

69 9 10

4

Better

Equal

23



• Motivation: A large reduction in test size is possible by increasing the fault coverage of currently restored subsequences.

• This is achieved by relaxing and randomly filling the restored SS.

• Fault coverage (FC) based compaction:– LROR based on increasing the FC FC-LROR– MR based on increasing the FC FC-MR

Fault-Coverage based Compaction

24




IDEA

LROR

FC-LROR

25



FC-LROR

Currently Compacted Test New SS

Test Relaxation

Yes

EndNoUnd Faults?

n

26



FC-MR

Fully SpecifiedNew SS

Random Filling &Test Relaxation

Yes

EndNoUnd Faults?

n

Test Relaxation for all und. faults

Merging towards Top

Currently Compacted Test

27



Exp. Results: FC-based Compaction

HITEC Test Sequences

Ckt TS SECO [37] SIFAR [13] LROR [12] FC-LROR MR FC-MR MISC [12]

s298 322 216 129 169 157 207 175 139

s344 127 61 50 47 47 69 59 48

s641 209 125 112 105 88 158 81 102

s713 173 106 93 89 77 129 72 88

s820 1115 790 599 598 574 863 709 496

s832 1137 779 597 605 568 879 694 484

s1196 435 281 256 251 250 255 213 252

s1238 475 303 272 266 263 269 228 267

s1488 1170 828 613 647 705 911 711 643

s1494 1245 855 640 630 668 974 781 605

s5378 912 653 456 300 330 706 357 292

Total 7320 4997 3817 3707 3727 5420 4080 3416

Better

Equal

All 4 4 4AllAll 8 7

1

5All 7

28



Exp. Results: FC-based Compaction

STRATEGATE Test Sequences

Ckt TS LROR [14] SIFAR [13] LROR [12] MR FC-MR FC-LROR MISC [12]

s298 194 138 116 125 154 141 150 123

s344 86 62 48 47 61 50 41 44

s641 166 118 87 91 148 79 101 74

s713 176 139 125 112 140 87 86 92

s820 590 489 423 401 531 497 392 356

s832 701 543 511 475 568 509 465 375

s1196 574 277 251 234 242 199 241 234

s1238 625 285 251 244 248 212 245 244

s1488 593 501 390 363 533 591 433 370

s1494 540 468 408 417 501 460 413 417

s5378 11481 677 597 734 1549 809 608 704

Total 15726 3697 3207 3243 4675 3634 3175 3033

Better 7 5 4 10 3710 6 6 4All

29



Hybrid-FC-LROR

FC-LROR MR

1+2+

30



Exp. Results: Hybrid-FC-LRORSTRATEGATE Test Sequences

Circuit TSITE

LROR [12]

ITE SIFAR [13]

ITE MISC[12

]

ITE Hyb-FC-

LROR

S298 194 125 112 98 95

S344 86 47 48 43 38

S641 166 78 87 63 59

S713 176 72 94 60 45

S820 590 394 388 335 347

S832 701 458 435 368 366

S1196 574 221 237 216 180

S1238 625 222 251 222 192

S1488 593 343 312 364 380

S1494 540 297 313 296 362

S5378 11481 711 597 583 561

Total 15983 2968 2874 2648 2625899Better

31



Exp. Results: Hybrid-FC-LRORHITEC Test Sequences

ITE ITE ITE

Ckt TS LROR [12] MISC [12] Hyb-FC-LROR

s298 322 109 97 96

s344 127 47 47 44

s641 209 63 72 60

s713 173 74 74 57

s820 1115 578 432 403

s832 1137 562 383 379

s1196 435 226 223 182

s1238 475 227 225 188

s1488 1170 571 572 586

s1494 1245 540 492 462

s5378 912 245 271 215

s3271 709 555 443 351

s3330 578 219 218 188

s3384 161 104 92 56

s4863 518 302 315 136

Total 9286 4422 3956 3403

32



Limitations of Justification Algorithm

• Justification of G/F value is done based on cost functions, which is an approximate method.

• Cost of Good value is only used.

• These limitations result in extraction of longer test sequences than necessary.

33



Conclusion & Future Work

• In this work, we have proposed several efficient static compaction techniques, which achieve the following:– Better or comparable level of compaction while reducing the

runtime.

– All important attributes of static compaction techniques are integrated.

– Limitation of quick saturation of Restoration based techniques has been addressed.

– A new class of compaction algorithms has been introduced, based on increasing the fault-coverage of restored subsequences.

34



Conclusion & Future Work

• Investigate techniques to overcome the limitations of Justification Algorithm.

• Investigate techniques for increasing the fault coverage of an extracted Subsequences.

35



Thank you!Q & A

36



Backup Slides

37



• Unique opportunities provided by Static Compaction:– It may be applied to test vectors generated by any

ATPG tool without modifying the test generation process.

– It may be applied after dynamic compaction.– It takes lesser time to get final test set.– The shortest test sequence for sequential circuits are

generated by static compaction techniques.• For these reasons, Static Compaction is more popular in

Sequential circuits than Dynamic Compaction.

Types of Compaction Algorithms

38



Modified LROR

39



• SIFAR uses the basic idea of Test Vector Restoration.

• It considers a single target fault (in decreasing order of detection time) and restores test vectors until fault is detected.– This is also called Test Vector Restoration.

• SIFAR uses parallel fault simulator to speed up the restoration process.

State-of-the-art Static Compaction Algorithms (SIFAR)

40



SIFAR

Targeting f1. Restoring vector #6 doesn’t detect the faultTargeting f1. Restoring vector # 5 and 6, doesn’t detect the fault

Restoring vector # 4, 5 and 6, detects the fault f1.

F1 detected

Restored vector # 4, 5 and 6, are concatenated with previously restored test vectors .


41



• RROR is a variation of LROR, meant to speed up the restoration process.

• In RROR, rather than restoring frame by frame, the algorithm jumps to previous time frames.

• Radix Search is based on binary search and depends on the value of ri-1, such that, 1< r ≤ 2 and i=1,2,3..

• The algorithm keeps jumping until the target fault(s) is detected.

State-of-the-art Static Compaction Algorithms (RROR)

42



RROR


Targeting f1 and f2. Restoring vector #9 doesn’t detect the fault. r=2, i=1

Restoring vector # 7, 8 and 9, doesn’t detect the fault f1 and f2. r=2, i=2

f1 and f2 detected

Restoring vector # 3, 4, 5 and 6, detects the faults f1 and f2.

r=2, i=3

Restored vector # 3, 4 … 9, are concatenated with previously restored test vectors .

43



• A newly restored subsequence may be merged with previous subsequences either towards Top or Bottom or from where the savings are highest.

• Merging towards bottom starts from top and slides the newly restored SS downwards until merged or appended.

• Merging towards TOP starts from Bottom and slides the newly restored SS upwards until merged or appended

Merging Restoration

44




• Observations: Initially restored test sequences cover a large number of faults. This is called covering effect, which is used by Restoration based compaction algorithms.

• Motivation: A large reduction in test size is possible by increasing the fault coverage of currently restored subsequences.

test set compaction for sequential circuits based on test relaxation

Documents