Team DataPath ResearchComputer Architechture

PC and IF in the Processor

Program Counter &Instruction FetchPC Instruction address registerIncrements after fetch to read next instructionJumps, branches, subroutines, & returnsInstruction FetchCopies the address in the PC into the IRRetrieves the instruction content from memory

PC & IF Inputs and OutputsInputsInstruction MemoryIncrementorControl LineOutputsDatabus to Instruction Decode

Instruction TypesR-Type (Register Only)I-Type (Immediate Value)J-Type (Jump)

The Register File!What is it?Contains all 32 registers; some available to the programmerRegisters are designated using 5 of the bits in the instructionEach register contains 32 bits of informationWhat does it do?Controls the flow of information to or from registersReads two registers at a time and writes to oneReceives a control bit for knowing when to writeReads from registers on the positive edge of the clock cycle and writes to a register on the negative edge

The Register File!Lets learn how to read!From Computer Organization & Design: The Hardware/Software InterfaceThe 5 bits determining the registers are used to control a Mux that picks from 32 registers. (5 bits = 32 distinct bit sequences)Data is passed along to the ALU.This all happens when either the "Write" (from Figure B.8.8) is on or off and during the rising edge of the clock cycle.

The Register File!How about writing?Register number is determined in the decoder which, when ANDed with "Write", sets that register to have it's data overwritten.The data being written is coming from the ALU on a 32 bit bus connected to each register.Performs the write to the register when the clock cycle has a negative slope.From Computer Organization & Design: The Hardware/Software Interface

The Register File!Going a little deeper...Implementation:RegistersEach bit of a register can be made up of D-Flip FlopThe D signifies the data that is being inputted.Q is the output, where the bit is read fromWritingUses 32:1 Mux for toggling the appropriate registerANDs this signal with the RegWrite control signal to enable writing to registerA 32 bit bus is attached to each registerReadingA 32x32 to 32 Mux must be used. This type of Mux chooses between 32 registers with 32 bits each and outputs the 32 bits of the chosen register designated in 5 bits in the instructionOne method of implementing this is to use 32, 32 to 1 Multiplexers

D-Flip FlopFrom physicsforums.com

The ALU and You!Fig 4.2 Computer Organize and Design

Fun FactsWhat is an alu?Main brain Mclain of the PLP ArchitectureCombination of Adders and Logic GatesWhat does it do?Performs Mathmatical and Logical OperationsWhy do we need it?Allows us to process Data in a multitude of ways

3 ALUs within PLP Architecture.PC incrementationBranching InstructionsR and I-type Arithmetic and Logical Instructions

ALU R-type Instruction ExampleFrom PLP wiki

Simple Data PathFig. 4.11 Computer Organize and DesignI-typeR-typeBranching

Oh It makes senseFunction determined by Control

ALU gives us POWAHCan do process data in a multitude of ways

Mux, Sign Extension, Logical Shift, and Branching and JumpingMux (Multiplexer)It is used anytime you need to make adecisionbetween multiple inputsSign ExtensionIt is used to keep a number value the same but have the number take up more bitsLogical ShiftIt is used to move theinformationin a word to right or leftBranching and JumpingThey are used to move from one line of code to another

Inputs and OutputsMux, Sign Extend and Logical ShiftMux 3 inputs and 1 output Sign Extend In this example there are 16 inputs and 32 outputs Logical Shift In this example there are 8 inputs and outputs The number of outputs will always equal the number or inputs

Where They Fit InMux, Sign Extension, and Logical ShiftMux, Sign Extend and Logical ShiftThese are all used many times in the mips architecture and they can be used or placed anywhere one of these operations is needed

Branching and JumpingBranching (Orange) and Jumping (Blue)They take many inputs form many different parts of the architecture and it outputs back to the program counter

The Memory

The Memory: StructureBlue lines: control signals (MemWrite, MemRead)Black lines: 32-bit values (Address, Write data, Read data)It is a 232x32 memory

If the data memory is to be read =>MemRead=1 (the active signal)MemWrite=0If the data memory is to be written =>MemRead=0MemWrite=1 (the active signal)

Address?Write data?Read data?

The instructionsR-type instruction, add, sub, and, or, slt... MemWrite and MemRead are set to 0,Memory doesnt have to do anything. Branch instructions,MemWrite and MemRead are set to 0,Memory doesnt have to do anything.

Lw instruction,MemWrite is set to 0 and MemRead to 1.Need to compute the effective address =>sign extend.ALUOp should be ADD (010).ALUSrc fixed to 1. Complete address in its line => value wanted at Read data Sw instruction,MemRead is set to 0 and MemWrite to 1.Need to compute the effective address => sign extend.ALUOp should be ADD (010).ALUSrc fixed to 1. We put the data in the Write data => value saved at the specified address

Two New Instructions

Variable Logical Shift Left (sllv)Purpose: shift left by a number of bits that is unknown to the programmer. The shift is stored in a register instead of in an immediate value.Variable Logical Shift Right (srlv)Purpose: shift right by a number of bits that is unknown to the programmer. The shift is stored in a register instead of in an immediate value.

Two New Instructions Cont.

Current implementation example: li $t0 5 loop: slli $t1, $t2, 0x1 subi $t0, $t0, 1 // value shift counter bne $t0,$Zero,loopExample with new instructions sllv $t1, $t2, $t0 This saves 3n-2 instructions.

Wrap-UpResearch will enable code implementation of a PLP-architecture processor.The hardware will comprise all five stages of the processor.Behavioral Verilog code will "construct" the processor within an FPGA. Questions?