tea 5764

* Philips Semiconductors* Composed by: D. Janta, W. Brummelman* Comm. No.: TEA5764* Type: N53370* Version: 2.7

Preliminary IC Specification V2.7 - TEA5764

CONFIDENTIAL

Accepted: IPM Dept. Date: 2004 Nov 09

Page: 1

NECTAR-R

TEA5764

FM-RADIO + RDS

Author: Wim-Jan BrummelmanDate: 2004 Nov 09Reference Number: RNB-C/2631/2004XI-1545Version: 2.7Status: Approved

VERSION: CHANGES: DATE AUTHOR

1.1 - 6 feb 2003 WJ Brummelman

1.3 - 1 apr 2003 WJ Brummelman

1.4 see chapter 23 revision history 9 apr 2003 WJ Brummelman

2.0 Upgraded to V2.0, see chapter 23 revision history 4 jul 2003 WJ Brummelman

2.1 Updated SWPORT output, see chapter 23 revision history 10 jul 2003 WJ Brummelman

2.2 see chapter 23 revision history 28 jan 2004 WJ Brummelman

2.4 added Chip Scale Package pinning and die size information 04 feb 2004 WJ Brummelman

2.5 see chapter 24 revision history 03 jun 2004 WJ Brummelman

2.6 see chapter 24 revision history 04 jun 2004 WJ Brummelman

2.7 see chapter 24 revision history 09 nov 2004 WJ Brummelman

CONTENTS

1 FEATURES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 ELECTRICAL PARAMETERS GENERAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 FM / RDS OVERALL SYSTEM PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 ORDERING INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

6 FIGURE 1: BLOCKDIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

7 PINNING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8.1 Low Noise RF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128.2 FM Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128.5 PLL Tuning System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128.6 Band Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.7 RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.8 Local / DX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.9 IF Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.10 FM Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.11 IF Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.12 Level Voltage Generator and Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.13 Softmute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138.14 Hard Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.15 Audio Frequency Mute - AFM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.16 MPX Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.17 Signal depending Mono/Stereo Blend (Stereo Noise Cancellation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.18 Software Progammable Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.19 Stand-By . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.20 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.21 RDS/RBDS Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148.22 RDS Data and Clock Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158.23 RDS/RBDS Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158.24 Audio Pause Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158.25 Autosearch and preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158.25.1 Auto Hi-Lo side injection stop switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158.25.2 Muting during search or preset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168.26 RDS update / Aternative Frequency Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188.26.1 Muting during RDS update.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9 INTERRUPT HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.1 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209.1.1 Interrupt clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209.1.2 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209.1.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209.1.4 Interrupt flags and behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229.1.4.1 Multiple interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229.1.4.2 Data available: DAVFLG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229.1.4.3 RDS synchronisation: LSYNCFL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229.1.4.4 IF Frequency: IFFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229.1.4.5 RSSI threshold: LEVFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239.1.4.6 Pause Detection: PDFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239.1.4.7 Frequency ready: FRRFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25


CONFIDENTIAL

Date: 2004 Nov 09

Page: 2

9.1.4.8 Band limit: BLFLAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259.2 Interrupt Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

10 RDS DATA PROCESSING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

10.1 DAV-A Processing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2710.2 DAV-B Processing mode / Fast PI search mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2810.3 DAV-C Reduced Processing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2910.4 Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010.4.1 Conditions for synchronisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010.4.2 Data Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3010.5 RDS Flag behaviour during read action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3110.6 Error detection and reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210.7 RDS test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3210.8 RDS data - Reading from the registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

11 CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

11.1 I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

12 REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12.1 Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3512.2 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

13 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

14 AC / DC CHARACTERISICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

15 LIMITING VALUES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

17 PACKAGE OUTLINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

18 OUTLINE-WFBGA34-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

19 SOLDERING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

19.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6019.2 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6019.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6019.4 Manual soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6019.5 Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . . . . . . . . . . 61

20 DATA SHEET STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

21 DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

22 DISCLAIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

23 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

24 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65


CONFIDENTIAL

Date: 2004 Nov 09

Page: 3

1 FEATURES

• Chip Scale Package

• High sensitivity due to integrated low noise RF input amplifier

• FM mixer for conversion of the US/Europe (87.5MHz to 108MHz) and Japanese FM band (76 MHz to 90MHz) to IF

Preset tuning to receive Japanese TV audio up to 108MHz, raster 100kHz

• RF Automatic Gain Control circuit

• LC tuner oscillator operating with low cost fixed chip inductors

• Fully integrated FM IF selectivity

• Fully integrated FM demodulator, no external discriminator

• Crystal reference frequency oscillator. The oscillator operates with a 32768Hz clock crystal.

• PLL synthesizer tuning system

• IF counter, 7 bit output via bus

• Level detector, 4 bit level information output via the bus

• Soft mute

• Signal depending mono/stereo blend (SNC, stereo noise canceling)

• Soft mute, SNC can be switched off via the bus

• Adjustment free stereo decoder

• Autonomous search tuning function

• Stand-by mode

• MPX output

• One software programmable port

• Fully integrated RDS/RBDS demodulator in accordance with EN50067

• RDS/RBDS decoder with memory for two RDS data blocks provides block synchronization and error correction.Block data and status information are available via the I2C-bus.

• Audio Pause Detector

• Interrupt flag

• Suitable for automotive temperature range with supply voltages of 5Volt

2 GENERAL DESCRIPTION

The TEA5764 is a single chip electronically tuned FM stereo radio with RDS/RBDS demodulator and RDS/RBDSdecoder for low voltage application with fully integrated IF selectivity and demodulation.The radio is completely adjustment free and does only require a minimum of small and low cost external components.The radio can tune the European-, US- and Japan FM bands. The Radio does not meet all of the requirements fromEN55020 a trade off was done to make possible the previously stated features. The IC is available in HVQFN packageand in Chip Scale Package.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 4

3 ELECTRICAL PARAMETERS GENERAL

NOTE: The listed parameters are valid when a crystal is used which meets the requirements as stated in chapter 14AC/DC Characteristics.

NR SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

G1 VCC analog supply voltage at pin 34 2.5 2.7 3.3 V

G2 ICC analog supply current pin 34 10 13.7 18 mA

G3 ICCSB stand-by supply current pin 34 0 1.0 5.0 µA

G4 VDD digital supply voltage at pin 15 2.5 2.7 3.3 V

G5 IDD digital supply current pin 15includes RDS current (page 52)

0.3 0.7 1.5 mA

G6 IDDSB digital stand-by current pin 15 10 18 25 µA

G8 VVREFDIG Digital Reference Voltage forBus-interface

VVREFDIG <= VDD 1.65 1.8 VDD V

G9 IVREFDIG digital pin reference current pin 9 Nominal, VVREFDIG=1.8V 0 0.5 1 µA

G10 fFMant FM input frequency 76 − 108 MHz

Tamb operating ambient temperature VDD, VCC =2.7VVVREFDIG=1.8V

−20 − +85 °C


CONFIDENTIAL

Date: 2004 Nov 09

Page: 5

4 FM / RDS OVERALL SYSTEM PARAMETERS

5 ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VRF Sensitivity EMF value fRF= 76 to 108MHz∆f=22.5kHz, fmod = 1kHz(S+N/N)=26dB,deemphasis = 75µs, L=RBAF= 300Hz to 15kHz

2 3.5 µV

IP3in inband 3rd-order intercept pointrelated to V36-37 (peak value)

∆f1=200kHz, ∆f2=400kHzftuned = 76 to 108MHz

81 87 dBµV

IP3out outband 3rd-order intercept pointrelated to V36-37 (peak value)

∆f1=4MHz, ∆f2=8MHzftuned = 76 to 108MHz

87 93 dBµV

S-200 low side 200kHz selectivity ∆f=-200kHzfRF = 76 to 108MHz

32 36 dB

S+200 high side 200kHz selectivity

low side and high side selectivitycan be switched by changing themixer from high side to low sideLO injection

∆f=+200kHzfRF= 76 to 108MHz

39 43 dB

VoutL,VoutR L-, R audio output voltage VRF= 1mV, L=R,∆f=22.5kHz, fmod = 1kHzdeemphasis = 75µs

60 75 90 mV

(S+N/N) maximum signal-to-noise ratio fRF= 76 to 108MHzVRF= 1mV, L=R∆f=22.5kHz, fmod = 1kHzdeemphasis = 75µsBAF= 300Hz to 15kHz

56 59 dB

αsep stereo channel separation VRF= 1mV, R=1,L=0 orR=0, L=1,fmod=1kHz,∆fpilot=6.75kHz,∆fL=67.5kHz, ∆fR=0 or,∆fR=67.5kHz, ∆fL=0

27 33 dB

THD total harmonic distortionmeasured at pins VAFL, VAFR

VRF= 1mV, L=R, ∆f=75kHz,fmod = 1kHz, no pilot,deemphasis = 75µs

0.4 0.9 %

VinRF RDS Sensitivity EMF value ∆f=22.5kHz, fAF = 1kHz,L=R, ∆fRDS=2kHz,deemphasis = 50µs,Block Quality Rate >= 95%SYM_1=0 and SYM_0=0

12 18 µV

TYPENUMBER

PACKAGE

NAME DESCRIPTION VERSION

TEA5764HN HVQFN40 plastic micro leadframe package;40 leads; body 6× 6 × 0.9 mm SOT618AB1

TEA5764UK WL-CSP Chip Scale Packaging / Flip-Chip; 34 bumps; die size 4 x 4 x 0.4 mm WFBGA34-2


CONFIDENTIAL

Date: 2004 Nov 09

Page: 6

6 FIGURE 1: BLOCKDIAGRAM

note: total of 23 external components including xtal and 12pF capacitor connected to pin 33

FM

AN

T

33n

27p

LEFT

RIGHT

CLO

CK

DA

TA

MPXOUT

32.7

68kH

z32

9

2928

2726

25

17

10

181920

2223

1st F

MI/Q

-MIX

ER

: 2 N1

IF F

ILT

ER

LIM

ITE

R

LEV

EL

DE

MO

D

GA

INS

TA

BI

IF C

OU

NT

MPX DECODER

SDS

I2C

Bus

VC

O

Pilo

t

Iref

IF C

ente

rF

req.

Adj

ust

AD

C TE

A57

64H

NA

GC

SW

PO

RT

3031

MU

X

Pro

g. d

iv o

ut

Ref

. div

out

33n

XT

AL

Mon

o16 12 11

SO

FT

MU

TE

24

47p

100p L1

33n

33n

47kΩ

D1

D2

L3L2

34

n.c.

33 34 35 36 37 38

n.c.

57kH

z B

P F

ILT

ER

RD

S/R

BD

SIN

TX

INT

ER

FA

CE

RE

GIS

TE

R

DE

CO

DE

R

BUSENABLE

optio

nal i

nput

for

VREF DIG

n.c

.

intc

on1

SWPORT

8

VD

D12

Ω

33n

76

5

VC

C

33n

3.7Ω

33n

MPXIN

intc

on2

CD

3

21 131415

n.c.

Pau

seD

etec

tor

OS

C

TU

NIN

G S

YS

TE

M

+

10n

33n

12 10

0kΩ

10kΩ

10n

40n.

c.

n.c.

39

12pF

X1


CONFIDENTIAL

Date: 2004 Nov 09

Page: 7

Paulo

Highlight

Table 1 List of components

SYMBOL PARAMETER TYPE MANUFACTURER

D1,D2 varicap for VCO tuning BB202 Philips

L1 RF band filter coil 120nH, 0603CS series or equivalentQmin = 20, tolerance: +- 5%

Coilcraft, Murata

L2,L3 VCO coil 33nH, 0603CS series or equivalentQmin = 40, tolerance: +- 2%

Coilcraft,Murata

X1 32.768KHz Crystal see section 14 AC/DC characteristics

R 10k, 47k, 100k +- 10% max

C 12p, 27p, 47p, 100p, 10n(2x),33n(8x)

+- 10% max


CONFIDENTIAL

Date: 2004 Nov 09

Page: 8

7 PINNING

SYMBOL PIN WL-CSPposition

DESCRIPTION

LOOPSW 1 A1 Switch output of synthesizer PLL loop filter

CPOUT 2 B2 charge pump output of synthesizer PLL

LO1 3 A2 Local oscillator coil connection

LO2 4 A3 Local oscillator coil connection

CD1 5 A4 VCO supply decoupling capacitor

RDSLP 6 B4 RDS loop filter

SWPORT 7 A5 software programmable port

BUSENABLE 8 A6 Bus enable

VREFDIG 9 B6 Digital reference for bus signals

CLOCK 10 A7 Bus clock line input

DATA 11 B7 Bus data line input/output

NC1 12 - not connected

DGND 13 C7 digital ground

DGND 14 D6 digital ground

VDD 15 D7 Digital supply voltage

CD2 16 E7 VDD decoupling capacitor


INTCON2 18 E6 internally connected

DGND 19 F7 digital ground

INTX 20 G7 Interrupt pin


INTCON1 22 F6 internally connected

TMUTE 23 G6 time constant for soft mute

VAFR 24 G5 Right audio output

VAFL 25 F4 Left audio output

MPXOUT 26 G4 FM demodulator MPX output

MPXIN 27 G3 MPX decoder and RDS decoder MPX input

DGND 28 G2 digital ground, this pin has an internal pull-down resistor of 10 kΩ toground.


AGND 30 F2 Analog ground


FREQIN 32 G1 input for 32.768kHz reference frequency

XTAL 33 F1 crystal input crystal oscillator

VCC 34 E1 Analog supply voltage

CD3 35 D2 VCC decoupling capacitor

RFIN1 36 D1 RF input1

RFIN2 37 C1 RF input2

RFGND 38 C2 RF ground

CAGC 39 B1 time constant RF AGC



CONFIDENTIAL

Date: 2004 Nov 09

Page: 9

Fig.2 HVQFN40 Pin configuration - Topview

CP

OU

T

RFIN2

RFGND

RFIN1

AG

ND

XTAL

CAGC

CD3

RD

SLP

BU

SE

NA

BLE

DATA

CLO

CK

DGND

NC1

INTX

INT

CO

N1

1 2 3 4 5

TEA5764HN

30

6 7 8 9 10

32

31

11

12

13

14

15

16

17

18

19

20

212223242526272829

33

34

36

35

38

37

39

40

VAF

R

TM

UT

E

VAF

L

MP

XIN

MP

XO

UT

DG

ND

NC2

NC

3

FREFIN

VCC

NC

4

VR

EF

DIG

CD2

LO1

LO2

CD

1

SW

PO

RT

VDD

DGND

INTCON2

LOO

PS

W

NC5

NC6

DGND


CONFIDENTIAL

Date: 2004 Nov 09

Page: 10

Paulo

Highlight

Fig.3 WLP-CSP pin layout bottom view, the die has a laser marking on the backside. The lasermarking marks pinA1, see also chapter 18.

4000 µm

4000

µm

500 µm

500 µm

1 2 3 4 5 6 7

G

F

E

D

C

B

A


CONFIDENTIAL

Date: 2004 Nov 09

Page: 11

8 FUNCTIONAL DESCRIPTION

8.1 Low Noise RF Amplifier

The LNA input impedance together with the LC RF input circuit defines an FM band filter. The gain of the LNA iscontrolled by the RF AGC circuit.

8.2 FM Mixer

FM quadrature mixer converts FM RF (76 to 108 MHz) to IF.

8.3 VCO

The varactor tuned LC VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer. The VCO frequencyrange is 150MHz to 217MHz.

8.4 Crystal Oscillator

The crystal oscillator can operate with a 32.768kHz clock crystal, with a high performance as specified in chapter 14. Theosillator can be overruled via the FREFIN pin. When the FREFIN pin is used the oscillator is clocked externally with a32.768kHz, signal. Selection between a reference clock or a reference crystal can be done via the bus. When a crystalis connected the FREFIN pin must be left open and when the FREFIN pin is used a crystel may not be connected. It isnot possible to connect a crystal and apply a frequency via the FREFIN pin in the same application.

The crystal oscillator generates the reference frequency for

• the reference frequency divider for synthesizer PLL

• the timing for the IF counter

• the timing for the Pause Detector

• the free running frequency adjust of the stereo decoder VCO

• the centre frequency for adjustment of the IF filters

• clock frequency of the RDS/RBDS decoder

8.5 PLL Tuning System

The PLL synthesizer tuning system is suitable to operate with a 32.768kHz reference frequency generated by the crystaloscillator or a reference clock of 32.768kHz fed into the IC. To tune the radio to the wanted frequency the PLL word mustbe calculated first and then programmed to the register. The PLL word is 14 bits long, see table 12. Calculation of this14 bit word can be done as follows:

with: NDEC = Decimal value of PLL wordFRF= the wanted tuning frequency [Hz]FIF = the Intermediate Frequency [Hz]: 225kHzFREFS = the reference frequency [Hz] : 32.768 kHz

(4 x (FRF + FIF))NDEC =

FREFS

(4 x (FRF - FIF))NDEC =

FREFS

Equation 1 for Hi-Side Injection: Equation 2 for Lo-Side Injection:

(4 x (100.1e6 + 225e3))NDEC =

32768

Example for receiving a channel @ 100.1 MHz:

12246.704, round down to the lowest integer value = 12246, the PLL word becomes PLLHEX = 2FD6

= 12246.704


CONFIDENTIAL

Date: 2004 Nov 09

Page: 12

The result found using equation 1 or equation 2 must always be rounded to the lowest integer value.

So via the bus this value can be written to register FRQSET and the IC will then start an autonomous search beginningat this frequency or go to a preset channel at this frequency. When the application is built according to the blockdiagramof figure 1 and with the preferred components, the PLL will settle to the new frequency within 5ms.

The PLL is triggered by writing one of the following bytes: FRQSETMSB, FRQSETLSB, TNCTRL1, TNCTRL2,TESTBITS, TESTMODE.

Accurate validation of the PLL locking on the new frequency can take 2ms - 10ms. When a lock is detected the LD bit,table 20, is set.

8.6 Band Limits

The IC can be switched to the Japanese FM-band or the US/Europe FM-band. With BLIM set to 0 the band goes from87.5Mhz to 108MHz, BLIM set to 1 gives the Japanese band 76 MHz to 90 MHz.

8.7 RF AGC

The RF AGC prevents overloading and limits the amount of intermodulation products created by strong adjacentchannels. Default the RFAGC is on.

8.8 Local / DX

With the LDX bit set the LNA gain is reduced with 6dB to prevent distorsion when a transmitter is very near. With the LDXbit zero the LNA gain is normal to receive long distance (DX) stations.

8.9 IF Filter

Fully integrated IF filter.

8.10 FM Demodulator

The FM quadrature demodulator has an integrated resonator to perform the phase shift of the IF-signal.

8.11 IF Counter

The received signal is mixed to a 225kHz Intermediate frequency. The result of the mixing is counted. A good IF countresult indicates that the radio is tuned to a valid channel and not to an image or a channel with much interference .TheIF counter outputs a 7bit count result via the bus . The IF counter is continuously active and can be read at any time viathe bus. It also activates a flag when the IF count result is outside the IF count valid result window. See also section9.1.4.4.

Before a tuning cycle is initiated the IF count period can be set to 2ms or to 15.6ms with bit IFCTC. When the IF countperiod is set to 2ms, initiating the tuning algorithm with a preset (SM = 0) will always give an RDS update as is shown insection . In case the IF count time is set to 15.6ms the tuning flowchart of section is used. Once tuned, the IF count periodis always 15.6ms.

8.12 Level Voltage Generator and Analog to Digital Converter

The level voltage reflects the fieldstrength received by the antenna. The level voltage is analogue to digital convertedwith 4 bit and output via the bus. The level ADC is continously active and can be read at any time via the bus. It alsoactivates a flag as the Level voltages falls under a predefined selectable threshold. With the bit LHSW large hysteresyssteps or small hyteresys steps can be chosen, according to table 23. See also section 9.1.4.5.

When the ADC level is set to 3 it’s minimum value the search algorithm will only stop at channels having a RF level higherthan/or equal to ADC level 3. After completing the search algorithm and being tuned to a station, due to the hysteresisthe effective limit will be set to 0. This means that the continuous ADC level check will never set the LEVFLAG.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 13

8.13 Softmute

The lowpass filtered level voltage drives the softmute attenuator at low RF input levels, the audio output is faded andhence also the noise, see also figure 14 and 16 and compare the lines with reference nr 1 and 2. The softmute functioncan be toggled via the bus, bit SMUTE.

8.14 Hard Mute

With the MU bit, of the TUNCTRL2 byte, the audio outputs VAFL and VAFR can be hard-muted, this means they are putin tri-state. The same can be done by setting the bits LHM (Left Hard Mute) or RHM (Right Hard Mute) in byte TESTBITS,which mute only one output at a time (or both when both set) and force the IC to mono. Also with the IC in standby-modethe audio outputs are hard-muted.

8.15 Audio Frequency Mute - AFM

With the AFM bit, of the TUNCTRL register, the audio signal can be muted. In the softmute attenuator the audio signalis blocked and thus pins VAFL and VAFR will be at their DC biasing point having no signal. The audio is automaticallymuted during a preset as shown in the flowchart of Fig. 6. When the audio must be muted during search mode, this mustbe done by setting the AFM bit before the search and resetting it afterwards.

When the AFM bit is set also the RDS data is stopped.

8.16 MPX Decoder

The PLL stereo decoder is adjustment free. The Stereo decoder can be switched to Mono via bus.

8.17 Signal depending Mono/Stereo Blend (Stereo Noise Cancellation)

With decreasing RF input level the MPX decoder blends from Stereo to Mono to limit the output noise. The continuousmono-to-stereo blend can also be programmed by bus to an RF level depending switched mono-to stereo transition. SNCcan be switched off via bus with the SNC bit.

8.18 Software Progammable Port

One software programmable port (cmos output) can be addressed via bus.With bit SWPM = 1 the softwareport (pin7) the output for the FRRFLAG, with bit SWPM = 0 the software port outputs bitSWP of the registers, in testmode the software port outputs signals according to table 24. Testmode is selected settingbit TM of byte TESTMODE. The sofware port is not disabled by the PUPD bits, see section 8.19.

8.19 Stand-By

With the PUPD (Power Up / Power Down) bits the radio can be put in stand-by mode. The RDS part can be turned offseperately or both the RDS and the FM part can be turned off. The IC is still accesible via the bus, but takes only a lowpower from the supply, in stand-by the audio outputs are hard-muted.

8.20 Power On Reset

After start-up of VCC and VDD a power-on-reset circuit will generate a reset pulse and the registers will be set to theirdefault values as shown in chapter 12. The power-on-reset is effectively generated by VDD.

Note: After a power-on-reset the IC is in standby mode and the PUPD bits are 0. After a power-on-reset the registers arereset to their default value, except for bytes 12R to19R and flags DAVFLG, LSYNCFLG and PDFLAG. To reset these theradio must be turned on by setting PUPD[0]. After setting PUPD[0] = 1, it will take 0.9ms to startup the IC and set theseregisters to their default value.

The power supplies can be switched on in any order.

When the supply voltage VCC and VDD are made 0V, then all I/O ‘s, the audio outputs and the reference clock input arehigh-ohmic.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 14

8.21 RDS/RBDS Demodulator

Fully integrated RDS/RBDS demodulator, uses the reference frequency (32.678Hz) of the PLL synthesizer tuningsystem. The RDS demodulator recovers and regenerates the continuously transmitted RDS or RBDS data stream of themultiplex signal (MPXRDS) and provides the signals clock (RDCL), data (RDDA) for further processing by the integratedRDS decoder.

8.22 RDS Data and Clock Direct

The RDS demodulator retrieves the RDS data and clock signals, this data can be put directly onto the pins VAFL and VAFRby setting the RDSCDA bit to HIGH.

8.23 RDS/RBDS Decoder

The RDS decoder provides block synchronisation, error correction and flywheel function for reliable extraction of RDS orRBDS block data. Different modes of operation can be selected to fit different application requirements. Availability ofnew data is signalled by bit DAVFLG and output pin INTX, which generates an interrupt. Up to two blocks of data andstatus information are available via the I2C-bus in a single transmission.

The behaviour of the DAVFLG is described in section .

8.24 Audio Pause DetectorThe Audio Pause detector watches the audio modulation for pauses by looking at low levels. The modulation thresholdcan be adjusted in 4 steps of 4dB by the control bits PL0 and PL1. The minimum time for detecting a pause can beadjusted by the control bits PT0 and PT1 as in table 39. When there is a pause this is indicated by a flag, the PDFLAGis set to 1 and a hardware interrupt is generated. See also section 9.1.4.6.

8.25 Autosearch and preset

In search mode the IC can search channels automatically.

Before starting a search or a preset the INTMSK register must be reset and only the FRRMSK must be set. This way theuP will only be interrupted when the search/preset algorithm is ready.

Search mode is initiated setting the SM bit to 1. The SM bit is in the FRQSETMSB byte. When SUD is 0 then it searchesdown, when SUD is 1 it searches up. The tuner starts searching at the frequency set in the FRQSET bytes. With the SSL(Search Stop Level) bits the fieldstrength of channels to be found can be set. The tuner will stop on a channel with afieldstrength equal to or higher than this reference level and then check the IF frequency, when both are valid it stops.(Note that this depends on the AHLSI bit as described in figure 5.) If the level-check or the IF-count fails, it keeps onsearching. If the level-check or the IF-count fails, it keeps on searching. When no channels are found the IC stopssearching when it has reached the band-limit and the the BLFLAG goes high. A search always stops with the FRRFLAGbeing set and a hardware interrupt. Figure 5 describes this procedure.

The search algorithm can stop at a frequency which will give an offset of the IF frequency of maximum 12kHz, whileapplying a preset can limit the offset of the IF frequency to maximum 8kHz. It is recommended to do a preset after asearch when the found frequency has an offset higher than 8kHz for the best tuning.

After this interrupt the IC will not update the tuner-registers for a period of 15ms. The state of the IC can be checked byreading the bytes of: INTFLAG, FRQCHKMSB, FRQCHKLSB and TUNCTRL1/2. Table 2 shows the possible states afteran autosearch or a preset.

A preset is done by setting SM to 0 and writing a frequency to byte FRQSETMSB. The tuner jumps to the selectedfrequency and sets the FRRFLAG when it is ready. After this interrupt the IC will keep not update the tuner-registers fora period of 15ms. The state of the IC can be checked by reading registers: INTFLAG, FRQCHKMSB, FRQCHKLSB andTUNCTRL1/2. Table 2 shows the possible states after an autosearch or preset.

8.25.1 AUTO HI-LO SIDE INJECTION STOP SWITCH.

When a channel is searched or a preset is done, reception can sometimes improve when injection is done at the otherside of the wanted channel.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 15

The IC has bit HLSI, this bit toggles the injection of the local oscillator from Hi-Side HLSI=1to Lo-Side with HLSI = 0.When HLSI is toggled also a new PLL setting must be sent to the IC.

When the AHLSI bit is set, the search/preset algorithm will stop after a channel has a valid RSSI level check but fails theIF count. The uP can now respond by toggling the HLSI switch and sending a new PLL value to the tuner.

8.25.2 MUTING DURING SEARCH OR PRESET.

During a preset the tuner is always muted, this is done by the algorithm itself. A search is default not muted unless theAFM is set or the AHLSI bit is set. When the AHLSI bit is set and the tuner stopped during a preset or a search becauseof a wrong IF count, the tuner keeps muted; this way the uP can switch the Hi-Lo setting quietly and wait for the newresult. The AFM bit mutes the tuner always, independent of a search or a preset. It can be used to mute a search, bysetting the AFM bit before a search is initiated and resetting it when the tuner is ready. Note: Only set FRRMSK wheninitiating a search or preset.

All these mute actions are done by blocking the audio signal inside the softmute attenuator, the audio output will keepit’s DC level and stay low-ohmic i.e. 50Ω (a hard mute with the MU bit will cause a plop).

Table 2 Tuner Truth Table*

Note: This table is valid untill 30.6ms after the tuning cycle has completed. It shows the outcome of the flag register whena read is done after INTX has gone low, on condition that no other mask bits are set than shown in the table.

IFFLAG BLFLAG FRRFLAG Comment

0 0 0 If INTX has gone low and only IFMSK, FRRMSK and BLMSK were set then thiscannot occur.

0 0 1 Channel found during search/preset FRRMSK set.

0 1 0 Not a valid state.

0 1 1 A valid channel found and the bandlimit has been reached during a search, BLMSKor FRRMSK set.


1 0 1 A preset or search has been done, but the wanted channel has a valid RSSI levelbut fails the IF count. When AHLSI was set HLSI must be toggled and a new PLLvalue must be programmed, FRRMSK set.


1 1 1 Bandlimit is reached during search, no valid channel found, BLMSK or FRRMSKset.

Wanted channel Image on Hi-SideImage on Lo-Side

Switch LO from Hi-Side to Lo-Side

Fig.4 Switch from Hi-Side injection of LO to Lo-Side injection using the HLSI bit..


CONFIDENTIAL

Date: 2004 Nov 09

Page: 16

Fig.5 Flowchart autosearch or preset (IF statement down = True).

wait for PLL to settle

Start

Searchmode

IF OK

AHLSI

decrement current_pllby 100 kHz

increment current_pllby 100 kHz

Searchup

Level OK

During a preset mute is always active.Search mode is default not mutedunless AHLSI is set.

BLFLAG = 1FRRFLAG = 1

BandLimit



Unmute

set PLL frequencyreset Flags

muted

Set LEVFLAG

Unmute


CONFIDENTIAL

Date: 2004 Nov 09

Page: 17

Paulo

Highlight

8.26 RDS update / Aternative Frequency Jump

A channel which transmits RDS data can have alternative channels which have the same information. These alternativechannel frequencies are in the RDS data, so the uP can read the alternative frequencys and store them in a memory.

The tuner can do an RDS update. This is much like a preset, but with a 4ms IF count time. The tuner will jump to thealternative frequency and check the level and the IF count using a 4ms count time. When RSSI level check is above thespecified level and the IF count result is within the limits then the tuner will stay at the alternative frequency and staymuted, the uP can now decide what to do. If the Alternative Frequency is not valid it will jump back to the frequency itcame from. The algorithm will finish with the FRRFLAG being set and generate an interrupt. After this interrupt the IC willnot measure the IF count for a period of 15ms. 15ms after completing a RDS jump a measurement of the IF count willstart and hence the IF count result and the IFFLAG will be updated 30.6ms after completing the algorithm. The Levelmeasurement will start immediately after the tuning algorithm, so the LEVFLAG will be updated 500us after the algorithm.The state of the IC can be checked by reading registers: INTFLAG, FRQCHK and TUNCHK. Table 3 shows the possiblestates after an autosearch, figure 6 the flowchart.

8.26.1 MUTING DURING RDS UPDATE.

An RDS update (AF jump) is always muted. There are two possibilities for leaving the algorithm.

The tuner jumps to an alternative frequency which is not valid (according to the specified SSL limit and fixed IF counterlimits) and jumps back, then it will automatically unmute.

Or the tuner jumps to a valid alternative frequency and stays there. Now it does not unmute. The uP can unmute or itkeeps the tuner muted and can check for the presence of RDS data. The valid way to unmute is to do a preset to thecurrent frequency (at a preset an ifcount time of 15.6ms is used, which gives a more accurate if count result than theresult obtained by the AF jump, where 2ms is used).

Table 3 RDS update Truth Table*

Note: This table is valid untill 30.6ms after an RDS update has completed. It shows the outcome of the flag register whena read is done after INTX has gone low, on condition that no other mask bits are set than shown in the table.

IFFLAG BLFLAG FRRFLAG Comment


0 0 1 Alternative Frequency Jump succesfull, radio is tuned to the alternative frequencyand keeps muted.




1 0 1 AF jump has been done, but the wanted channel fails the IF count, the PLL will beset back to the old value.




CONFIDENTIAL

Date: 2004 Nov 09

Page: 18

Fig.6 Flowchart RDS update.

wait for PLL to settle

Start

Level OK?

Unmute

Activate mute

Set pll to AFfreq.


keep muted

Store ‘old’ PLL setting

(pll is old freq)(pll is AF freq)

IF OK?

set IF count timeto 2ms

Clear LEVFLAGClear IFFLAG

Wait for IF counter

Reset ‘old’ PLL setting

Wait for PLL to settle


Set LEVFLAG


CONFIDENTIAL

Date: 2004 Nov 09

Page: 19

9 INTERRUPT HANDLING

9.1 Interrupt Register

The first two bytes of the I2C register contain the interrupt masks and the interrupt flags.

Table 4 INTFLAG Byte0R

A flag is set when it is 1.

Table 5 INTMSK Byte0W / Byte1R

The interrupt flag register contains the flags set according to the behaviour outlined in section 9.1.4. When these are setthey can also cause the INTX to go active (HW interrupt line) depending on the status of the corresponding mask bit intable 5. A ’1’ in the mask register enables the HW interrupt for that flag.

Hence it is conceivable that, with all the mask bits cleared, the SW could operate in a polling mode by continuous readoperation of the interrupt flag register to look for bits being set.

Interrupt mask bits are always cleared after reading the first two bytes of the interrupt register. This is to control multipleHW interrupts. See figure 7. The LSYNCMSK has a different function and is not cleared after reading the interrupt registerbytes, see also section 9.1.4.3.

9.1.1 Interrupt clearing

The interrupt flag and mask bits are always cleared after:• they have been read via the bus

• a power on reset

9.1.2 Timing

The timing sequence for the general operation interrupts is shown in Figure 7 and shows a read access of the interruptbytes INTFLAG and INTMSK and a subsequent (though not necessarily immediate) write to the mask register. It alsoindicates two key timing points A and B.

If an interrupt event occurs while the register is being accessed (after point A) it must be held until after the mask registeris cleared at the end of the read operation (point B).

Point A is after the R/W bit has been decoded and point B is where the acknowledge has been received from the master(uP etc.) after the first two bytes have been sent.

The low time for the INTX line (TFMINT) has a maximum value specified in chapter 14. However it can be shorter if theread of the INTREG registers occurs within the TFMINT.

9.1.3 Reset

A reset can be performed (at any time) by a simple read of the interrupt bytes, byte0R and byte0W, which automaticallyclears the Interrupt flags and masks.

Bit No 7 6 5 4 3 2 1 0

Name DAVFLG TESTBIT LSYNCFLG IFFLAG LEVFLAG PDFLAG FRRFLAG BLFLAG

Bit No 7 6 5 4 3 2 1 0

Name DAVMSK - LSYNCMSK IFMSK LEVMSK PDMSK FRRMSK BLMSK


CONFIDENTIAL

Date: 2004 Nov 09

Page: 20

Date: 2004 Nov 09

Page: 21

set theird. Whichcurred ingh.

s to the mask byte and enables theask bits. Any flags currently set will

hen trigger a HW interrupt.

data A A

TMSK

1W data

FRQSETMSB

A 2W data

FRQSETLSB

P

ending on the

n is received

terminated by


CONFIDENTIAL

Data

Interrupt Event

Interrupt Flag bit

Interrupt Mask bit

INTX

A B2

Interrupt events that occur outside ofthe region A-B set their respective flagbits in the normal way i.e. immediatelyand can thus trigger a HW interrupt if

the mask bits are set.

All interrupt mask bits are clearedat the end of the interrupt flag and

mask bytes.

Interrupt events that occur between A and B respective flags after the mask bits are clearemeans that in this picture an interrupt event oc

period A-B, so after A-B the Flag goes hi

INTX is set HIGH (inactive) at the end ofreading the interrupt mask bytes.

SW writerequired m

t

Fig.7 I2C Interrupt sequence, read and write operation.

S 0R dataDeviceaddress R A A Data A

INTFLAG

1R data

INTMSK

A S 0WDeviceaddress W A

INRead access Write access

B1

1. The blocking of interrupts is marked by the region A - B1/B2 depactual read cycle.2. B1 is when only the INTFLAG register is read and a stop conditio(i.e. only INTFLAG is read so only this will be cleared)3. B2 is when both registers are read and hence cleared and this iseither an ack or stop bit.

9.1.4 Interrupt flags and behaviour

9.1.4.1 Multiple interrupt events

If the interrupt mask register bit is set then the setting of an interrupt flag for that bit causes a HW interrupt (INTX goeslow). If the event occurs again, before the flag is cleared, then this does not trigger any further HW interrupts until thatspecific flag is cleared. However two different events can occur in sequence and generate a sequence of HW interrupts.Only when read, followed by a write of the INTMSK byte has been done, a second interrupt can be generated, as thefirst interrupt blocks the input of the INTX oneshot generator.

If subsequent interrupts occur within the INTX low period then these do not cause the INTX period to extend beyond itsspecified maximum period. See also section 9.2.

9.1.4.2 Data available: DAVFLG

The DAVFLG is set when a new block of data is received according to the diagrams shown in chapter 10 where thedifferent DAV modes are described. Once synchronised, this continues for all subsequent received blocks (dependenton DAV mode) and in the following situations:

* During sync search, in any DAV mode, two valid blocks in the correct sequence received with BBC<BBL(synchronised).

* During synchronization search in DAVB mode if a valid A(C’)-block has been detected. This mode can be used for fastsearch tuning (detection and comparison of the PI code contained in the A(C’)-block).

* If the pre-processor is synchronized and in mode DAVA and DAVB a new block has been processed. This mode is thestandard data processing mode, if the decoder is synchronized.

* If the pre-processor is synchronized and in DAVC mode two new blocks have been processed.

* If the decoder is synchronised and for any DAV mode, with LSYNCMSK=0, loss of synchronisation is detected (flywheelloss of synchronisation, resulting in a restart of synchronisation search).

The DAVFLG is reset by a read of RDSLBLSB (byte15R) or RDSPBLSB (byte17R). An interrupt is given each time whena new block of data is decoded and when the DAVMSK is set, for details look in chapter 10.

9.1.4.3 RDS synchronisation: LSYNCFL

The SYNC bit, table 25, shows the status of the RDS decoder. If it is set then the decoder is synhronised, if it is 0 it is not.

The action of the ASIC depends on the status of the LSYNCMSK bit in table 5. If this is set then the loss ofsynchronisation causes the LSYNCFL to go HIGH when synchronisation is lost and a hardware interrupt. The RDS partof the ASIC is set to IDLE and waits for the uP to initiate a new synchronisation search by setting the NWSY bit asdescribed in table 25.

If the LSYNCMSK bit is 0 and synchronisation is lost the ASIC automatically starts a new synchronisation search. It willnot generate a hardware interrupt. The uP can wait untill the RDS decoder is synchronised again, this will be indicatedby the DAVFLAG and the SYNC status bit (this requires the DAVMSK being set).

The LSYNCFL is reset by a read of the INTMSK byte1R.

The LSYNCMSK is not reset by a read of the INTMSK byte, it must be set or reset by the uP. Resetting it automaticallywould change the status of the ASIC and cause an automatical synschronisation search as described above.

How the synchronisation is defined is explained in brief in chapter 10 and in [2].

9.1.4.4 IF Frequency: IFFLAG

During Automatic frequency search, preset or AF update, the FM part of the ASIC performs a check on the received IFfrequency as a measure of the level of interference in the channel received. If an incorrect IF frequency is received thenthis indicates the presence of strong interferers or tuning to an image and the IFFLAG bit in the INTFLAG register is set.Also a preset to a channel with no signal will result in a wrong IF count value and hence setting of the IFFLAG.

When a search, preset or AF update is finished the FRRFLAG will be set to indicate this and generate an interrupt. TheuP can now read the outcome of the registers which will contain the IF count value and the IFFLAG status of the channel


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it is tuned to. In case of an AF update the IF count value of the alternative frequency will be in the registers, also when itjumps back, because it will then not start a new IF count. Note: 15.6 ms after the tuning algorithm has completed the IFcounter will start a new count. So 30.6ms after a failed AF update the IF count result will be equal again to that of thechannel from where the jump was initiated.

15ms after the FRRFLAG has been set the IF counter will start to run continuously on the tuned frequency and if theconditions for correct frequency are not met then this sets the IFFLAG bit in the interrupt register. When the IFMSK is setthis will also cause an interrupt.

The IFFLAG bit is cleared by a read of byte1R , or by starting the tuning algorithm.

9.1.4.5 RSSI threshold: LEVFLAG

The level voltage reflects the fieldstrength received by the antenna. The level voltage is analogue to digital convertedwith 4 bit and output via the bus, this 4 bit level value can be compared to a threshold level set by the SSL bits in table16 or the LH bits in table 23. The levelADC (which converts the analogue value to digital) can be triggered to convert intwo ways.

During a tuning step, a search, a preset or an AF update the LEVFLAG is triggered by these algorithms and comparesthe level with the threshold set by the SSL bits. The LEVFLAG bit is set if the RSSI level drops below the threshold levelset by the SSL bits in table 16, the HW interrupt is only generated if the corresponding mask bit is set.

After a search, a preset or an AF update, the threshold for comparison is switched to the hysteresis level. The hysteresislevel is set by the combination of SSL bits and the LHSW bit table 21, which results in a hysteresis as shown in table 23.Then the levelADC starts to run automatically and compares the level each 500µs with the hysteresis level. TheLEVFLAG bit is set if the RSSI level drops below the threshold level set by the SSL bits in combination with the LHSWbit table 23, the HW interrupt is only generated if the corresponding mask bit is set. With the LHSW bit a small or a largehysteresis can be selected, which results in the levels of the left RSSI hysteresis threshold column for LHSW = 0 and inthe right RSSI hysteresis threshold column see table 23. Note: When a search or preset is done with the ADC level setto 3 then when the algorithm has finished, the threshold level is set to 0. Hence the LEVFLAG will never be set.

The LEVFLAG bit is cleared by a read of the INTMSK byte1R , or by starting the tuning algorithm

9.1.4.6 Pause Detection: PDFLAG

The pause detector compares the amplitude of the audio signal and starts counting when this drops below the referencelevel, when the counter reaches the specified count time a pause is detected and the PDFLAG will be set. IfPDMSK=1then setting the PDFLAG will also give an interrupt. The PDFLAG operates independent of the PDMSK.

The PDFLAG bit is cleared by a read of byte1R on condition that the read action takes place more than 500usec afterreceiving the pause interrupt on the INTX line.

The PDFLAG only works when RDS is turned on PUPD[1] = 1 and RDS is not idle by a loss of synchronisation.


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Refer to Figure 7. When the peak audio level of the (L+R) drops below the threshold (t1) set by the PL bits in table 39.It then counts the duration of the pause and if the pause lasts longer than the value set by the PT bits, then the PDFLAGbit is set and this in turn generates a HW interrupt (if PDMSK=1).

The circuit should ignore short transients where the audio level momentarily rises above the threshold (at t2).

The PSCOn signal is going directly to the software port, the PDFLAG is set by the integrator and going to the bus. Theinterrupt line is triggered by the PDFLAG.

tpause tpausetaudio

Audio present

No Audio present

E.g. Suppose PT = 20ms, t pause=16ms and t audio= 1.5ms. The pause detector will count according (2):2*tpause - 8*taudio = 20ms => 2*16ms - 8*1.5ms = 20ms.In this case the pause detector has measured 1*16ms 'pause', 8*1.5ms 'no pause' and 1*16ms pause. Therefore, on averagethe pause detector has measured 16ms-12ms+16ms = 20ms pause time and hence a pause will be detected.

Audio signal

PSCO

+reference level "PL” [mV]

0

Pause

No pause

To detect a pause the amplitude of the audio signal is compared with the reference level selected by the PL-bits. The resultsignal “psco”of this comparison is sampled with a frequency of 2341Hz, resulting in the signal “PSCOn ”. A pause is detectedif:

SUM(0 to N-1) [PSCOn =0] - 8*SUM(0 to N-1) [PSCOn = 1] > PT x 2341 (1)tpause - 8* taudio > PT (2)

where N equals the number of samples taken over time and PT represents the pause time selected by the busbits PT. Ondetection of a pause the integrator will be reset. The integrator value cannot become smaller than zero. Therefore, if in theformula above the second SUM becomes larger than the first SUM, the integrator output will remain zero.

PSCOn

PT x 2341Integratoroutput

0

- reference level "PL”

The reference level is defined in kHz,but internally this is transformed to mV.E.g. 22.5kHz = 75 mV 1kHz = 3.3mV

Audio

PDFLAG

t1 t2

Note: The actual PSCOsignal behaves asshown above, here weassume that all samplesare taken at peaks of theaudio signal, whichresults in PSCOn

Fig.8 Operation and timing of Pause Detection according to levels set in table 39.


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9.1.4.7 Frequency ready: FRRFLAG

The Frequency Ready flag bit is set when the automatic tuning has finished a search, a preset or an RDS AF update.the description of this bit is in table 2 and table 3. The FRRFLAG is cleared by a read of byte1R.

9.1.4.8 Band limit: BLFLAG

The Band Limit bit BLFLAG is set when the automatic tuning has detected the end of the tuning band or when the PLLcannot lock on a certain frequency, the description of this bit is in table 2 and table 3 . This bit is cleared by a read ofbyte1R.

9.2 Interrupt Line

The interrupt line driver is a MOS transistor with a nominal sink-current of 680 uA, it is pulled high by an 18kΩ resistorconnected to VREFDIG. The interrupt line can be connected to one other similar device with an interrupt output and an18kΩ pull-up resistor, providing a wired OR function. This allows any of the drivers to pull the line low by sinking thecurrent as specified in chapter 14. So when a flag is set and not masked it generates an interrupt:

Fig.9 Interrupt line behaviour.

<10ms10ms<10ms10ms

VCC

Flag

INTX

Read INTMSK

Note1: read INTMSK clears Flag, INTMSK and INTXNote2: write INTMSK enables INTXNote3: when Flag is set next interrupts are blocked untill Read/Write INTMSK

read clears INTX

Write INTMSK

Flag is set immediately after thereset, because event is still there.


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10 RDS DATA PROCESSING

The RDS demodulator and decoder perform the following operations:• Demodulation of the RDS/RDBS data stream from the MPX signal

• Symbol decoding

• Obtain block and group synchronisation

• Error detection and correction

• Store last and previous data block received with associated ID and error status.

• Set the DAVFLAG when new data is received

• Set the SYNC status bit according to the current synchronisation state.

• Set the LSYNCFL flag when synchronisation is lost.

The RDS decoder can be set in different modes, each meant to look for specific information. The modes DAV-A, DAV-Band DAV-C are described in the next paragraphs.


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10.1 DAV-A Processing mode

The DAV-A processing mode is the standard processing mode used. In this mode each time when a data block has beendecoded it is transferred to the bus-registers. It generates interrupts on the INTX line after every new block of RDS datathat has been processed and also the DAVFLAG is set. This is shown in figure 10. The DAVFLAG is reset by a read ofthe bus-registers.

If a data block is decoded and a new one arrives, INTX will go low again, the DAVFLAG will be set and the Last Blockwill be shifted to the Previous Block and the last decoded block will be put in the Last Block. This means that all RDSdata is still available in the BL and BP registers.

When the bus-registers are not read the DAVFLAG will not be reset. If a data block is decoded and a new one arrives,INTX will go low and the Last Block will be shifted to the Previous Block and the last decoded block will be put in the LastBlock. This means that all RDS data is still available in the BL and BP registers, but must be read. This is indicated bythe DOVF bit, which is set.

If again the bus-registers are not read data will be lost, except when this read is done within 20ms after the INTX line hasgone low, so 2ms before the arrival of a new block. If this read is done at least 2ms before the arrival of a new block, thenBL and BP are read and the data in the decoder buffer is then instantanieously shifted to the BL register. All data is nowread and the DOVF bit will be reset.

The diagram assumes that block synchronisation has been achieved and that no other interrupt flags are being set.

A1

B1

C1

D1

A2

B2

INTX

read intflg+RDS on INTX

tRead

21.9ms

BL Register

BP Register x

B1

C1

B1

C1

Data Overflow bit

B1

If there is no read cycle, B1 is placed inthe BP register and the new block C1 isnow in the BL register. The DOVF bit is

set to indicate two blocks available.

DAV-A/B: Normal

DOVF set when 2 new blocksreceived in BL/BP

DOVF is cleared when theBL is read. To be of useDOVF has to be read be-fore BL and BP registers

DecoderRegisters

A2

Instant copy of decoder buffer to BLregister and BL register to BP registerafter reading RDSR4. The block in BL

is concidered as a new block.

TINT_RD

<~ 10ms

A1

Being decoded

In the decoder buffer

B1

A1

C1

B1

D1

C1

A2

D1 A

2

B2

C2

A2

>2ms

end read intmsk

In order not to lose D1a read must have beenperformed before A2has been decoded.

DAVFLGDAVFLG set onDAVN=0, cleared on

read BL-reg

B2

TINT_RD

Read BL Read BL Read BL

D1

C1

A2

D1

D1

A2

A1

A2

A2

B2

To prevent DOVF tobe set again, anextra read of BL

must be performedbefore A2 has been

decoded

BusRegisters

Fig.10 DAV-A timing diagram


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10.2 DAV-B Processing mode / Fast PI search mode

This mode is used when, for example, the receiver has been re-tuned to a new station and a fast search of the PI code,always contained in the A or C’ block, is required. The diagram shown in figure Fig.11, assumes that the RDS decoderis unsynchronised initially and is performing a synchronisation search.

During synchronisation search the decoder does not set the DAVFLG until a valid A/C’ -block is detected. If then a validB-block is immediately detected, then the decoder is now synchronised and the SYNC bit is set to 1. In fact, if any 2 goodblocks in a valid order are found the RDS decoder will synchronise and give an interrupt.

If for some reason a valid B block was not received then the next valid A/C’-block would be decoded and the DAVFLAGset. The BP and BL registers would record the A block history.

When the decoder is synchronised each decoded block will set the DAVFLAG (assuming it was reset by a read-action)and generate an interrupt.

B1

C'1

D1

A2

B2

DAV B mode: With Bad blocks detected during sync search

INTX

21.9ms

BL Register

BP Register

Good A or C' block detected

BusAccess - Read

Sync status bit

Unsynchronised Synchronised

Only valid blocks with no errorsare counted as good blocks

Error correction appliedaccording to SYM bits

Bad Good Bad Bad

X

X X

C'1

C'1

Good Good

B2

C'1

C2

C2

DAVFLG

X

C'1

X B2

Note: BBG > 2

read intmskRead BL register

Fig.11 DAV-B timing diagram


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10.3 DAV-C Reduced Processing mode

The DAV-C processing mode is very similar to DAV-A mode with the main exception that a data flag is only set after twonew blocks are received. Hence the update rate is reduced by half.

A1

B1

C1

D1

A2

B2

DAVFLG

INTX

Read access (Case 1)

tINTX

TINT_RD

tRead

21.9ms

BL Register

BP Register

A1

D0

A2

Data Overflowbit


tRead

DAVFLG(Case 2)

Case2: Late read of BL, BP register

Case 1: Normal DAV-C mode

Dashed line shows what would happen if no read occured at (a). DOVF bit setuntil the next read of BP register, however,D1,A2 would be lost.

(a)

INTX cleared @ end read INTMSK

DAVFLG not cleared as no read performed

C0

D0

D1

D1

No read on INTX soB1 will be lost

DAVFLG reset when1st new block wouldhave been copied toBL register

B1 copied to BLreg shortly beforeC1 decoded

BLreg copied to BPregand C1 to BLreg

tINTX

= 10 ms

DAVFLG cleared @ end read BPregand forced to zero till en read RDSR4

C1

A1 C

1

Instant copy of C1

fromdecoder buffer to BLand BL to BP justbefore D

1 decoded

due to read action.

2 new blockshave arrived inBL/BP register

2 new blocks have arrived in BL/BP (C1,D

1) and a new block (A

2)

has entered the decoder buffer. Hence, DOVF is set again. Toprevent this, an extra read must be performed after reading (a).

DAVFLG set when 2 nd new blockin decoder buffer

Instant copy A2

from decoderbuffer to BL andBL to BP

Beingdecoded

Fig.12 DAV-C timing diagram


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10.4 Synchronisation

10.4.1 CONDITIONS FOR SYNCHRONISATION.

When the RDS decoder is turned on it must be synchronised to extract valid data from the MPX signal. To do so thedecoder automatically initiates a search for synchronisation. The conditions to meet synchronisation and the status ofthis synchronisation can be set and checked with the following bits.

BBL - Bad Blocks Lose - these bits can be set via the bus and have a value between 0 - 63.

GBL - Good Blocks Lose - these bits can be set via the bus and have a value between 0 - 63.

BBG - Bad Blocks Gain - these bits can be set via the bus and have a value between 0 - 32.

GBC - Good Block Count - these bits can be read via the bus and have a value between 0 - 63.

BBL - Bad Block Count - bits can be read via the bus and have a value between 0 - 63

When the decoder is not synchronised it will initiate a synchronisation search. This involves calculation of the syndrome(see reference [2] for details) for each block of 26 received bits on a bit-by-bit basis. When a correct syndrome (and henceblock ID) is received the decoder clocks the next 26 bits into the internal registers and performs a second syndromecheck. Synchronisation is found when a certain number of blocks have been decoded and two goods blocks have beenfound, this number of blocks is defined by the BBG bits. If the first block needed for synchronisation has been found andthe expected second block (after 26 bits) is an unvalid block, then the decoder module internal bad_blocks_counter isincremented and the next expected block is calculated; exception: if RBDS mode is selected and the first block is E, thenthe next expected block is always block A, until synchronisation is found or the maximum bad_blocks_counter value isreached. If the the decoder module internal bad_blocks_counter reaches the value of the BBG<4:0>, then immediatelystart of new synchronisation search (bit-by-bit) is started to find a new first block.

The synchronisation is monitored by use of two flywheel counters, GBC and BBC. These are 6-bit counters that can bepreset by the GBL and BBL bits to values between 0 and 63. Each time a block is decoded and recognised as a badblock the Bad Block Counter value, BBC, is incremented by 1. When the BBC value is equal to the BBL value,synchronisation is lost. The SYNC bit will become 0 and the LSYNCFL is set to signal the loss of synchronisation. (Nowthe ASIC will automatically initiate a new synchronisation search).

Each time when a good block is decoded the GBC value is incremented. When the GBC value is equal to the GBL valueboth counters, BBC and GBC, are set to 0 and a new count starts. The GBC counter is only incremented when thedecoder is synchronised.

10.4.2 DATA OVERFLOW

During synchronisation after RDS data is read from the registers, new available blocks are shifted to the registers asdescribed in sections 10.1- 10.3. When the registers are not read in time, the decoder cannot shift any new availableblock to the registers and hence a data overflow will occur, this is indicated by the DOVF bit which is set to 1. The DOVFbit is reset by a read of the registers or if NWSY = 1 which results in the start of a new synchronisation search.


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lock. Also the DAVN signal triggers the interrupt outputR before the arrival of a new RDS data block. In the can have various causes such as a µProcessor whichdescribes the behaviour of the DAVFLG and the DAVN

TX-oneshot generator when DAVMSK=1. Unlike INTX

A B C10ms

Normally reading byte19R would resetDAVN, but now it is reset after 10ms, themax low time of the DAVN.

0R 15

R 17

R 19

R W0

W 15

R 17

R 19

R W0

W


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10.5 RDS Flag behaviour during read action.

Each time when a RDS data block is decoded the DAVN signal will go low to signal the presence of a new data bINTX. In principle the µProcessor must now start reading and must have read all RDS data, so byte12R to byte19application it can be that there is a too large delay between the arrival of a new block and reading this block. Thishas to start up from sleep mode or when “polling” is used instead of interrupt based read actions. The picture belowsignal in case off polling, which effectively means that reading can occur at any moment. Note: DAVN sets the INDAVN is not cleared by a read of the Mask register.

A B C DRDS data

DAVN

DAVFLG

BusRead byte: 0R 15R 17R 19R W0W

Read of byte15R in DAV-A and DAV-B mode clears DAVFLG. In DAV-C mode two consecutive RDS datablocks are read and hence DAVFLG is reset after reading byte17R instead of byte15R (dotted line).

Read of byte19R clears DAVN

RDS flag behaviour during read actions and reading across a block boundary.

reset of DAVFLG

Blocking DAVFLG: At the end of reading byte15R / 17R (DAV-A,B/C) the DAVFLG signal is forced to zero . Only after readingbyte19R DAVFLG is released again.When synchronous reading is done, using ASIC generated interrupts this problem does not occur.To prevent undefined situations byte 12R - 19R should always be read in one read action immediately after eachother.

Note: DAVN INTX

Write byte0W - INTREG

0R 15R 17R 19R W0W 0R 15

R 17

R 19

R W0

W 0R 15R 17R 19R W0W0

R

Fig.13 RDS flag behaviour

10.6 Error detection and reporting

The FM/RDS ASIC must report information on the number of errors corrected in the last and previously decoded blocks.This is reported in the ELB and ELP fields as shown in table 27.

During synchronisation search the error correction is disabled for detection of the first block and is enabled for processingof the second block according to the mode set by the SYM bits as described in Table 37.

10.7 RDS test modes

In test mode the raw RDS clock and RDS data can be recovered directly from pins VAFL and VAFR when bit RDSCDA= 1.

10.8 RDS data - Reading from the registers.

To read RDS data the µProcessor must read byte12R to byte19R. All 8 bytes must be read to reset the status bytesbyte12R and byte13R, i.e. effectively the status bits can be updated by the decoder after reading the last bit of byte19R.The DOVL bit is cleared after reading the last bit of byte19R and the status of the SYNC bit does not depend on readingthe register, the SYNC bit tells if the decoder is synchronised or not. When starting a read action from byte12R, thedecoder blocks update from the RDS bytes untill byte19R has been read. RDS byte12R - 19R must be read in one readaction.


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11 CONTROL INTERFACE

The full I2C bus specification can be found in [1].

11.1 I2C Bus

I2C BUS Write mode

I2C BUS Read mode

Notes

1. S = START condition.

2. A = acknowledge

3. P = STOP condition.

The I2C Bus specification is based on version 2.1 January 2000 expanded by the following definitions.

The chip has two I2C addresses:FM-radio : 0010000[RWn] starts at byte0R or byte0W.RDS part: 0010001[RWn] starts at byte12R or byte7W.

Structure of the I2C Bus: Slave transceiver, Subaddresses not used.The input maximum LOW level and the input minimum HIGH levels are specified to 0.3*VREFDIG resp. 0.7*VREFDIG.

Data Transfer to the IC:

The data transfer has to be in this order. The LSB=0 of the address indicates a WRITE operation to the IC, indicated bythe RWn bit of the I2C address.

Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of the byte.

The data becomes valid bitwise at the appropriate falling edge of the clock. A stop condition after any byte can shortentransmission times. When writing to the transceiver by using the stop condition before completion of the whole transfer:

- The remaining bytes will contain the old information

- If the transfer of a byte is not completed, the new bits will be used, but a new tuning cycle will not be started.

So to speed up RDS traffic it is possible to read all the RDS data and then only write back byte INTMSK to set theappropriate mask(s) again.

The tables below show the sequence of I2C data bytes for read and write operations for both FM and FM+RDS acces.For simplicity the address, start, stop and acknowledge bits are not shown. The FM and RDS part have different I2Caddresses as stated.

When the IC is adressed with the FM-radio address, also in one read action byte12R - byte27R can be read. A read doesnot have to stop at byte11R.

When writing also all bytes, byte0W - byte10W can be written with one write action.

So effectively using the RDS-part address only skips some bytes, which reduces bus-access.

Table 6 FM - Read mode data transfer

S(1) CHIP ADDRESS (write) A(2) DATA BYTE(S) A(2) P(3)

S(1) CHIP ADDRESS (read) A(2) DATA BYTE 1

← byte0R byte1R byte2R byte3R byte4R byte5R byte6R byte7R byte8R byte9R byte10R byte11R


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Table 7 RDS - Read mode data transfer

Table 8 FM - Write mode data transfer

Table 9 RDS - Write mode data transfer

With the Standby Bit the IC can be switched in a low current stand-by mode. The bus is then still active. Is the BusInterface deactivated, by making pin BUSENABLE low, without programmed stand-by mode, the IC keeps its normaloperation, but is isolated from the bus lines.

It is possible to operate the IC with BUSENABLE hard wired to VREFDIG and have the businterface always active.

Power-on reset : The mute is set, all other bits are set default according to the tables in chapter 12. To initialize the ICall bytes have to be transfered.

← byte12R byte13R byte14R byte15R byte16R byte17R byte18R byte19R byte20R byte21R byte22R byte23R

byte24R byte25R byte26R byte27R

→ byte0W byte1W byte2W byte3W byte4W byte5W byte6W

→ byte7W byte8W byte9W byte10W


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12 REGISTERS

12.1 Register Map

I2C-Byte Nr. BYTE NAME R/W ACCESS RESET

0R INTFLAG R 00

1R/0W INTMSK R/W 00

1W/2R FRQSETMSB R/W 80

2W/3R FRQSETLSB R/W 00

3W/4R TNCTRL1 R/W 08

4W/5R TNCTRL2 R/W D2

6R FRQCHKMSB R -

7R FRQCHKLSB R -

8R IFCHK R -

9R LEVCHK R -

5W/10R TESTBITS R/W 00

6W/11R TESTMODE R/W 00

12R RDSSTAT1 R -

13R RDSSTAT2 R -

14R RDSLBMSB R -

15R RDSLBLSB R -

16R RDSPBMSB R -

17R RDSPBLSB R -

18R RDSBBC R -

19R RDSGBC R -

7W/20R RDSCTRL1 R/W 00

8W/21R RDSCTRL2 R/W 10

9W/22R PAUSEDET R/W 00

10W/23R RDSBBL R/W 00

24R MANID1 R 00

25R MANID2 R 2B

26R CHIPID1 R 57

27R CHIPID2 R 64


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12.2 Register description

Table 10 INTFLAG - byte0R

Table 11 INTMSK - byte1R / byte0W

Table 12 FRQSETMSB - byte2R / byte1W

bit Bitname Def R/W Functional description

7 DAVFLG 0 R DAVFLG = 1 RDS data is available

6 TESTBIT 0 R Internal Use

5 LSYNCFL 0 R LSYNCFL = 1 synchronisation is lost

4 IFFLAG 0 R IFFLAG = 1 IF count is not correct

3 LEVFLAG 0 R • Outside the tuning period the RSSI level is continuously checked using the following RSSIlevel: LEVFLAG = 1 RSSI level has dropped below (VSSL[1:0] - Vhys) table 23.

• During a tuning period (preset or search): LEVFLAG = 1 RSSI level has dropped belowVSSL[1:0] table 16.

2 PDFLAG 0 R PDFLAG = 1 a pause is detected

1 FRRFLAG 0 R FRRFLAG = 1 the tuner state machine is ready

0 BLFLAG 0 R BLFLAG = 1 during a search the bandlimit has been reached or time out


7 DAVMSK 0 R/W masks bit DAVFLG

6 - 0 R/W -

5 LSYMSK 0 R/W masks bit LSYNCFL

4 IFMSK 0 R/W masks bit IFFLAG

3 LEVMSK 0 R/W masks bit LEVFLAG

2 PDMSK 0 R/W masks bit PDFLAG and enables the Pause detection circuit

1 FRMSK 0 R/W masks bit FRRFLAG

0 BLMSK 0 R/W masks bit BLFLAG

IIC Bitname Def R/W Functional description

7 SUD 1 R/W 1 = search up, 0 = search down

6 SM 0 R/W 1 = search mode, 0 = preset mode

5 FR_13 0 R/W Frequency set bits, set the frequency of the PLL according to the formula in section 8.5.

4 FR_12 0 R/W

3 FR_11 0 R/W

2 FR_10 0 R/W

1 FR_09 0 R/W

0 FR_08 0 R/W


CONFIDENTIAL

Date: 2004 Nov 09

Page: 36

Table 13 FRQSETLSB - byte3R / byte2W

Table 14 TNCTRL1 - byte4R / byte3W

Table 15 TNCTRL2 - byte5R / byte4W

Table 16 Truth tables PUPD + SSL


7 FR_07 0 R/W Frequency set bits, set the frequency of the PLL according to the formula in section 8.5.

6 FR_06 0 R/W

5 FR_05 0 R/W

4 FR_04 0 R/W

3 FR_03 0 R/W

2 FR_02 0 R/W

1 FR_01 0 R/W

0 FR_00 0 R/W


7 PUPD_1 0 R/W Power up Power Down MSB - see PUPD truth table

6 PUPD_0 0 R/W Power up Power Down LSB - see PUPD truth table

5 BLIM 0 R/W 1 = Japan FM band 76 MHz to 90 MHz, 0 = US/Europe FM band 87.5MHz to 108 MHz

4 SWPM 0 R/W 1 = Software port is output of FRRFLAG, 0 = SWP

3 IFCTC 1 R/W 1 = IF count time = 15.02ms, 0 =IF count time = 2.02ms

2 AFM 0 R/W 1 = L-, R-audio muted, 0 = Audio not muted

1 SMUTE 0 R/W 1 = Soft mute on, 0 = off

0 SNC 0 R/W 1 = Stereo noise cancellation on, 0 = off


7 MU 1 R/W 1 = L-, R- Audio hard muted, 0 = no hard mute

6 SSL_1 1 R/W Search stop level MSB - see SSL truth table

5 SSL_0 0 R/W Search stop level LSB - see SSL truth table

4 HLSI 1 R/W 1 = high side injection, 0 = low side injection

3 MST 0 R/W 1 = forced mono, 0 = stereo “ON”

2 SWP 0 R/W 1 = SWPORT = “High”, 0 = SWPORT = “Low”

1 DTC 1 R/W 1 = deemphasis time constant = 50µs, 0 = deemphasis time constant = 75µs

0 AHLSI 0 R/W see section 8.25.1 for the functionality of this bit

PUPD truth table SSL truth table

PUPD_1 PUPD_0 status SSL_1 SSL_0 Search stop level

0 0 FM/RDS OFF 0 0 ADC3

0 1 FM ON / RDS OFF 0 1 ADC5

1 0 Not Used 1 0 ADC7

1 1 FM / RDS ON 1 1 ADC10


CONFIDENTIAL

Date: 2004 Nov 09

Page: 37

Table 17 FRQCHKMSB - byte6R

Table 18 FRQCHKLSB - byte7R

Table 19 IFCHK - byteR8

Table 20 LEVCHK - byteR8 + byte9R


7

6

5 PLL_13 - R Frequency output

4 PLL_12 - R

3 PLL_11 - R

2 PLL_10 - R

1 PLL_09 - R

0 PLL_08 - R


7 PLL_07 - R Frequency output

6 PLL_06 - R

5 PLL_05 - R

4 PLL_04 - R

3 PLL_03 - R

2 PLL_02 - R

1 PLL_01 - R

0 PLL_00 - R


7 IF_6 - R IF count MSB

6 IF_5 - R IF count bit





1 IF_0 - R IF count LSB

0


7 LEV_3 - R Level Count MSB

6 LEV_2 - R Level Count bit

5 LEV_1 - R Level Count bit

4 LEV_0 - R Level Count LSB

3 LD - R Lock Detect 1 = PLL is locked, 0 = PLL is not locked

2 STEREO - R 1 = pilot detected, 0 = no pilotnote: this does not switch the radio to mono or stereo, this depends on the RF input level as shownunder “mono stereo blend” or “mono stereo switched”

1

0


CONFIDENTIAL

Date: 2004 Nov 09

Page: 38

Table 21 TESTBITS - byte10R / byte5W

Table 22 TESTMODE - byte11R / byte6W

Table 23 LH - RSSI Level Hysteresis


7 LHM 0 R/W 1 = Left audio output is hard muted, 0 = not muted

6 RHM 0 R/W 1 = Reft audio output is hard muted, 0 = not muted

5 RDSCDA 0 R/W 1 = VAFL pin 25 is RDS clock and VAFR pin 24 is RDS data, 0 = normal operation

4 LHSW 0 R/W 1 = Level hysteresis is large, 0 = level; hysteresis is small

3 TRIGFR 0 R/W 1 = Reference Frequency selected pin 19, 0 = XTAL as reference pin 332 LDX 0 R/W 1 = Local DX on -6dB gain of LNA, 0 = Local DX off LNA has normal gain

1 RFAGC 0 R/W 0 = RFAGC on , 1 = RFAGC off

0 INTCTRL 0 R/W when INTCTRL is set to 1 this generates and interrupt on pin INTX


7 0 R/W

6 0 R/W

5 0 R/W

4 TM 0 R/W 1 =IC in testmode and software port outputs according to table 24, TM = 0 normal operation.

3 TB_3 0 R/W Test bits table 24 describes selection of signals outputted to the SWPORT when SWPM = 0When TM = 1, TB_[3:0] = 0, so effectively this is an and function.2 TB_2 0 R/W

1 TB_1 0 R/W

0 TB_0 0 R/W

RSSI ADCSearch Stop

Level

RSSI HysteresisThreshold LHSW =0

RSSI HysteresisThreshold LHSW =1

3 0 0

5 2 1

7 4 3

10 7 5


CONFIDENTIAL

Date: 2004 Nov 09

Page: 39

Table 24 Testbits (SWPM = 0)

TB_3 TB_2 TB_1 TB_0 SWPORT output signal

0 0 0 0 bit SWP of byte4W, depending on bits SWPM and SWP0 0 0 1 oscillator output 32.768 kHz, when TM =1

0 0 1 0 Lock Detect bit LD

0 0 1 1 Stereo bit STEREO

0 1 0 0 Programmable Divider, when TM =1

0 1 0 1 PSCOn see section 9.1.4.60 1 1 0 57 kHz clock

0 1 1 1 tri-state

1 0 0 0 output of RDS comparator

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1


CONFIDENTIAL

Date: 2004 Nov 09

Page: 40

Table 25 RDSSTAT1 - byte12R

Table 26 RDSTAT2 - byte13R

Table 27 Truth tables ELB + EPB

Table 28 Last Block ID addressing + Previous Block ID addressing


7

6 BLID_2 - R Block ID of Last block, see block ID truth table

5 BLID_1 - R Block ID of Last block

4 BLID_0 - R Block ID of Last block

3

2

1 ELB_1 - R nr. of Errors for last processed block

0 ELB_0 - R nr. of Errors for last processed block


7 BPID_2 - R Block ID of Previous block, see block ID truth table

6 BPID_1 - R Block ID of Previous block

5 BPID_0 - R Block ID of Previous block

4 EPB_1 - R nr. of Errors for previous processed block

3 EPB_0 - R nr. of Errors for previous processed block

2 SYNC - R SYNC = 1 RDS bitstream is synchronised, 0 = not synchronised

1 RSTD - R 1 =Power On Reset Detected

0 DOVF - R 1 = Data overflow occured during read operation, 0 =normal operation

ELB truth table EPB truth table

ELB_1 ELB_0 Nr. of corrected bits. EPB_1 EPB_0 Nr. of corrected bits.

0 0 No errors 0 0 No errors

0 1 Max 2 bits 0 1 Max 2 bits

1 0 Max 5 bits 1 0 Max 5 bits

1 1 Uncorrectable 1 1 Uncorrectable

BLID truth table BPID truth table

BLID_2 BLID_1 BLID_0 Block BPID_2 BPID_1 BPID_0 Block

0 0 0 A 0 0 0 A

0 0 1 B 0 0 1 B

0 1 0 C 0 1 0 C

0 1 1 D 0 1 1 D

1 0 0 C’ 1 0 0 C’

1 0 1 E 1 0 1 E

1 1 0 Inval. BL.E (RDBS) 1 1 0 Inval. BL.E (RDBS)

1 1 1 Invalid block 1 1 1 Invalid block


CONFIDENTIAL

Date: 2004 Nov 09

Page: 41

Table 29 RDSRLBMSB - byte14R

Table 30 RDSLBLSB - byte15R

Table 31 RDSPBMSB - byte16R

Table 32 RDSPBLSB - byte17R


7 BL_15 - R Last RDS Data Byte - MSB

6 BL_14 - R -

5 BL_13 - R -

4 BL_12 - R -

3 BL_11 - R -

2 BL_10 - R -

1 BL_9 - R -

0 BL_8 - R -


7 BL_7 - R -

6 BL_6 - R -

5 BL_5 - R -

4 BL_4 - R -

3 BL_3 - R -

2 BL_2 - R -

1 BL_1 - R -

0 BL_0 - R Last RDS Data Byte - LSB


7 BP_15 - R Previous RDS Data Byte - MSB

6 BP_14 - R -

5 BP_13 - R -

4 BP_12 - R -

3 BP_11 - R -

2 BP_10 - R -

1 BP_9 - R -


7 BP_7 - R -

6 BP_6 - R -

5 BP_5 - R -

4 BP_4 - R -

3 BP_3 - R -

2 BP_2 - R -

1 BP_1 - R -

0 BP_0 - R Previous RDS Data Byte - LSB


CONFIDENTIAL

Date: 2004 Nov 09

Page: 42

Table 33 RDSBBC - byte18R

Table 34 RDSGBC - byte19R

Table 35 RDSCTRL1 - byte20R / byte7W

Table 36 RDSCTRL2 - byte21R / byte8W


7 BBC_5 - R Bad Block Count MSB

6 BBC_4 - R -

5 BBC_3 - R -

4 BBC_2 - R -

3 BBC_1 - R -

2 BBC_0 - R Bad Block Count LSB

1 GBC_5 - R Good Block Count MSB

0 GBC_4 - R -


7 GBC_3 - R -

6 GBC_2 - R -

5 GBC_1 - R -

4 GBC_0 - R Good Block Count LSB

3

2

1

0


7 NWSY 0 R/W 1 = start new synchronisation, 0 = normal processing

6 SYM_1 0 R/W Error correction, see SYM truth table

5 SYM_0 0 R/W Error correction, see SYM truth table

4 RDBS 0 R/W 1 = RBDS processing mode, 0 = RDS processing mode

3 DAC_1 0 R/W RDS data output mode, see DAC truth table

2 DAC_0 0 R/W RDS data output mode, see DAC truth table

1 - 0 R/W -

0 - 0 R/W -


7 - 0 R/W -

6 - 0 R/W -

5 - 0 R/W -

4 BBG_4 1 R/W Bad Blocks Gain MSB

3 BBG_3 0 R/W Bad Blocks Gain bit



0 BBG_0 0 R/W Bad Blocks Gain LSB


CONFIDENTIAL

Date: 2004 Nov 09

Page: 43

Table 37 Truth tables SYM + DAC

Table 38 PAUSEDET - byte22R / byte9W

Table 39 Truth tables Pause Time + Pause Level

Table 40 RDSBBL - byte23R / byte10W

SYM Error corection truth table DAC RDS data output truth table

SYM_1 SYM_0 status DAC_1 DAC_0 Rds data output table

0 0 No correction 0 0 DAVA

0 1 Max 2 bits 0 1 DAVB

1 0 Max 5 bits 1 0 DAVC

1 1 No correction 1 1 Not used


7 PT_1 0 R/W Pause Time MSB, see PT truth table

6 PT_0 0 R/W Pause Time LSB, see PT truth table

5 PL_1 0 R/W Pause Level MSB, see PL truth table

4 PL_0 0 R/W Pause Level MSB, see PL truth table

3 GBL_5 0 R/W Number of Good Blocks Lose MSB

2 GBL_4 0 R/W -

1 GBL_3 0 R/W -

0 GBL_2 0 R/W -

PT truth table PL truth table

PT_1 PT_0 pause time PT [ms] PL_1 PL_0 Pause Level [kHz]L=R

0 0 20 0 0 1

0 1 40 0 1 1.6

1 0 80 1 0 2.5

1 1 160 1 1 4.0


7 GBL_1 0 R/W -

6 GBL_0 0 R/W Number of Good Blocks Lose LSB

5 BBL_5 0 R/W Number of Bad Blocks Lose MSB

4 BBL_4 0 R/W -

3 BBL_3 0 R/W -

2 BBL_2 0 R/W -

1 BBL_1 0 R/W -

0 BBL_0 0 R/W Number of Bad Blocks Lose LSB


CONFIDENTIAL

Date: 2004 Nov 09

Page: 44

Table 41 MANID1 - byte24R

Table 42 MANID2 - byte25R

Table 43 CHIPID1 - byte26R

Table 44 CHIPID2 - byte27R


7 VERSION 0 R Version codeN1D = 0000

N2A = 0001N2D = 0100N2E = 0101

6 VERSION 0 R

5 VERSION 0 R

4 VERSION 0 R

3 MAN ID 0 R Manufacturer ID code

2 MAN ID 0 R -

1 MAN ID 0 R -




6 MAN ID 0 R -

5 MAN ID 1 R -

4 MAN ID 0 R -

3 MAN ID 1 R -

2 MAN ID 0 R -


0 IDAV 1 R 1 =manufacturer ID available, 0 = CHIP has no ID


7 CHIP ID 0 R Chip identification Code

6 CHIP ID 1 R -

5 CHIP ID 0 R -

4 CHIP ID 1 R -

3 CHIP ID 0 R -

2 CHIP ID 1 R -

1 CHIP ID 1 R -




6 CHIP ID 1 R -

5 CHIP ID 1 R -

4 CHIP ID 0 R -

3 CHIP ID 0 R -

2 CHIP ID 1 R -

1 CHIP ID 0 R -



CONFIDENTIAL

Date: 2004 Nov 09

Page: 45

13 DC CHARACTERISTICSVCC = VDD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; unless otherwise specified the min. and max values include spread

due to: voltage from 2.5V to 3.3V; temperature from -20oC to 85oC;


Supply voltages

G1 VCC analog supply voltage 2.5 2.7 3.3 V

G4 VDD digital supply voltage 2.5 2.7 3.3 V

G8 VREFDIG digital supply voltage 1.65 1.8 VDD V

Supply currents

G2 ICC analog supply current operating

VCC = 2.5 V - 3.3V 10 13.7 18 mA

G3 standby mode

VCC = 2.5 V - 3.3V 0 1 5 µA

G5 IDD digital supply current operating

VDD = 2.5 V - 3.3V mA0.3 0.7 1.5

G6 standby modeVDD = 2.5 V - 3.3V µA10 18 25

G9 IREFDIG digital referencesupply current

operating

VVREFDIG = 1.65 V - VDDV 0 0.5 1 µA

DC operating points

DC1 VLOOPSW unloaded DC voltage VCD3 -0.2 − VCD3 V

DC2 VCPOUT 0.1 − VCD3 − 0.1 V

DC3 VLO1 VCD3 -0.1 − VCD3 V

DC4 VLO2 VCD3 -0.1 − VCD3 V

DC5 VRDSLP 1.15 V

DC8 VTMUTE measured w.r.t. CD3; VRF = 0 V 0.6 0.7 0.8 mV

DC10 VVAFL fRF = 98 MHz; VRF = 1 mV 720 850 940 mV

DC11 VVAFR fRF = 98 MHz; VRF = 1 mV 720 850 940 mV

DC12 VMPXOUT fRF = 98 MHz; VRF = 1 mV 680 815 950 mV

DC13 VMPXIN fRF = 98 MHz; VRF = 1 mV 780 mV

DC14DC15

VFREQIN TRIGFR = 1 1.3 1.5 1.7 V

TRIGFR = 0 0 0.05 0.1 V

DC16DC17

VXTALw.r.t. CD3

TRIGFR = 1 0.9 1.17 1.3 V

TRIGFR = 0 0.8 1 1.2 V

DC18 VRFIN1 420 530 680 mV

DC19 VRFIN2 420 530 680 mV

DC20 VCAGC VRF = 0 V 1 1.57 2 V


CONFIDENTIAL

Date: 2004 Nov 09

Page: 46

14 AC / DC CHARACTERISICSVCC = VDD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; all AC values are given in RMS; unless otherwise specified the min.

and max values include spread due to: voltage from 2.5V to 3.3V; temperature from -20oC to 85oC;


Voltage controlled oscillator

V1 fosc oscillator frequency 150 217 MHz

Reference frequency input, pin32

FR1 VFREFIN(osc) oscillator input voltage(pin 32)

externally clocked 0 VCC V

FR2 RFREFIN input resistance(pin 32)

externally clockedwith 32.768KHz

500 KΩ

FR3 CFREFIN input capacitance(pin 32)

externally clockedwith 32.768KHz

5 6 7 pF

Crystal oscillator 32.768KHz, pin33

FR4 fr series resonancefrequency at 25°C

the parasitic capacitance onthe PCB <= 2 pF

− 32.768 − kHz

FR5 ∆f/fr frequency deviation −20 +20 ppm

FR6 Cs shunt capacitance 3.5 pF

FR7 Cm motional capacitance 1.5 3.0 fF

FR8 Rs series resistance 75 KΩ

Reference frequency 32.768KHz, pin32

FR10 fr frequency @ 25°C − 32.768 − kHzFR11 ∆f/fr frequency deviation @ 25°C −20 +20 ppmFR12 ∆f/fr frequency deviation -20°C - +75°C −150 +150 ppmFR13 Duty Cycle square wave 30 70 %FR14 Input high level square wave 1.15 1.95 VFR15 Input low level square wave 0 0.55 VFR16 Jitter Integrated over the band

300Hz - 15kHz1 Hz

Synthesizer

PROGRAMMABLE DIVIDER

S1 Dprog programmable dividerratio

FRQSET[15:8] = XX11 1111andFRQSET[7:0]= 1111 1110

8191

S2 Dprog programmable dividerratio

FRQSET[15:8] = XX00 1000andFRQSET[7:0]= 0000 0000

2048

S3 Dstep programmable dividerstep size

1

CHARGE PUMP: PIN 2(CPOUT)

S5 Isink charge pump sink peakcurrent

0.2V < V1 <V4-0.2VfVCO > fREF ∗ divratio

250 500 1000 nA

S6 - Isource charge pump sourcepeak current

0.2V < V1 <V4-0.2VfVCO <fREF ∗ divratio

250 500 1000 nA


CONFIDENTIAL

Date: 2004 Nov 09

Page: 47

IF counter

I1 NIF IF counter length − 7 − bit

I2 VRF Sensitivity − 12 18 µV

I3 NIFcount IF count result for searchstop

20µV < Vrf < 1V 31 3C HEX

I4 T IF counter period IFCTC = 1IFCTC = 0fxtal = 32768Hz

156251953

µsµs

I5 RESIFCOUNT IF counter resolution fxtal = 32768Hz, 4096 Hz

LOGIC PINS , pin 10, 11, 13, 14, 8 - Clock, Data, Busenable

L1 Ri input resistance 10 − − MΩL2 Logic High Level input switching level up 0.7*V9 - V9+0.3 V

L3 Logic Low Level input switching level down -0.3 - 0.3*V9 V

Software programmable port; pin 7

L10 Vout(max) maximum output voltage V9-0.2 V9 V

L11 Vout(min) minimum output voltage 0 0.2 0.4 V

L12 Isink/source SWPORT minimumcurrent pin 7

500 µA

L13 Ileak SWPORT maximumleakage current pin 7

0< V7 < VVREFDIG V -1.0 1.0 µA

INTX, pin 20

L15 Vout(max) maximum output voltage 1.65 V < VVREFDIG < 1.95VRpull-up of second deviceconnected to INTX 18K +- 20%.ormaximum load current 200µA

V9-0.2 V9+0.2 V

L16 Vout(min) minimum output voltage 0.130 0.215 0.4 V

L17 Isink pull-down currentinterrupt output

500 680 1200 µA

L18 Rpull-up pull-up resistor 14.4k 18k 21.6k ΩL19 INTX low period One shot pulse time when the low period is not

shortened by a read action5 9.98 10 ms

FM SIGNAL CHANNEL

FM RF INPUT

RF1 Ri input resistance (pin 36and 37 to RFGND)

75 100 125 Ω

RF2 Ci input capacitance(pin 36 and 37 toRFGND)

2.5 4 6 pF

RF3 VRF Sensitivity EMF value fRF = 76 to 108MHz∆f=22.5kHz, fmod = 1kHz(S+N/N)=26dBdeemphasis = 75µsBAF= 300Hz to 15kHz

1 2 3.5 µV

RF4 IP3in inband 3rd-orderintercept point related toV36-37

∆f1=200kHz, ∆f2=400kHzftuned = 76 to 108MHzRFagc = off

81 87 dBµV



CONFIDENTIAL

Date: 2004 Nov 09

Page: 48

RF5 IP3out outband 3rd-orderintercept point related toV36-37

∆f1=4MHz, ∆f2=8MHzftuned = 76 to 108MHzRFagc = off

87 93 dBµV

INBAND AGC

RF6 VRF RF input voltage for startof AGC

fRF= 98MHz∆VTMUTE/∆VRF < 4mV/dBµV

55 61 67 dBµV

WIDEBAND AGC

RF7 VRF1 RF input voltage for startof AGC

fRF1 = 93MHz, fRF2 = 98MHzVRF2 = 50dBµV,∆VTMUTE/∆VRF1 < 4mV/dBµVradio tuned to 98MHz

66 72 78 dBµV

IF FILTER

IF1 fIF IF filter center frequency 215 225 235 kHz

IF2 BWIF IF filter bandwidth 85 94 102 kHz

IF3 S+200 high side 200kHzselectivity

∆f=+200kHzftuned = 76 to 108MHz

low and high side selectivitycan be measured bychanging the mixer from highside to low side LO injection

39 43 dB

IF4 S-200 low side 200kHzselectivity

∆f=-200kHzftuned = 76 to 108MHz

32 36 dB

IF5 S+-100 high/ low side100kHzselectivity

∆f=+-100kHzftuned = 76 to 108MHz

8 12 dB

IF6 αimage image rejection ftuned = 76 to 108MHz,VRF = 50dBµV

24 30 dB

FM IF LEVEL DETECTOR AND MUTE VOLTAGE

LE1 Vlevel level output DC voltage VRF = 0 µV 1.55 1.65 1.8 V

LE2 Vlevel level output DC voltage VRF = 3 µV 1.6 1.7 1.85 V

LE3 Slevel slope of level voltage(∆Vlevel / ∆VRF)

VRF = 10µV to 500 µV 150 165 180

LE4 VRF level ADC start byte9R = 0001 0000 2 3 5 µV

LE5 ∆VRF level ADC step size 2 3 5 dB

LE6 Ro output resistance(pin 23)

280 400 520 KΩ

FM Demodulator

D1 VMPXOUT demodulator outputvoltage

VRF=1mV, L=R, ∆f=22.5kHz,fmod = 1kHzdeemphasis = 75µsBAF = 300Hz to 15kHz

60 75 90 mV

D2 RMPXOUT demodulator outputresistance

500 Ω

D3 IsinkMPXOUT demodulator output sinkcurrent

30 - - µA


mV20 dB---------------


CONFIDENTIAL

Date: 2004 Nov 09

Page: 49

D4 (S+N/N) maximumsignal-to-noise ratio

VRF=1mV, L=R, ∆f=22.5kHzfmod = 1kHzdeemphasis = 75µsBAF = 300Hz to 15kHz

57 60 dB

D5 THD total harmonic distortion VRF=1mV, L=R, ∆f=75kHzfmod = 1kHzdeemphasis = 75µsBAF= 300Hz to 15kHz

0.4 0.9 %

D6 THD total harmonic distortionoverdrive

VRF=1mV, L=R, ∆f=100kHzfmod = 1kHz, deemphasis =75µs, BAF= 300Hz to 15kHz

1 %

D7 VMPXFM/VMPXFM AM suppression L=R, ∆f=22.5kHz, fmod =1kHzVRF= 100µV -> VRF= 10mV

m=0.3, deemphasis = 75msBAF= 300Hz to 15kHz

-40 dB

Soft Mute

SM1 Soft mute startlevel

Mute attenuation = 3dB SMUTE = 1, relative to VAFL@ VRF = 1 mV, ∆f=22.5kHz,fmod = 1kHz

3 5 10 uV

SM2 αmute mute attenuation VRF= 1µV, L=R, ∆f=22.5kHzfmod = 1kHz,deemphasis = 75µsBAF= 300Hz to 15kHzSMUTE = 1

10 20 30 dB

MPX Decoder

M1 VAFL,VAFR, L-, R-AF output voltage VRF= 1mV, L=R, ∆f=22.5kHzfmod = 1kHz, deemphasis =75µs

60 75 90 mV

M2 RAFL, RAFR left, right audio outputresistance

MU = LHM = RHM =0RDSCDA = 0, AFM = 0 orAFM =1

50 100 Ω

M3 RAFL, RAFR left, right audio outputresistance when muted

MU = LHM = RHM = 1RDSCDA = 0

500 kΩ

M4 IsinkAFL, IsinkAFR left, right audio outputsink current

170 µA

M5 Vmaxmpxin input overdrive margin THD = 3% relative to fAF =1kHz, VAF = 250mV

4 dB

M6 ∆VAF=VAFL/VAFR L-, R-AF output voltagedifference

VRF= 1mV, L=R, ∆f=75kHzincluding 9% pilot,fmod = 1kHz,deemphasis = 75µs

-1 1 dB

M7 αsep stereo channelseparation

VRF= 1mV, ∆f=75kHzincluding 9% pilot, R=1, L=0or R=0, L=1, fmod = 1kHzMST = 0, SNC = 1

27 dB



CONFIDENTIAL

Date: 2004 Nov 09

Page: 50

M8 AFBWH Higher Audio bandwidth-3dB point

VRF= 1mV, ∆f=22.5kHz, L=R,preemphasis = 75µs,deemphasis = 75µs, with Cbetween 27 - 26 = 33n +- 5%

13 15 17 kHz

M9 AFBWL Lower Audio bandwidth-3dB point

VRF= 1mV, ∆f=22.5kHz, L=R,preemphasis = 75µs,deemphasis = 75µs, with Cbetween 27 - 26 = 33n +- 5%

20 25 30 Hz

M10 (S+N/N) maximumsignal-to-noise ratiomono

VRF= 1mV, ∆f=22.5kHz, L=R,fmod = 1kHz, deemphasis =75 µs , BAF= 300Hz to 15kHz+ A-weighting filter

56 59 dB

M11 (S+N/N) maximumsignal-to-noise ratiostereo

VRF= 1mV, ∆f=22.5 kHz,L=R, fmod = 1kHz, pilot = 6.75kHz, deemphasis = 75 µs,BAF= 300Hz to 15kHz +A-weighting filter

52 55 dB

M12 THD total harmonic distortionMONO

VRF= 1mV, ∆f=75kHz , L=Rfmod = 1kHz, no pilot,deemphasis = 75µs

0.4 0.9 %

M13 THD total harmonic distortionSTEREO

VRF=1mV, L=1 R=0,∆f=75kHz including 9% pilot,fmod = 1kHz, deemphasis =75µs, BAF= 300Hz to 15kHz

0.9 2.5 %

M14 α19 Pilot suppressionmeasured at pins VAFL,VAFR

related to ∆f=75kHz including9% pilot, fmod = 1kHzdeemphasis = 75µs

40 50 dB

M15 ∆fpilot1 stereo pilot frequencydeviation

VRF = 1mVSTEREO = 1

3.6 5.8 kHz

M16 ∆fpilot2 stereo pilot frequencydeviation

VRF = 1mVSTEREO = 0

1.0 3 kHz

M17 ∆fpilot1/∆fpilot2 pilot switch hysteresis VRF = 1mV 2 6 dB

M18 Tdeem deemphasis timeconstant

VRF = 1mVDTC = 1DTC = 0

3857

5075

6293

µsµs

Mono stereo blend

M20 Mono/stereoblend start level

With increasing inputlevels the radio switchesgradually from mono tostereo.

stereo channel separation=1dB, SNC = 1.

2 4 20 µV

M21 αsep stereo channelseparation

VRF= 30µV, ∆f=75kHzincluding 9% pilot, R=1, L=0or R=0, L=1,fmod = 1kHzMST = 0 ,SNC = 1

4 10 16 dB

Mono stereo switched

M23 αsep stereo channel separationswitching from mono tostereo with increasing RFinput level

VRF= 30µV, ∆f=75kHzincluding 9% pilot, R=1, L=0or R=0, L=1, fmod = 1kHzMST = 0 , SNC = 0

27 33 dB



CONFIDENTIAL

Date: 2004 Nov 09

Page: 51

M24 αsep stereo channel separationswitching from stereo tomono with decreasing RFinput level

VRF= 10µV, ∆f=75kHzincluding 9% pilot, R=1, L=0or R=0, L=1, fmod = 1kHzMST = 0 , SNC = 0

1 dB

M25 Mono/stereoswitching level

The mono stereo switchinglevel is the RF input level forswitching from mono-tostereo.

∆f=75kHz, including 9% pilot,fmod = 1kHz, SNC = 0

17 22 32 µV

M26 Mono/stereohysteresis

∆f=75kHz, including 9% pilot,fmod = 1kHz, SNC = 0

3 3.5 4 dB

Bus driven Mute funtions

Tuning mute

MU1 αmute VAFL,VAFR ,mutingdepth

AFM = 1 -60 dB

MU2 αmute(L) VAFL muting depth AFM = 1, LHM = 1 -80 dB

MU3 αmute(R) VAFR muting depth AFM = 1, RHM = 1 -80 dB

RDS demodulator / decoderR1 IRDS IDD current when RDS is running 0.3 0.7 1.5 mA

R2 VinRF RDS Sensitivity EMFvalue

∆f=22.5kHz, fAF = 1kHz, L=R,∆fRDS=1.2kHz, deemphasis =50µs,Block Quality Rate >= 85%,SYM_1=0 and SYM_0=0,average over 2000 blocks

20 30 µV

R3 VinRF RDS Sensitivity EMFvalue

∆f=22.5kHz, fAF = 1kHz, L=R,∆fRDS=2kHz, deemphasis =50µs,Block Quality Rate >= 95%,SYM_1=0 and SYM_0=0,average over 2000 blocks

12 18 µV

R4 fc(RDS) RDS filter center frequency 56.5 57 57.5 kHz

R5 B-3dB RDS filter Bandwidth 2.5 3 3.5 kHz

Pause DetectorP1 ∆f pause Pause detection threshold fmod=1kHz, L=R,

PL_0=0, PL_1=00.7 1.0 1.4 kHz



CONFIDENTIAL

Date: 2004 Nov 09

Page: 52

0 dB

-10

-20

-30

-40

-50

-60

-70

-80

TEA5764HN-N2D, VCC=2.7V, 25 deg

Remark: AFoutR, A_weighting, BPF 300Hz-15kHz

0.1 µV 1 µV 10 µV 100 µV 1 mV 10 mV 100 mV 1 V

4.0 %

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Input Level

Date: Monday, 18 October 2004, 15:26Owner: 4m

Signal

Signal Inc RF: FM: 22.5 kHz AF: 1000 HzKey data:

dB = 0 71 mV at 3 µV RF dB = -3 1.0 µV dB = 26 1.4 µV

RF Frequency: 98 MHzMeasurements/Decade: 12

Noise

Noise Inc RF:

Key data: dB = 0 71 mV at 3 µV RF dB = -3 1.0 µV dB = 26 1.4 µV


THD

THD Inc RF: FM: 75 kHz AF: 1000 Hz



Fig.14 Mono Characteristics

(1) Mono signal, Softmute off

(2) Noise in mono mode,Softmute off

(3) Total harmonic distortion ∆f = 75 kHz

1

2

3


CONFIDENTIAL

Date: 2004 Nov 09

Page: 53

0 dB

-10

-20

-30

-40

-50

-60

-70

-80

TEA5764HN-N2D, VCC=2.7 V , 25 deg

Remark: AFoutR, A_weighting, BPF 300Hz-15kHz , SNC on


4.0 %

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Input Level

TH

D +

N

Date: Monday, 18 October 2004, 16:07Owner: 4s

Right (R=1, L=0)

Right (R=1, L=0) Inc RF: FM: Stereo: R at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHzKey data:



Stereo Noise

Stereo Noise Inc RF: FM: Stereo: L at 0 kHz AF: 1000 Hz Pilot at 6.75 kHz



Right (R=0, L=1)

Right (R=0, L=1) Inc RF: FM: Stereo: L at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHz



THD (stereo)

THD (stereo) Inc RF: FM: Stereo: R at 67.5 kHz AF: 1000 Hz Pilot at 6.75 kHz



Fig.15 Stereo Characteristics

(1) VAFL signal, Softmute off

(2) VAFR signal, Softmute off

(3) Noise in stereo mode,Softmute off


1

2

3

4


CONFIDENTIAL

Date: 2004 Nov 09

Page: 54

0 dB

-10

-20

-30

-40

-50

-60

-70

-80

TEA5764HN-N2D, VCC=2.7V, 25 deg

Remark: AFoutR, A_weighting, BPF 300Hz-15kHz, Soft mute on


4.0 %

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Input Level

Date: Monday, 18 October 2004, 16:36Owner: 4m

Signal

Signal Inc RF: FM: 22.5 kHz AF: 1000 HzKey data:



Noise

Noise Inc RF:



THD

THD Inc RF: FM: 100 kHz AF: 1000 Hz



Fig.16 Sofmute and Overdrive Characteristics

(1) Mono signal, softmute on

(2) Noise in mono mode, softmute on


1

2

3


CONFIDENTIAL

Date: 2004 Nov 09

Page: 55

0.1

1

10

100

1000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Fig.17 Level ADC conversion

Level ADC output

VRF [µV]


CONFIDENTIAL

Date: 2004 Nov 09

Page: 56

15 LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. Machine Model l (R = 0 Ω, C = 200 pF).

2. Human body model (R = 1.5 kΩ, C = 100 pF).

3. Charged Device Model (JEDEC Standard JESD22-C101[4]).

16 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V2 VCO tuned circuit output 1 −0.3 (+8) V

V3 VCO tuned circuit output 2 −0.3 (+8) V

V15 digital supply voltage −0.3 (+5.5) V

V34 analog supply voltage −0.3 (+8) V

Tstg storage temperature −55 +150 °CTamb operating ambient temperature −40 +85 °CVes electrostatic handling ESD note 1 −200 +200 V

note 2 −2000 +2000 V

note 3 −500 +500 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) HVQFN40 thermal resistance from junction to ambient in free air 80 K/W


CONFIDENTIAL

Date: 2004 Nov 09

Page: 57

17 PACKAGE OUTLINE

terminal 1index area

0.51

A1 EhbUNIT ye

0.2

c

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 6.15.9

Dh

4.253.95

y1

6.15.9

4.253.95

e1

4.5

e2

4.50.300.18

0.050.00

0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT618-1 MO-220- - - - - -

0.50.3

L

0.1

v

0.05

w

0 2.5 5 mm

scale

SOT618-1HVQFN40: plastic thermal enhanced very thin quad flat package; no leads;40 terminals; body 6 x 6 x 0.85 mm

A(1)

max.

AA1

c

detail X

yy1 Ce

L

Eh

Dh

e

e1

b11 20

40 31

30

2110

1

X

D

E

C

B A

e2

01-08-0802-10-22

terminal 1index area

1/2 e

1/2 e

ACC

Bv M

w M

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1) E(1)


CONFIDENTIAL

Date: 2004 Nov 09

Page: 58

18 OUTLINE-WFBGA34-2


CONFIDENTIAL

Date: 2004 Nov 09

Page: 59

19 SOLDERING

19.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our“Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable forsurface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is oftenused.

19.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to theprinted-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times(preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages shouldpreferable be kept below 230 °C.

19.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards witha high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smoothlaminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport directionof the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuitboard.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of theprinted-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residuesin most applications.

19.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering ironapplied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between270 and 320 °C.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 60

19.5 Suitability of surface mount IC packages for wave and reflow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximumtemperature (with respect to time) and body size of the package, there is a risk that internal or external packagecracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to theDrypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it isdefinitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGESOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable


CONFIDENTIAL

Date: 2004 Nov 09

Page: 61

20 DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUSPRODUCTSTATUS

DEFINITIONS (1)

Objective specification Development This data sheet contains the design target or goal specifications forproduct development. Specification may change in any manner withoutnotice.

Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will bepublished at a later date. Philips Semiconductors reserves the right tomake changes at any time without notice in order to improve design andsupply the best possible product.

Product specification Production This data sheet contains final specifications. Philips Semiconductorsreserves the right to make changes at any time without notice in order toimprove design and supply the best possible product.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 62

21 DEFINITIONS

Short-form specification The data in a short-form specification is extracted from a full data sheet with the same typenumber and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These arestress ratings only and operation of the device at these or at any other conditions above those given in the Characteristicssections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information Applications that are described herein for any of these products are for illustrative purposesonly. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specifieduse without further testing or modification.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 63

22 DISCLAIMERS

Life support applications These products are not designed for use in life support appliances, devices, or systemswhere malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductorscustomers using or selling these products for use in such applications do so at their own risk and agree to fully indemnifyPhilips Semiconductors for any damages resulting from such application.

Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products,including circuits, standard cells, and/or software, described or contained herein in order to improve design and/orperformance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveysno licence or title under any patent, copyright, or mask work right to these products, and makes no representations orwarranties that these products are free from patent, copyright, or mask work right infringement, unless otherwisespecified.

23 REFERENCES

[1] “The I2C-Bus Specification” Version 2.1 January 2000

[2] “Specification of the radio data system (RDS) for VHF/FM sound broadcasting range from 87.5 to 108MHz”, BSEN50067:1998

[3] Datasheet, TEF6892H Car radio integrated signal processor, 2002 Sep 13.

[4] JEDEC Standard JESD22-C101

[5] Datasheet, SAA6588 RDS/RBDS pre-processor, 2002 Jan 14.


CONFIDENTIAL

Date: 2004 Nov 09

Page: 64

24 REVISION HISTORY

From V2.4 (04 feb 2004) to V2.5 (03 jun 2004)

Chapter 3

- Updated electrical parameters general changed condtions all are set to 2.7V

- updated limits

Chapter 4

- updated specpoint for IP3 and changed conditions

- new limits for (S+N/N)

- moved min limit for RDS sensitivity spec

Chapter 5

- added name for WL-CSP package

Chapter 6

- changed value of decoupling capacitor, connected to CD3, back to 33nF

Chapter 7

- added column with positions for WL-CSP

- changed name TIFCENTER to DGND in figure 3

Chapter 8

- updated sections: 8.6, 8,7, 8.11, 8.19, 8.20, 8.25, 8.26

- updated table 2 Tuner truth table and table 3 RDS update truth table

- updated figure 5 flowchart autosearch or preset

- updated figure 6 flowchart RDS update

Chapter 9

- updated figure 7 I2C interrupt sequence

- updated section 9.1.4.2 DAVFLG

- updated section 9.1.4.3 LSYNCFL

- updated section 9.1.4.4 IFFLAG

- updated section 9.1.4.5 LEVFLAG

- updated section 9.1.4.6 PDFLAG

- section 9.2 updated description of interrupt line behaviour and figure 9

Chapter 10

- complete update including all pictures, reflecting the behaviour of the TEA5764N2

Chapter 11

- put correct address for starting point when using the RDS I2C address

- removed influence of BUSENABLE on standby current

Chapter 12

- table 14 changed upper limit of Japan band

- table 24 renamed to testbits and updated functionality


CONFIDENTIAL

Date: 2004 Nov 09

Page: 65

Chapter 13

- added DC characteristics

Chapter 14

- new numbering

- adjusted limits of: I3, L2, L3, L17, RF4, RF5, D3, M2, M3, M20, R2, R3

- updated conditions for: L17, RF4, RF5, SM1, M1, M5, M21, M23,R2, R3

- added: M8, M9, M11, M13

Chapter 15

- added specpoint for Charge Device Model

From V2.5 (03 jun 2004) to V2.6 (04 jun 2004)

Chapter 6

- Updated blockdiagram connection of CAGC from GND to CD3 (pin 39)

- updated table 1 removed 2 capacitors

From V2.6 (04 jun 2004) to V2.7 (09 nov 2004)

- Page 1 changed status from Objective to Preliminary

Chapter 3

- specpoint G1 changed voltage range from 2.4 - 5.0 V to 2.5 - 3.3 V

- specpoint G3 changed limits


Chapter 6

- blockdiagram added 12pF in series with pin 33

- table 1 added 12pF to list of components

Chapter 8

- section 8.5 added statement which bytes trigger the PLL

- section 8.7 changed default setting of AGC

- section 8.12 added comment about ADC level 3

- section 8.13 updated reference to figures 15 and 17

- section 8.20 changed dependency of POR from VCC to VDD and added statement about order of switching on powersupplies

- section 8.25 added comment about preset after search

Chapter 9

- section 9.1.4.6 updated functionality of pause detector and updated figure 8


CONFIDENTIAL

Date: 2004 Nov 09

Page: 66

Chapter 10

- updated figure 10; red is changed

- updated figure 12; red is changed

Chapter 11

- section 11.1 changed table 9 removed byte0W

Chapter 12

- table 21 changed functionality of RFAGC

- table 24 changed text of setting 0000 and changed ouput of setting 0101

Chapter 13

- changed conditions for which the figures in chapter 13 are valid

Chapter 14

- changed conditions for which the figures in chapter 14 are valid



- specpoint G3 changed limits

- specpoint G2, G3, G4, G5 changed conditions set to 2.5 - 3.3 V

- specpoint DC6 and DC7 removed

- specpoint DC8 changed output of TMUTE voltage, now w.r.t. CD3

- specpoint DC16 and DC17 changed limits

- specpoint FR4 added condition

- specpoint FR15 changed upper limit set to 0.55V

A1

B1

C1

D1

A2

B2

INTX

read intflg+RDS on INTX

tRead

21.9ms

BL Register

BP Register x

B1

C1

B1

C1

Data Overflow bit

B1

If there is no read cycle, B1 is placed inthe BP register and the new block C1 isnow in the BL register. The DOVF bit is

set to indicate two blocks available.

DAV-A/B: Normal

DOVF set when 2 new blocksreceived in BL/BP

DOVF is cleared when theBL is read. To be of useDOVF has to be read be-fore BL and BP registers

DecoderRegisters

A2

Instant copy of decoder buffer to BLregister and BL register to BP registerafter reading RDSR4. The block in BL

is concidered as a new block.

TINT_RD

<~ 10ms

A1

Being decoded

In the decoder buffer

B1

A1

C1

B1

D1

C1

A2

D1 A

2

B2

C2

A2

>2ms

end read intmsk

In order not to lose D1a read must have beenperformed before A2has been decoded.

DAVFLGDAVFLG set onDAVN=0, cleared on

read BL-reg

B2

TINT_RD

Read BL Read BL Read BL

D1

C1

A2

D1

D1

A2

A1

A2

A2

B2

To prevent DOVF tobe set again, anextra read of BL

must be performedbefore A2 has been

decoded

BusRegisters

A1

B1

C1

D1

A2

B2

DAVFLG

INTX


tINTX

TINT_RD

tRead

21.9ms

BL Register

BP Register

A1

D0

A2

Data Overflowbit


tRead

DAVFLG(Case 2)

Case2: Late read of BL, BP register

Case 1: Normal DAV-C mode

Dashed line shows what would happen if no read occured at (a). DOVF bit setuntil the next read of BP register, however,D1,A2 would be lost.

(a)

INTX cleared @ end read INTMSK

DAVFLG not cleared as no read performed

C0

D0

D1

D1

No read on INTX soB1 will be lost

DAVFLG reset when1st new block wouldhave been copied toBL register

B1 copied to BLreg shortly beforeC1 decoded

BLreg copied to BPregand C1 to BLreg

tINTX

= 10 ms

DAVFLG cleared @ end read BPregand forced to zero till en read RDSR4

C1

A1 C

1

Instant copy of C1

fromdecoder buffer to BLand BL to BP justbefore D

1 decoded

due to read action.

2 new blockshave arrived inBL/BP register

2 new blocks have arrived in BL/BP (C1,D

1) and a new block (A

2)

has entered the decoder buffer. Hence, DOVF is set again. Toprevent this, an extra read must be performed after reading (a).

DAVFLG set when 2 nd new blockin decoder buffer

Instant copy A2

from decoderbuffer to BL andBL to BP

Beingdecoded


CONFIDENTIAL

Date: 2004 Nov 09

Page: 67

- specpoint L12 changed text maximum to minimum

- specpoint L13 changed conditions from 5V to VVREFDIG V

- specpoint M2 removed preemphasis from conditions

- specpoint M11 removed text “no pilot” from conditions

- specpoint M12 added “no pilot” to conditions

- specpoint M13 changed upper limit, set to 2.5% added “including 9 pilot” to conditions

- specpoint M20 added limits

- specpoint M21 changed from 40uV to 30uV

- specpoint M23 added typical value 33dB

- specpoint M24 changed from 20uV to 10uV



- specpoint R2 updated limits and removed preemphasis from conditions

- specpoint R3 removed preemphasis from conditions

- page 53 updated figure 14 Mono Characteristics

- page 54 updated figure 15 Stereo Characteristics

- page 55 updated figure 16 Softmute and Overdrive Characteristics

- page 56 added figure 17 Level ADC conversion


CONFIDENTIAL

Date: 2004 Nov 09

Page: 68

tea 5764

Documents

wj brummelman2

revision history

wj brummelman1

rds data processing

rds synchronisation

interrupt flags

interrupt clearing209

interrupt line