tapeout review form for cell-based ic example

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1.
( full-custom )
1-5 200MHz
clock domain
clock domain clock CLK1200MHz CLK250MHz
1-6 50mW
1-8
( 2 10 17)
TSMC 0.18UM CMOS HIGH VOLTAGE MIXED SIGNAL BASED GENERATION II BCD
1P6M SALICIDE AL_FSG 1.8/ 5/ 6/ 7/ 8/ 12/ 16/ 20/ 24/ 29/ 36/ 45/ 55/ 65/ 70V/ VG1.8/ 5V AND
5/ 6/ 7/ 8/ 12/ 16/ 20/ 24/ 29/ 36/ 45/ 55/ 65/ 70V/ VG5V
( 3 10 17)
TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V
( 4 10 17)
TSMC 90 nm CMOS Mixed Signal MS General Purpose Standard Process LowK Cu 1P9M
1.0&3.3V (With UTM)
( 5 10 17)
TSMC 40 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V
( 6 10 17)
TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus ELK Cu 1P10M
0.9/2.5V
( 7 10 17)
TSMC 16 nm CMOS LOGIC FinFET Compact(Shrink) LL ELK Cu 1P13M 0.8/1.8V
( 8 10 17)
UMC 0.18um Mixed-Mode and RFCMOS 1.8V/3.3V 1P6M Metal Metal Capacitor Process
( 9 17)
EN T E XA M PL E
2-1 Core library
2.1.1 Core library CBDK_TSMC035_TSMC_v7.0
/cad/CBDK/CBDK035_TSMC_TSMC/01_rev.txt
2.1.2 cell name ( cell name )
2.1.3 core filler
2-2 IO library
2.2.1 IO library CBDK035_TSMC_TSMC_v7.0 D35/IOPAD_STC
1CBDK035_TSMC_TSMC_v7.0/cad/CBDK/CBDK035_TSMC_TSMC
2.2.5 corner cell R0
2-3 Dummy Pattern

2.3.2 mixed-signal full-custom dummy pattern
Layer FUSE[FW(235)] block layer cell-based replace
dummy pattern
2.3.3 addDummyCell dummy pattern
2-4 DRC
2.4.2 Queue server DRC :
2.4.3 Queue sever DRC
2.4.3.1 DRC
2.4.3.2
http://www2.cic.org.tw/~shuttle/drc/all/D35.pdf
Whole Chip DRC AMS
CORE CORE I/O PAD
CB.R.1~4
CB.C.1~2
CB.S.1~4
Error Free
CB rule
EN T E XA M PL E
NW.W.2 VDDI_33 VDDE_33
AIN_33
NW.W.2
NW.S.1
CO.E.1
NW.W.2 C_VDDIC_VDDE C_VSSI
AIN_05
AIN_05
NET_AREA_RATIO_RDBS
PO.R.1
M1.R.1
M2.R.1
M3.R.1
M4.R.1
Density
2-5 LVS
2.5.1 Queue server DRC layout LVS
2.5.2 CIC blackbox
2.5.3 LVS Calibre LVS
2.5.4 LVS
2.5.5
2.5.6 Queue server DRC Short_Check_With_Dummy
lvs.rep.ext lvs.rep.short LVS

: Queue server Post-layout transistor level

3. TSMC 0.18UM CMOS HIGH VOLTAGE MIXED SIGNAL BASED GENERATION II BCD 1P6M
SALICIDE AL_FSG 1.8/ 5/ 6/ 7/ 8/ 12/ 16/ 20/ 24/ 29/ 36/ 45/ 55/ 65/ 70V/ VG1.8/ 5V AND 5/ 6/ 7/ 8/ 12/
16/ 20/ 24/ 29/ 36/ 45/ 55/ 65/ 70V/ VG5V
3-1 Core library
3.1.1 Core library CBDK_T18HVG2_ARM_v4.0
/cad/ CBDK/CBDK_T18HVG2_ARM/01_rev.txt
3.1.3 core filler
3-2 Dummy Pattern

TS RI D OC UM
EN T E XA M PL E
page 4 / 16
V4.9
Layer DMEXCL (Layer number 150 ; Data type 1~6)Layer ODBLK
(Layer number 150 ; Data type 20) Layer POBLK (Layer number 150 ; Data type 21)
Block Layer 8 Layer Cell-Based replace dummy
pattern
3-3 DRC
3.3.2 Queue server DRC
3.3.4.1 DRC
3.3.4.2
: http://www2.cic.org.tw/~shuttle/drc/all/T18HVG2.pdf
DRM.R.1 T-018-CV-DR-027
DOD.R.1 OD density
3-4 LVS
3.4.2 CIC blackbox
3.4.4 LVS
3.4.5


4. TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V
4-1 Core library
4.1.1 Core library CBDK_TSMC018_Arm_v4.0
/cad/ CBDK/CBDK_TSMC018_Arm/01_rev.txt
4.1.3 core filler
TS RI D OC UM
EN T E XA M PL E
Spec(*.spec) ROM(*.txt)

(2) ROMexample2.spec (ROMexample2.txt)
4.2.1
4.2.2 UNIX LINUX vi ( vi
, ROM )
4-3 IO library
4.3.1 IO library T018MMIO001 CBDK_TSMC018_Arm_v4.0
4.3.2 IO filler
4.3.3 bonding pad
(C-1 C-3) CBDK_TSMC018_Arm_v4.0 IO library
C-1. power domain PVDD2POC PAD
C-2. addTagCell
C-3. Corner Cell R0
4-4 Dummy Pattern

pattern
4-5 DRC
4.5.3.1 DRC
4.5.3.2
4.5.4 Queue server DRC DRC
http://www2.cic.org.tw/~shuttle/drc/all/T18.pdf
EN T E XA M PL E
RES.2 RES.4_PO RES.8 NW.S.1.1
ESD.24g ESD.25g ESD.28g ESD.34g
OD.EX.1 LUP.1g LUP.2g DRM.R.1
OD.R.1 NET_AREA_RATIO_RDBS FPAD.R.1 NW.R.1
DOD.DN.1 DOD.DN.2 CTM.R.2 UTM20K.C.1
TSMC18 Density DRC
4-6 LVS
4.6.2 CIC blackbox
4.6.4 LVS
4.6.5


5. TSMC 90 nm CMOS Mixed Signal MS General Purpose Standard Process LowK Cu 1P9M 1.0&3.3V
(With UTM)
5.1.1 Core library CBDK_TSMC90GUTM_Arm_v1.2
/cad/ CBDK/CBDK_TSMC90GUTM_Arm_v1.2/01_rev.txt
5.1.3 Core cell multi-Vt
5.1.4 core cell RVT HVT
5.1.5 core filler
5-2 memory
TS RI D OC UM
EN T E XA M PL E
page 7 / 16

(2) ROMexample2.spec (ROMexample2.txt)
t90utm_sram_dp_adv
t90utm_rf_sp_adv
t90utm_rf_dp_adv
5.2.1
, ROM )
5-3 IO library
5.3.1 IO library CBDK_TSMC90GUTM_Arm_v1.2
5.3.2 power domain PVDD2POC_33 PAD
5.3.3 IO filler
5.3.4 bonding pad
5.3.5 addTagCell
5-4 CIC ADPLL IP
5.4.1 ADPLL IP ADPLL_TSMC90GUTM_CIC_v1.0
5-5 CIC CPU IP ( 16)
5.5.1 CPU AndesCore
5-6 Dummy Pattern

pattern
5-7 DRC
5.7.2 Queue server DRC
18-3-9_cic01c_DRC_10700
5.7.4.1 DRC DRC.rep
5.7.4.2
EN T E XA M PL E
page 8 / 16
DRC
Density CBDK Circuit –addDummy
Density
TN90GUTM density DRC
M1.DN.1_M1.DN.3H M2.DN.1_M2.DN.3H M3.DN.1_M3.DN.3H
M4.DN.1_M4.DN.3H M5.DN.1_M5.DN.3H M6.DN.1_M6.DN.3H
M7.DN.1_M7.DN.3H M8.DN.1_M8.DN.3H UTM.DN.1_UTM.DN.3H
M4.DN.1_M4.DN.3 L M5.DN.1_M5.DN.3 L M6.DN.1_M6.DN.3 L
M7.DN.1_M7.DN.3 L M8.DN.1_M8.DN.3 L UTM.DN.1_UTM.DN.3 L
DOD.R.1 DPO.R.1 DM1.R.1
DM2.R.1 DM3.R.1 DM4.R.1
DM5.R.1 DM6.R.1 DM7.R.1
http://www2.cic.org.tw/~cis/chipapply/doc/handout.pdf
5-8 LVS
5.8.2 CIC blackbox
TS RI D OC UM
EN T E XA M PL E
5.8.5


6. TSMC 40 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V
6-1 Core library
6.1.1 Core library CBDK_TSMC40_core_Arm_v2.0 CBDK_TN40G_ITRI_v3.1

6.1.4 core cell LVT RVT HVT
6.1.5 core filler
6.1.6 Core cell core filler Layout :
6-2 memory

(2) 1024 X 8
6.3.1 IO library CBDK_TSMC40_io_TSMC_v2.0
6.3.2 power domain PVDD2POC PAD
6.3.3 IO filler
6.3.4 bonding pad
6.3.5 addTagCell
6-4 Dummy Pattern

pattern
6-5 DRC
EN T E XA M PL E
page 10 / 16
DRC
DTCD.DN.2
DRM.R.1 Wirebond rule Antenna rule
6.5.2 6.5.1 DRC
TN40G DRC

6-6 LVS
6.6.2 CIC blackbox
6.6.4 LVS
6.6.5
7. TSMC 28 nm CMOS RF High Performance Compact Mobile Computing Plus ELK Cu 1P10M 0.9/2.5V

7.1.1 Core library CBTK_TSMC28HPCPlus_core_TSMC_v1.0
7.1.4 core cell LVT RVT HVT
7.1.5 core filler
7.1.6 Well Tap Cell (Cell Name: TAPCELLBWP12T30P140)
7.1.7 End Cap Cell
(Cell Name: BOUNDARY_LEFTBWP12T30P140, BOUNDARY_RIGHTBWP12T30P140)
7-2 memory

TN28HPCPlus One Port Register File (1) 256 X 4
(2) 1024 X 8
TN28HPCPlus Single Port SRAM
TN28HPCPlus Dual Port SRAM
TS RI D OC UM
EN T E XA M PL E
page 11 / 16
7.3.1 IO library CBTK_TSMC28HPCPlus _io_TSMC_v1.0
7.3.2 power domain PVDD2POC_H_G, PVDD2POC_V_G
PAD
7.3.3 IO filler
7.3.4 bonding pad
7.3.5 IO PADIO fillerbonding pad Layout:
7.3.6 L Corner Tag
7-4 DRC
TN28HPCplu DRC
DRC
7-5 LVS
7.5.3 LVS
7.5.4
8. TSMC 16 nm CMOS LOGIC FinFET Compact(Shrink) LL ELK Cu 1P13M 0.8/1.8V
8-1 Core library
8.1.1 Core library CBTK_TSMC16FFC_core_TSMC_v1.0
8.1.4 core cell SVT LVT ULVT ILVT
8.1.5 core filler
8.1.6 Well Tap Cell (Cell Name: TAPCELLBWP16P90
8.1.7 End Cap Cell (Cell Name: BOUNDARY_PTAPBWP16P90 ,
BOUNDARY_NTAPBWP16P90 )
8-2 memory

TN16FFC Low Leakage One Port Register File (1) 256 X 4
(2) 1024 X 8
TN16 FFC Low Leakage High Density Single Port
TS RI D OC UM
EN T E XA M PL E
page 12 / 16
Single Bank SRAM
Single Port Single Bank SRAM
TN16FFC Low Leakage Smaller High Density
Single Port Multi Bank SRAM
TN16FFC Low Leakage Smaller High Density
Single Port Single Bank SRAM
TN16FFC Low Leakage Single Port SRAM
TN16FFC Low Leakage Ultra High Density One
Port Register File
Port Register File
8.3.1 Core library CBTK_TSMC16FFC_io_TSMC_v1.0
8.3.2 power domain PVDD2POCM PAD
8.3.3 power domain PCBRTE PAD
8.3.4 IO filler
8.3.5 bonding pad
8.3.6 IO PADIO fillerbonding pad Layout:
8.3.7 L Corner Tag
8-4 DRC
TN16FFC DRC

8-5 LVS
8.5.3 LVS
8.5.4
9. UMC 0.18um Mixed-Mode and RFCMOS 1.8V/3.3V 1P6M Metal Metal Capacitor Process
9-1 Core library
9.1.1 Core library CBDK018_UMC_Faraday_v1.0 CBDK_UMC018_ITRI_v0.8

9.1.3 core filler
9-2 memory
TS RI D OC UM
EN T E XA M PL E
page 13 / 16

(2) RAMexample2.spec (RAMexample2.txt)
9.2.1
, ROM )
9-3 IO library
9.3.1 IO library CBDK_UMC18_Faraday CBDK_UMC018_ITRI
9.3.2 IO filler
9.3.3 bonding pad
(C-1 C-2) CBDK_UMC18_Faraday IO library CBDK_UMC018_ITRI IO Library

C-2. Corner Cell R180
9-4 Dummy Pattern
9.4.1 UMC Dummy Pattern Dummy Pattern
Diffusion/Poly/Metal 1~6 Dummy Diffusion/Poly/Metal Density Rules

9.4.2 mixed-signal Full-Custom FlowDummy
Pattern GDS No 70~77 Data Type 1 Dummy Block Layer 8
Dummy Pattern Full-Custom Flow Cell-Based Flow
UMC Diffusion/Poly/Metal Dummy
9-5 DRC
_________________________________________________
9.5.3.1 DRC ________
9.5.3.2
9.5.4 Queue server DRC DRC
http://www2.tsri.org.tw/~shuttle/drc/all/U18.pdf
EN T E XA M PL E
page 14 / 16
ANT.1D.b.ME1
ANT.1D.b.ME3
9.6.2 TSRI blackbox
9.6.4 LVS
9.6.5


10-1 cell name SRAM_2048x16
10-2 DRC
11.
11-2 boundary condition
input drive strength input delay output loading output delay
11-3 timing constraint
specify clock (sequential design)
11-4 report timing violation
setup time violation hold time violation
11-5 verilog assign
11-6 verilog *cell* instance name
12. ()
EN T E XA M PL E
page 15 / 16
12-3 Embedded memory SRAM 1 ROM 1
Memory SRAM : 512 X 8, ROM : 128 X 8
BIST YES or
BIST Test Algorithm March C-
memory BIST controller
BIST controller 2
12-4 Scan Chain Information
12-5 Uncollapsed fault coverage 90% 95.67%
ATPG pattern 348
Synopsys TetraMAX ATPG pattern set faults -fault_coverage
TetraMAX fault coverage information
SynTest TurboScan asicgen ATPG pattern atpg pessimistic fault coverage

13-1 gate level simulation setup timing violation
14.
14-1 P&R IC Compiler Innovus
14-2 power ring 40 m current density
14-3 IO power pad 5 Core power pad 5
14-4 IO ground pad 5 Core ground pad 5
14-5 output loading
14-6 Clock Tree
(C-1) IC Compiler
(S-1 S-2) Innovus
S-1. verify connectivity connectivity
S-2. verify geometry geometry violation
15.
STA(static timing analysis) PrimeTime
15-2 Queue server post-layout transistor level
( CIC ADPLL IP, post-layout transistor level )
15-3 SS TT FF
15-4 CIC 93000
15-5 : 10 pF
16. Andes N1213-30T2G CPU IP
16-1 Andes N1213-30T2G CPU IP
TS RI D OC UM
EN T E XA M PL E
page 16 / 16
SRAM ________

( bug)
17.
17-1 layout Virtuoso Laker layout editor layout
Innovus IC Compiler APR tool layout
17-2 layout IO pad

EN T E XA M PL E

tapeout review form for cell-based ic example

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