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The top documents tagged [gate delay]
PDF Chap 10
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1 Chapter 2 Combinational Logic Circuits Binary Logic and Gates Boolean Algebra Based on Logic and Computer Design Fundamentals, 4 th ed., by Mano and
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High-K Dielectrics: Extending Current Semiconductor Manufacturing Techniques by Alexander Glavtchev
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MonolithIC 3D Inc. Patents Pending 1 THE MONOLITHIC 3D-IC DISRUPTOR A DISRUPTOR TO THE SEMICONDUCTOR INDUSTRY
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A Survey and Comparison of Existing Low Power Ripple-Carry Adders
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MITIGATION OF SOFT ERRORS ON 65NM COMBINATIONAL LOGIC GATES VIA BUFFER GATE
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The wire
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VLSI Made Easy_ VLSI Interview Questions
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EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Sequential Circuits
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Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic
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Simulated Evolution Algorithm for Multi- Objective VLSI Netlist Bi-Partitioning Sadiq M. Sait, Aiman El-Maleh, Raslan Al-Abaji King Fahd University of
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Virtual and Physical Cellular Architectures for Kilo-processor Chip Computers Tamás Roska Hungarian Academy of Sciences and Pázmány P. Catholic University,
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