t r,f =t r.fo +α p,n *c l ru=[k’(w/l)(vdd-vt )]-1 c gu =cox(wl)u
DESCRIPTION
t r,f =t r.fo +α p,n *C L Ru=[k’(W/L)(Vdd-Vt )]-1 C GU =Cox(WL)u C DU =(C GD +C DB )u C SU =(C GS +C SB )u (W/L) m =m(W/L)u R m =Ru /m C (G,D,S)m =mC (G,D,S)u R m C m =RuCu= 常數. t r,f3 =t r,f,o +(1/3) α p,nu C L tr,f--- m 大 , tr,f 變小. - PowerPoint PPT PresentationTRANSCRIPT
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
tr,f=tr.fo+αp,n*CL Ru=[k’(W/L)(Vdd-Vt)]-1 CGU=Cox(WL)u
CDU=(CGD+CDB)u CSU=(CGS+CSB)u (W/L)m=m(W/L)u
Rm=Ru /m C(G,D,S)m=mC(G,D,S)u RmCm=RuCu= 常數
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第 8 章 Designing High-Speed CMOS Logic Networks
tr,f3=tr,f,o+(1/3) αp,nuCL tr,f---m 大 ,tr,f 變小
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
tr=[(N+1)/2]tro+(αpu/m)CL tf=(N+1)tfo+(Nαnu/m)CL
Cin=mCmin tr,f 因 m 大而變小
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
tr=(N+1)tro+(Nαpu/m)CL tf=[(N+1)/2]tfo+(αnu/m)CL Cin=mCmin tr,f 因 m 大而變小
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
td=tnot|m=1+tNAND2|m=2+tNOR2|m=3
=tfo+αnu(2Cmin)+
(3/2)tro+αpu(3Cmin)+
(3/2)tfo+αnu(4Cmin)
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic NetworksWn=Wmin Wp=rWmin
r=Un/Up βn=βp
Cin=(1+r)Cu=Cinv
ts=to+(α/m)CL
td=(A+Bn) τmin
n=CL/Cmin
τmin=Rmin Cmin
,
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic NetworksTime Delay
• td=(A+Bn) τmin : 單一 inv
• td,N=(x1)(N-1) (A+Bn) τmin N: 扇入• EX: x1=1.17 N=1----N=2
• tmd,N=(x1)(N-1) (A+(Bn/m)) τmin m: 縮放比
• tmd,N=x2(x1)(N-1) (A+(Bn/m)) τmin x2: 複雜 N
• EX8.1
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第 8 章 Designing High-Speed CMOS Logic Networks
(W/L)p=r*(W/L)n
r=Un/Up=kn’/kp’>1
Vtn=|Vtp|=Vt
Rn=Rp=R VM=0.5VDD
τ=RCout=R(CFET+CL)
ts=tr=tf
Cin=CGn+CGp
=Cox(AGn+AGp)=
CoxL(Wn+Wp)=(1+r)(CoxLWn)
=(1+r)CGn
8-2 驅動大電容負載
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
CL1=Cin
ts1=to+αCin : 單位負載
降低 ts1 降低 αβ 大
β’= Sβ, R’=R/S
α’=α/S
ts=to+(α/S)CL ts 變小
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic NetworksCL 大
CL=SCin
Wn’=SWn
Cin’=SCin
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
β1<β2<β3……………………..<βN-1<βN
β2=Sβ1 β3=Sβ2 ……… βj+1=Sβj
β3=Sβ2=S2 β1
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第 8 章 Designing High-Speed CMOS Logic Networks
βj=S(j-1)β1
Cj=S(j-1)C1
Rj=Rj/S(j-1)
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第 8 章 Designing High-Speed CMOS Logic Networks
τj=RjCj+1 τd=τ1+τ2+τ3+ …………+τN-1+τN
( 假設 Cj+1>>CFET,j) =R1C2+R2C3+R3C4+……+RN-1CN+RNCL
(CL=CN+1=SNC1) =R1SC1+(R1/S)S2C1+(R1/S2)S3C1+…….
………. +(R1/SN-2)SN-1C1 +(R1/SN-1)SNC1
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第 8 章 Designing High-Speed CMOS Logic Networks
τd
• τd=SR1C1+SR1C1+SR1C1+………SR1C1+SR1C1
• =NSR1C1 (8.71)<---- 有 bug
• =NSτr
• CL=SNC1 ln(SN)=ln(CL/C1)=NlnS
• N= [ln(CL/C1)]/lnS
• τd=τr [ln(CL/C1)][S/lnS]
• …S=e EX8.2 Real Case S>e
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
多 CF,j=SJ-1CF,1
………
τx=R1CF,1
S(lnS-1)=τx/ τr
EX8.3
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
8.3 邏輯效力g=Cin/Cref
gNOT=1
gNand=(2+r)/(1+r)
gNor=(1+2r)/(1+r)
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第 8 章 Designing High-Speed CMOS Logic Networks
h=Cout/Cin
( 電性效力 )
d=h+p
p: 寄生電容延遲
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic NetworksD=d1+d2=(h1+p1)+(h2+p2) ( 反相器 g=
1)
H=h1*h2 D=(h1+p1)+(H/h1+p2)
P8-27;28 公式 (8.122;123;124)
h1=h2, DMin.
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
8.3.2 推廣
Cin=CGn(1+r)
gNAND2=(2+r)/(1+r) ; gNOR2=(1+2r)/(1+r)
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第 8 章 Designing High-Speed CMOS Logic Networks
D=Σdi (8.134 p.8-30)
G=Πgi=g1*g2*g3…..
H=Πhi=h1*h2*h3….
F=GH=f1*f2*f3…..=fN ; F(1/N)=f=gh( 每一級皆相等 Dmin.) D=NF(1/N)+P (8.137-142)
=500fF=20fF
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第 8 章 Designing High-Speed CMOS Logic Networks
範例 8.4• G=gNOTgNOR2gnand2= 1*[(1+2r)/(1+r)][(2+r)/(1+
r)]
= 1(6/3.5)(4.5/3.5)=2.2 (r=2.5)• H=C4/C1=500/20=25• F=GH=55 f=F(1/N)=55(1/3)=3.8• D=3(3.8)+P=11.4+P• P=pNOT+pNOR2+pNAND2
• h3=f/g3=3.8/1.29=2.95=C4/C3; C3=500/2.95= 169.5fF=S3CGn(2+r)=S3(4.5CGn); S3: 縮放因數
• h2=3.8/g2=3/8/1.71=2.22=C3/C2
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第 8 章 Designing High-Speed CMOS Logic Networks
C2=169.5/2.22=76.35fF=S2CGn(1+2r)
=S2CGn(1+2r)=S2(6CGn)
h1=3.8/1=C2/C1; C1=76.35/3.8=20fF
CGn=20/3.5=5.71fF
S2=76.35/(6*CGn)=2.23 (Bug?) (8.159)
S3=169.5/(4.5*CGn)=6.60 (Bug?) (8.159)
( 另外假設 Cref=8fF 即 Cgn=8/3.5fF=2.2857fF)
P.8-33 最下面一行 S2=1.59*3.5=5.565 (Bug?)
S3=4.71*3.5=16.485 (Bug?)
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks範例 8.5
• F=200
• N=3 NF(1/N)=3*(200)(1/3)=17.54
• N=4 NF(1/N)=4*(200)(1/4)=15.04
• N=5 NF(1/N)=5*(200)(1/5)=14.43
• N=10 NF(1/N)= 10*(200)(1/10)=16.99
• N=5 Optimum Value
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第 8 章 Designing High-Speed CMOS Logic Networks
8.3.5 分枝
B=Πbi
b=CTotal/Cpath
Example 8.6
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第 8 章 Designing High-Speed CMOS Logic Networks8.4 BiCMOS 驅動器
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第 8 章 Designing High-Speed CMOS Logic Networks
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第 8 章 Designing High-Speed CMOS Logic Networks
Ic I≒ Se(VBE/Vth) Vth=kT/q=26mV 27 =300 ℃ 0K
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第 8 章 Designing High-Speed CMOS Logic Networks
Ic=αIE
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第 8 章 Designing High-Speed CMOS Logic Networks
XB<= 電子游離半徑
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第 8 章 Designing High-Speed CMOS Logic Networks
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Introduction to VLSI Circuits and Systems
第 8 章 Designing High-Speed CMOS Logic Networks
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第 8 章 Designing High-Speed CMOS Logic Networks
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第 8 章 Designing High-Speed CMOS Logic Networks
0,Vdd
Vdd,0
0 Vdd
OFF
SAT
SAT
OFF
Vdd
0
H L
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第 8 章 Designing High-Speed CMOS Logic Networks
VOH=VDD-VBE,SAT VOL=VBE,SAT=0.8 V EX8.7
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第 8 章 Designing High-Speed CMOS Logic NetworksCL>Cx BiCMOS 有優勢
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第 8 章 Designing High-Speed CMOS Logic Networks
Exercise• 習題… ..1,2-9• 題目 8.3 中第一行” 1 被切換至一個 0” 改成”
0 被切換至一個 1” ( 解答有 bug?)• td=tfo+αnu(Cmin)+3tro+2αpu(4Cmin) +3tfo+
(2/2)αnu(3Cmin)+tro+(α/3)pu(10cmin)=4tfo+4tro+4αnu(Cmin)+(34/3) αpu(Cmin) [ 紅色解答有 bug?]
• 習題 8.4 第一行加 Wn=2.2μm• 習題 8.6 第一行 c’=0.86 改成 8.6pF/cm• 習題 8.9 解答有問題把 b 改成• b=(2+r+3+r)/(2+r)=2.22