T. Hemperek

VERIFICATION OF COMPLEX MIXED SIGNAL ASICS

System-Verilog and UVM mini workshop 14 t h November 2013

Moore's law in HEP

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Name D-OMEGA Ion LHC1 FE-I3 FE-I4 FE-I5

Year 1991 ~1996 ~2005 ~2011 ???

Technology Node 3 µm 1µ 0.25 µm 0.13 µm 65 nm??

Chip size 8.3x6.6 mm2 8x6.35 mm2 10.8x7.6 mm2 10.2x19 mm2 ???

Pixel size 75x500 µm2 50x500 µm2 50x400 µm2 50x250 µm2 25x125 µm2 ??

Pixel array 16x63 16x127 18x160 80x336 ???

Transistor count ??? 800k 3.5M 80M 1G?

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Switch to big “D”, little “A”

Same pattern for HEP

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Verification

• Verification plan

• Simulation

• Assertion based verification

• Formal verification

• Mixed signal verification

• FE-I4

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Verification Plan

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Simulation – Unified Verification Methodology

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Assertions based verificationA pattern describes a proven solution to a recurring design problem

// A start can only occur after a grant for an active requestassert

property (@(posedge clk) disable iff (~rst_n)req[*1:8] ##0 grant ##1 req |-> start);

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Formal verification

// SystemVerilog Assertion

property p_arb; @(posedge clk) req |=> ##[0:2] gnt;endpropertyassert property (p_arb);

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Static verification checking and simulation

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Metric Driven Verification

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MS Verification

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Accuracy versus performance

Source: Cadence Design Systems

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Modeling feature chart

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FE-I4 Top View

ANALOGARRAY

(digital part)

DIGITALARRAY

END OF COLUMN

END OF CHIP

COMMAND DECODER

REGISTER MEMORY

PLL

PLL

DATA OUTPUT

- verilog model

- Implementation (rtl/gate)

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FE-I4 Verification environment

For FE-I4 we heve 4 OVC:

- PIX

- CMD

- REVEIVE

- MANUAL

FE-I4

DETECTOR(PIX)

OUTPUT(RECIVE)

MANUAL

SLOW COMAND

(CMD)

Questions?

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UVM register model

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System Verilog

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A UVM layer for PyHVL

http://www.fivecomputers.com/a-uvm-layer-for-pyhvl.html