Tutorial

Reduced Pin Count Test for

Test Cost Reduction

Beom Ik Cheon System LSI Division

Samsung Electronics Co., Ltd.

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Mobile with SOC

Image Processing

Computing

Communication

Broadcasting

Telematics

Entertainment

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Semiconductor in Mobile

Processor: AP - MC

Modem: GSM/GPRS - WCDMA - CDMA2000

Connectivity: Wireless LAN - GPS - Bluetooth

RF/Analog: Rx - Tx - Zero IF - PM

Camera Chipset: CIS - CCD - ISP

Display Driver IC (DDI): STN - TFT - OLED

Smart Card: SIM

Flash Memory: Code/Data Storage

SIP / MCP / TSV

RAM: Mobile DRAM - SRAM - UtRAM

[ DATE 2005 ]

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Test for SOC

[ DATE, 2005] [http://www.samsung.com/sec/]

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Example of SOC

Design Guide: Intel® PXA250 and PXA210 Applications Processors, 2002

[TOSHIBA mobile application processor for multimedia mobile applications] Development of Low Power and High Performance Application Processor (T6G) for

Multimedia Mobile Applications [ASPDAC2011]

[The Test Features of the Quad-Core AMD Opteron™ Microprocessor, Tendolkar, ITC, 2008 ]

L2 CORE

DD

R I

nte

rfac

e

CORE

CORE CORE L2

L2

L2

SC

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Technology Trend and Test Cost

Test Cost Trend

[ ITRS Roadmap ]

SOC Design Trend

Transistor production cost reduction exponentially Test cost does not change Test cost can be higher than production cost in future

Size of SOC devices increases about double every year Rapid increase of silicon size makes test cost higher Complex DFT methodology for high performance Higher test time drive us large ATE investment

2006 2007 2008 2009 2010 2011

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Test Methodology for SOC

DRAM Testing

Test strategy for SiP

Memory Testing

Logic Testing

Pad Testing

Analog Testing

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Test Cost for SOC

Test Cost Constraints

Test Time, Test Pin, ATE Investment Target

Test Time Reduction Test Pin Reduction

Methodologies Digital Logic

Scan Design with Scan Compression ATPG Logic BIST IO test

Memories Memory BIST for SRAM and DRAM

Analog Circuit ADC, DAC, CODEC, PLL, Etc.

Reduced Pin Count Test (RPCT) Multi-Site Testing with RPCT

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SOC with Large Test Cost

Test Cost Test Time

clock speed gate count # of scan FF # of memories

2006 2007 2008 2009 2010 2011

SOC Design Trend

RTL Design

Synthesis

Netlist

Scan Design

Placement

Routing

Timing Closure

Power Design

ATPG

Silicon

Silicon-Test

Memory BIST/BIRA

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Test Methodology for Digital Logic

Combinational Logic T1

Combinational Logic T2

Combinational Logic T3

Pattern Size Faul

t Co

vera

ge

Functional Test Vector ATPG for Sequential Circuit

Automatic Test Pattern Generation (ATPG) ATPG with Fault Models

FF

Clock

FF

Clock

Combinational Logic

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Test Methodology for Digital Logic

Scan Design ATPG for Combinational Circuit

FF

Clock

FF

Clock

Combinational Logic

0 1

Mode Clock

0 1

Mode Clock

FF FF

Combinational Logic

Clock Clock

FF FF

Combinational Logic

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Scan Design & ATPG

12

# of patterns # of FF Clock speed # of scan Chain Test Time

1 4 0.1 µsec (10MHz) 1 0.4 µsec

1000 4 0.1 µsec (10MHz) 1 0.4 msec

1000 400 K 0.1 µsec (10MHz) 1 40 sec

Mode

0 1

Clock

Mode

0 1

Clock

0 1

Clock

0 1

Clock

1 1 1 0

FF FF FF FF

1 1 1 0

1

0

0 Combinational

Logic

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Scan Design and Test Time

13

# of patterns # of FF Clock speed # of scan Chain Test Time

1000 400 K 0.1 µsec (10MHz) 1 40 sec

1000 40 K 0.1 µsec (10MHz) 10 4 sec

1000 40 0.1 µsec (10MHz) 10 K 4 msec

# of FF (per Scan Channel)

FF FF FF FF FF FF FF FF FF FF FF FF

Combinational Logic

# of FF (per Scan Channel)

# of Scan Channel

Combinational Logic

FF FF FF FF FF FF FF FF

FF FF FF FF FF FF FF FF

FF FF FF FF FF FF FF FF

FF FF FF FF FF FF FF FF

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Pin Reduction with Logic BIST

Pin Reduction with Logic BIST (Built-In Self-Test) Strong and Weak Points:

SFF SFF SFF SFF SFF SFF SFF SFF

SFF SFF SFF SFF SFF SFF SFF SFF

SFF SFF SFF SFF SFF SFF SFF SFF

Combinational Logic

Test

Pat

tern

Gen

erat

or

(PR

PG)

MIS

R

BIST Controller with JTAG

TDO TDI TMS TCK

TRST BIST-Mode

PLL Clocks

MS

BIST Mode

BIST Finished

BIST_Pass_Fail BIST Operation

BCLK

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PRPG with Logic BIST

Pseudo Random Pattern Generator LFSR (Linear Feedback Shift Register) & XORs

Very Low Fault Coverage with PRPG PRPG + Phase Shifter Test Point Insertion Top-Up ATPG

ATPG

# of Test Pattern

Fault Coverage

PRPG PRPG &

Phase Shifter PRPG & Phase Shifter & Test Point Insertion

Top-Up ATPG

PRPG with Characteristic Polynomial F(x) = 1 + h1X + h2X2 + h3X3 + ……. + hn-1Xn-1 + Xn

FF FF FF FF FF

h1 h2 hn-2 hn-1

[Digital System Testing and Testable Design, ISBN 0-7803-1062-4]

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Phase Shifter with Logic BIST

Automated Synthesis of Phase Shifters for Built-In Self-Test Applications [IEEE Trans. CAD 2000]

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MISR with Logic BIST

Time Compaction MISR with Characteristic Polynomial F(x) = 1 + h1X + h2X2 + h3X3 + ……. + hn-1Xn-1 + Xn

M0

FF FF FF FF FF

M1 M2 Mn-2 Mn-1

h1 h2 Hn-2 Hn-1

Sca

n C

hai

n

Sca

n C

hai

n

Sca

n C

hai

n

Sca

n C

hai

n

Sca

n C

hai

n

PRPG with Phase Shifter

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Clock Scheme for Logic BIST

Shift

Capture Shift

CLK1

CLK2

CLK3

Capture

Shift Shift

Shift Shift

Shift Shift

M I S R (1)

P R P G (1)

Combinational Logic

M I S R (3)

P R P G (3)

Combinational Logic

M I S R (2)

P R P G (2)

Combinational Logic

Combinational Logic

CLK1

CLK2

CLK3

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Pin Reduction with Scan Compression

Pin Reduction with Scan Compression Feature Max. 100X Compression Ratio

Strong and Weak Points:

SFF SFF SFF SFF SFF SFF

SFF SFF SFF SFF SFF SFF

SFF SFF SFF SFF SFF SFF

Combinational Logic

Dec

ompr

esso

r

Dec

ompr

esso

r

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Illinois Scan for Scan Compression

[ISVLSI’04 Enhancement of the Illinois Scan Architecture for Use with Multiple Scan Inputs]

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Scan Compression [Synopsys]

[DATE09 Scalable Adaptive Scan (SAS)]

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Scan Compression [Mentor Graphics]

[ ITC 2002, Embedded Deterministic Test for Low Cost Manufacturing Test ]

[USA patent, Serial No. 6,353,842, March 5, 2002]

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Scan Compression [Cadence]

[2002, IEEE Design & Test of Computers]

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Scan Compression for SOC

Scan Compression for Flatten Design

Scan Chain 1

Scan Chain 2

Scan Chain N

Compressor Compressor

Decompressor Decompressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Digital Logic

Core 1 Core k Core N

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Scan Compression for SOC

Scan Compression for Hierarchical Design

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core 1

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core k

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core N

Digital Logic

SC

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Test Pin Reduction with Serializer

Scan Compression with Serializer Deserializer : Serial-Input and Parallel-Output Serializer : Parallel-Input and Serial-Output

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core 1

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core k

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core N

Digital Logic

[DATE09 Scalable Adaptive Scan (SAS)]

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Scan Compression for SOC

Scan Compression with Shared Scan-Input/Output

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core 1

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core k

Decompressor

Compressor

Scan Chain 1

Scan Chain 2

Scan Chain N

Digital Logic

Core N

Digital Logic

[Synopsys DFTMAX User Guide]

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Test Pin Reduction with Scan Compression

Scan Chain 1

Scan Chain 2

Scan Chain N

SI[1]

SI[n]

SI[2]

SO[1]

SO[n]

SO[2]

Digital Logic

IN[1]

IN[k]

IN[2]

OUT[1]

OUT[k]

OUT[2]

[ N << n ]

(N+k)*2 (n+k)*2

Scan Chain 1

Scan Chain 2

Scan Chain N

SI[1]

SI[N]

SI[2]

SO[1]

SO[N]

SO[2]

Digital Logic

IN[1]

IN[k]

IN[2]

OUT[1]

OUT[k]

OUT[2]

Com

pres

sor

Dec

ompr

esso

r

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Test Pin Reduction with Scan Compression

(n)*2 (n)*2

SI[1]

SI[n]

SI[2]

IN[1]

IN[k]

Scan Chain 1

Scan Chain 2

Scan Chain N

SO[1]

SO[n]

SO[2]

Digital Logic

0 1

FF

FF

0 1

FF

FF

OUT[1]

OUT[k]

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

Digital Logic

Scan Chain 1

Scan Chain 2

Scan Chain N

SI[1]

SI[n]

SI[2]

SO[1]

SO[n]

SO[2]

IN[1]

IN[k]

OUT[1]

OUT[k]

TAP TDO TDI

[ ATS 2005, “Achieving High Test Quality with Reduced Pin Count Testing” ]

Dec

ompr

esso

r

Com

pres

sor

Dec

ompr

esso

r

Com

pres

sor

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Scan Compression vs. Logic BIST

Comparison with Logic BIST and Scan Compression

Strong and Weak Points:

Issues Scan

Compression Logic BIST

Fault Models

Fault Coverage

Design Rule

Seamless Design Flow

Design TAT

Verification

Timing Closure

Silicon Diagnosis

Production Yield

High Power Consumption

Test Quality

Test Time

Area Overhead

Reduced Pin Count Test

Test at System Level

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Memory Testing

Memory BIST for Memory Testing

SOC SR

AM

SR

AM

Function

Function

SRAM

Function

0 1

1 0 SR

AM

Function

SOC

0 1

1 0

BIST_Mode

SRAM

Address Decoder Module

BIST

Data Generator

Address Generator

Comparator

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Memory BIST for SOC

Top Controller with JTAG for Memory BISTs

2006 2007 2008 2009 2010 2011

Test Time M1 M2 M3 M4 M5 Mk

Mk

M5

M4

M3

M2

M1

Mk

M2

M1

P Top

CNTR_1

Memory Memory Memory Memory

Memory Memory Memory Memory BIRA BIRA BIRA

BIRA BIRA BIST

Memory Memory Memory Memory

Memory Memory Memory Memory BIRA BIRA BIRA

BIRA BIRA BIST

PLL PLL PLL

SOC Device

JTAG

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IEEE1500 for SOC Testing

IEEE 1500 Motivation A flexible DFT strategy for SOC designers

Flexible test methodology for embedded cores Test reuse for DFT design and test pattern of a core

Feature A serial interface A parallel interface

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IO Testing with JTAG

IO Testing with JTAG Stuck-fault Leakage current (IIL, IIH, IOZ),

Digital Logic

Scan Chain 1

Scan Chain 2

Scan Chain N

TDI TDO

TAP

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

BSC

VEn

BSC

BSC

BSC

[ ITC2002, Complete, Contactless 110 Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost ]

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SiP/MCM Testing

Test methodology in SiP & MCM Test time reduction

Test pin reduction

Test strategy

for SiP

DRAM Testing

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DUT-1

DUT-2

DUT-n

[ (A + b) / n ] (B > b)

A

T E

Multi-Site Testing with RPCT

A

T E

DUT-1

DUT-2

DUT-n

MS

Test Mode

Test Finished

Test_Pass_Fail Test Operation

CLK

A

T E

DUT-1

DUT-2

DUT-n

[ A/n + B ] [ A + B ]

MIS

R

MIS

R

MIS

R

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Massively Parallel Test with RPCT

[ ICCD 2009, Framework for Massively Parallel Testing at Wafer and Package Test ]

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Summary

Test Time Reduction High Testability Scan Design Scan Compression Logic BIST Memory BIST Concurrent Testing

Multi-Site Testing with RPCT Massively Parallel Test Advanced Methods

Issues ATE Limitation Analog Test Etc.