synchronous network
DESCRIPTION
Synchronous NetworkTRANSCRIPT
UNIT- III Synchronous Sequential Networks
Sequential Network Model
Sequential Logic Networks
• Combinational logic networks Outputs at any given time depends only on the
input at that time
Each output is represented by an algebraic function of the inputs
• Sequential logic networks Outputs depend on past and present inputs Past inputs must be stored – memory! Synchronous sequential network
behavior determined by values of the signal at discrete instants of time (clock)
Asynchronous sequential networks behavior immediately affected by the inputs changes
Clocked Synchronous Sequential Network
Mealy Model
Mealy model of a clocked synchronous sequential network.Figure 7.3
Outputs are only a function of the external inputs and the present state
Z = g(X,Q)
Moore Model
Moore model of a clocked synchronous sequential network.Figure 7.4
Outputs are only a function of the present state
Z = g(Q)
Analysis of Clocked Synchronous Sequential Networks
• Logic Diagram• Excitation and Output Expressions• Transition Equations• Transition Tables• Excitation Tables• State Tables• State Diagrams
Logic diagram for Example 7.1
Excitation and Output Expressions
• From example 7.1
D1 xQ2 Q1Q2
D2 xQ1 Q1Q2
zxQ1 xQ1Q2
• From example
Q1 xQ2 Q1Q2
Q2 xQ1 Q1Q2
Transition Equations
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)
0 1 0 1
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
1
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
10
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
10111000
01110000
0011
1000
Excitation Table
Present state(Q1Q2)
Excitation(D1D2)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
Excitation Table
Present state(Q1Q2)
Excitation(D1D2)
Output(z)
Input (x) Input (x)0 1 0 1
00011011
10111000
01110000
0011
1000
State Table
Present state Next state Output (z)
Input (x) Input (x)0 1 0 1
00A01B10C11D
State Table
Present state Next state Output (z)
Input (x) Input (x)0 1 0 1
00A01B10C11D
C
State Table
Present state Next state Output (z)
Input (x) Input (x)0 1 0 1
00A01B10C11D
CDCA
BDAA
0011
1000
State Table
Present state Next state, Output (z)
Input (x)0 1
ABCD
State Table
Present state Next state, Output (z)
Input (x)0 1
ABCD
C,0
State Table
Present state Next state, Output (z)
Input (x)0 1
ABCD
C,0D,0C,1A,1
B,1D,0A,0A,0
Example 7.1
State diagram
Logic diagram for Moore Network
Excitation and Output Expressions
• From example
J1 y
K1 y xQ2
J2 xQ1 xyQ1
K2 xy yQ1
z1 Q1Q2
z2 Q1 Q2
From example
Q1 yQ1 x yQ1 yQ1Q2
Transition Equations
Q2 xQ1Q2 xyQ1Q2 xyQ2 xQ1Q2 yQ1Q2
Transition Table
Present state(Q1Q2)
Next state(Q1
+Q2+)
Output(z1z2)
Input (xy)00 01 10 11
00011011
00011011
10110100
01000010
11110000
01001101
Excitation Table
Present state(Q1Q2)
Excitation(J1K1,J2K2)
Output
(z1z2)
Input (xy)00 01 10 11
00011011
00,0000,0000,0000,00
11,0011,0011,1111,11
01,1100,1101,0100,01
11,1011,1011,0111,01
01001101
State Table
Present state
Next state Output
(z1z2)
Input (xy)00 01 10 11
00A01B10C11D
ABCD
CDBA
BAAC
DDAA
01001101
State diagram
The serial binary adder
Figure 7.11
The serial binary adder
State A – no carry was generated from the previous order addition.State B – carry was generated from the previous order addition.
State diagram for a Mealy serial binary adder
(a) Partial state diagram
State diagram for a Mealy serial binary adder
(b) Completed state diagram
A sequence recognizer
Figure 7.14
A sequence recognizer
An output 1 is produced if the three input symbols following two consecutive input 0’s consist of aleast one 1
x = 0100010010010010000000011
A sequence recognizer
x = 01 00010 01 00100 1 00000 00011
z = 00 00001 00 00001 0 00000 00001
State diagram for a sequence recognizer