syam kumar pidaparthy, member, ieee ieee...

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1

Stabilizing Effects of Load Subsystem in MultistageDC-to-DC Power Conversion SystemsSyam Kumar Pidaparthy, Student Member, IEEE, Byungcho Choi, Member, IEEE,

Hansang Kim, and Yeonjung Kim

Abstract— This paper investigates the impacts of the load1

subsystem on stability and performance of the upstream con-2

verter in multistage dc-to-dc power conversion systems. This3

paper demonstrates that an appropriate load subsystem can be4

constructed to provide both stability and intended performance5

for the upstream converter at the brink of instability before being6

coupled with the load subsystem. These stabilizing effects of the7

load subsystem are theoretically analyzed and experimentally8

validated using a two-stage power conversion system, consisting9

of an upstream boost converter, downstream buck converter, and10

two filter stages. This paper also presents the design procedures11

for the stabilizing load subsystem, along with the performance12

verification of the upstream boost converter and the downstream13

buck converter.14

Index Terms— DC-to-DC power conversion systems, dynamic15

interaction, load subsystem design, loading effects, minor loop16

gain, stability and performance.17

I. INTRODUCTION18

DC-TO-DC power conversion systems employ several cas-19

caded stages of converters and filters to achieve efficient20

and reliable power conversion [1]. Fig. 1 shows the structure21

of a two-stage power conversion system, where a front-end22

converter with an input filter is connected to the load converter23

via an intermediate line filter stage. The combination of24

the line filter and load converter is considered as the load25

subsystem for the front-end converter.26

As addressed in previous publications [2]–[11], the27

front-end converter in Fig. 1 is exposed to potential insta-28

bility due to detrimental interactions among the cascaded29

dc-to-dc converters and filter stages. Advanced techniques30

have been proposed to alleviate or eliminate the stability31

problem, such as active damping schemes [3]–[5], feedforward32

controls [6], [7], controller tunings [8], and virtual impedance33

implementations [9]–[11]. These techniques attempted to avoid34

instability using an extra feedback controller or sophisticated35

control circuit. This paper presents a new method to secure36

stability of the front-end converter by employing the load37

Manuscript received January10, 2017; revised March 12, 2017 andApril 22, 2017; accepted May 6, 2017. This work was supported by BasicScience Research Program through the National Research Foundationof Korea funded by the Ministry of Education under GrantNRF-2016R1D1A1B03931966. Recommended for publication by AssociateEditor Marta Molinas. (Corresponding author: Byungcho Choi.)

The authors are with the School of Electronics Engineering, KyungpookNational University, Daegu 41566, South Korea (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JESTPE.2017.2707093

Fig. 1. Two-stage DC-to-DC power conversion system. Functional blockFv (s) represents the feedback compensation of the front-end converter. Loadconverter is also closed-loop controlled.

subsystem itself as a stabilizer. The proposed scheme is imple- 38

mented by redesigning the pre-existing line filter in the load 39

subsystem without any additional feedback controller or con- 40

trol circuit. This method is an application of the impedance- 41

based frequency-domain approach, which has been widely 42

used for dc-to-dc power conversion systems [2]–[11] and are 43

now emerging for stability analysis and control of ac power 44

electronics systems [12], [13]. 45

The front-end converter is designed and fabricated without 46

any prior information about the load subsystem [14]. When 47

combined with the load subsystem, the front-end converter 48

is exposed to the dynamic interaction originating from the 49

load subsystem. The consequential effects of this interaction 50

have been studied in previous publications [15]–[17]. The 51

prior publications mainly addressed the detrimental effects 52

of the load subsystem, implicitly presuming that the front- 53

end converter is subject to the performance degradation when 54

combined with the load subsystem [16], [18]. 55

This paper will demonstrate that, on the contrary to general 56

perception, an appropriate load subsystem can be constructed 57

to stabilize a nearly unstable front-end converter. It will be 58

shown that the front-end converter, on the verge of instability, 59

could secure stable operation and intended performance with 60

aid of an appropriately engineered stabilizing load subsys- 61

tem [19]. This paper analyzes and validates the stabilizing 62

effects of the load subsystem using a two-stage dc-to-dc power 63

conversion system. This paper presents the design procedures 64

for the stabilizing load subsystem, which provides a desired 65

phase margin and a specified transient response for the front- 66

end converter. This paper also investigates the dynamics and 67

performance of the downstream load converter in the stabi- 68

lizing load subsystem. Although a specific two-stage power 69

conversion system is considered, the results of this paper can 70

be extended to general multistage dc-to-dc power conversion 71

systems. Potential applications of the outcomes of this paper 72

would include the following. 73

2168-6777 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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2 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS

Fig. 2. Two-stage power conversion system consisting of front-end boost converter and load subsystem. Peak current mode control is employed to thefront-end boost converter. Current sensing network (CSN) with the dc gain of Ri = 0.5, Se = 5.68 × 104 V/s is the slope of the compensation ramp, PMW,and Fv (s) = 4.8 × 103(1 + s/2π · 258)/(s(1 + s/2π · 9.135 × 103)) is the voltage feedback compensation.

1) The implementation of a reliable dc-to-dc power con-74

version system which maintains the desired stability75

margin and transient performance, regardless of consid-76

erable drifts in the small-signal dynamics of upstream77

converters.78

2) The stabilization or performance enhancement of79

upstream converters which were initially well designed80

but later became destabilized or unsatisfactory, due to81

the detrimental interaction coming from unknown source82

subsystems.83

3) the establishment of general design guidelines for mul-84

tistage dc-to-dc power conversion systems with pre-85

dictable and programmable performance metrics.86

II. TWO-STAGE DC-TO-DC POWER CONVERSION SYSTEM87

Fig. 2 shows the two-stage power conversion system,88

consisting of two closed-loop controlled converters and two89

filter stages. A peak current-mode controlled boost converter90

with an input filter is employed as the front-end converter.91

The parameters for peak current mode control are shown92

in Fig. 2, along with the circuit components of the con-93

verter. The front-end boost converter is connected to the94

load subsystem, composed of an intermediate line filter and95

buck converter. The buck converter employs voltage mode96

control. The parameters of the buck converter will be given97

later in Fig. 5. Both the front-end converter and load sub-98

system are individually designed and later integrated together99

to form the complete two-stage dc-to-dc power conversion100

system.101

A. Front-End Boost Converter With Input Filter102

The front-end boost converter is designed and tested using103

a current sink load. The boost converter is duly designed104

based on the standard procedure [14]. However, the input105

filter parameters are deliberately selected to place the converter106

at the threshold of instability [20], in order to highlight107

the stabilizing effects of the load subsystem using a simple108

dc power conversion system.109

While the purpose of selecting the specific filter parame- 110

ters is to demonstrate the stabilizing effects using a simple 111

example, as practiced in earlier publications [5], [9], [21], 112

there are certain operational instances which resemble the 113

presentation of this paper. Such instance is illustrated in Fig. 3. 114

Fig. 3(a) is the block diagram of the front-end converter cou- 115

pled with a source converter through a filter stage. A current- 116

mode controlled buck converter is employed as the source 117

converter. The output impedance of the source converter, |Zo|, 118

the source impedance, |Zs |, and input impedance, |ZiC |, of the 119

front-end converter are evaluated for two different cases. 120

Fig. 3(b) shows the impedances when the source converter 121

is in regulation mode. A sufficient gap exists between |Zs | 122

and |ZiC |. Fig. 3(c) is the case when the source converter 123

enters a duty-ratio limited operation. Although the source 124

converter is still stable, the converter now presents a large 125

output impedance |Zo|. As will be shown in Section V, 126

the increased |Zo| induces a peak in |Zs|, thus shrink- 127

ing the distance to |ZiC |. This situation yields the case 128

of the front-end converter. Additional discussions about the 129

impacts of an unregulated converter operation can be found 130

in [9]. 131

For another instance, a properly designed input filter could 132

encounter the operational environment of improper input 133

filters. At a rated load current, |ZiC | and |ZoF | secure a 134

sufficient magnitude gap. When the load current is increased, 135

the gap diminishes and the converter becomes less stable. 136

This could eventually destabilize an originally stable front- 137

end converter. The converter stability under influences of load 138

current changes was also addressed in [9] and [21]. 139

In addition, the use of electrolytic capacitors and resistive 140

damping is often prohibited in space/marine power systems 141

and military applications [22]–[25]. In such cases, the selection 142

of the input filter components would be similar to that of the 143

front-end converter. 144

Fig. 4(a) is the functional block diagram of the boost 145

converter connected to the current sink. The performance of 146

the boost converter is shown in Fig. 4(b)–(e). Fig. 4(b) (top) 147

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PIDAPARTHY et al.: STABILIZING EFFECTS OF LOAD SUBSYSTEM IN MULTISTAGE DC-TO-DC POWER CONVERSION SYSTEMS 3

Fig. 3. Front-end converter coupled with source converter through filter stage. (a) Block diagram. (b) Impedance comparison with regulated source converter.(c) Impedance comparison with duty-ratio limited source converter.

is the comparison between the output impedance of the input148

filter, |ZoF |, and input impedance of the boost converter, |ZiC |.149

The predictions of the small-signal analysis in Fig. 4, as well as150

other forthcoming Bode plots, are shown in comparison with151

the experimental data. The small-signal predictions are made152

from computer simulations using small-signal models of pulse153

width modulation (PWM) converters [26], [27]. The experi-154

mental data are obtained with an impedance analyzer using155

the measurement techniques reported in [28]. The magnitude156

comparison reveals that |ZoF | nearly touches |ZiC |. This is157

an indication of the severe destructive interaction between158

the input filter and boost converter, which jeopardizes the159

converter operation [20]. Fig. 4(b) (bottom) is the polar plot of160

the impedance ratio ZoF/ZiC , referred to as the minor loop161

gain [29]. The polar plot resides inside the unit circle, but162

it closely approaches the (−1, 0) point. The nearness to the163

(−1, 0) point indicates the marginal stability and also signifies164

the presence of underdamped complex poles in the closed-loop165

transfer functions of the boost converter [26].166

The loop gain, TmC in Fig. 4(c), confirms that the converter167

is almost unstable with a marginal phase margin. The output168

impedance of the converter, |ZoC | in Fig. 4(d), exhibits a169

large peaking due to the small-phase margin. The instability170

is apparent in Fig. 4(e), which exhibits the output voltage of171

the boost converter, in response to the 1-A step changes in the172

sink current, IO .173

When the sink current is IO = 2 A, the converter exhibits174

a sustained oscillation due to the |ZoF | nearly touching |ZiC |.175

As IO is stepped down to 1 A, |ZiC | increases by 6 dB176

at low frequencies because the low-frequency asymptote of177

|ZiC | is inversely proportional to IO . Thus, an adequate gap178

is created between |ZoF | and |ZiC |. The converter now exits179

from instability and the oscillation soon ceases. When IO is180

again stepped up to 2 A, the oscillation resumes as shown181

in Fig. 4(e).182

III. CONVENTIONAL LOAD SUBSYSTEM AND 183

FRONT-END CONVERTER PERFORMANCE 184

The nearly unstable front-end converter will be stabilized 185

when coupled with a specially designed stabilizing load sub- 186

system. Before discussing the stabilizing load subsystem, this 187

section first presents the performance of the converter com- 188

bined with a nonstabilizing load subsystem, which does not 189

offer the stabilizing effects. The nonstabilizing load subsystem 190

is designed following the conventional approach, commonly 191

accepted as a standard design method [29]. The nonstabilizing 192

load subsystem will be referred to as the conventional load 193

subsystem. 194

Fig. 5(a) is a simplified circuit block diagram of the con- 195

ventional load subsystem, consisting of the voltage source, 196

filter stage, and buck converter. The input impedance of 197

the load subsystem, denoted as the load impedance Z L , is 198

the most important parameter to investigate the influences 199

of the load subsystem [15]. Fig. 5(b) displays the load 200

impedance |Z L |, together with the input impedance of the 201

downstream buck converter, denoted as |Z ′iC |, and an open- 202

circuit input impedance of the line filter, labeled as |Zi F |. 203

As discussed in [15], |Z L | initially follows |Z ′iC | at low 204

frequencies, but it tracks |Zi F | at mid and high frequencies. 205

Thus, |Zi F | of the line filter determines the load impedance 206

|Z L | for the frequencies of practical importance. 207

The influence of the load subsystem can be judged by com- 208

paring |Z L | and the magnitude of the output impedance of the 209

front-end converter, |ZoC | defined in Fig. 4(a). If the condition 210

|ZoC | � |Z L | is met for all frequencies, the load subsystem 211

has only negligible effects on the front-end converter. Con- 212

ventionally, the line filter components are selected for a larger 213

|Zi F | so that |Z L | stays well above |ZoC | for all frequencies. 214

Fig. 5(c) shows |ZoC | and |Z L | of the conventional load 215

subsystem whose line filter parameters are selected for a large 216

|Z L |: L f = 168 μH, Rl f = 0.06 �, C f = 16.8 μF, and 217

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Fig. 4. Front-end converter connected to current sink load. (a) Block diagram. (b) Impedances and minor loop gain. (c) Loop gain of converter. (d) Outputimpedance of converter. (e) Step load response.

Rd = 3.1 �. However, this design will be inappropriate for218

the front-end converter, which is initially unstable. The front-219

end converter will remain unstable after integration, because220

the load subsystem will not exert any appreciable influences,221

due to the sizable gap between |Z L | and |ZoC |.222

Fig. 6 illustrates the performance of the front-end converter223

combined with the conventional load subsystem. The loop224

gain in Fig. 6(a) does not show any noticeable changes from225

the current sink case, thus predicting instability. Fig. 6(b)226

depicts the step load response of the output voltage of the227

front-end converter. For this experiment, 3.1-A step changes228

are introduced to the load current of the downstream buck 229

converter. The 3.1-A change is equivalent to the 1-A change to 230

the current sink, directly connected to the front-end converter. 231

The output voltage does not show any meaningful changes 232

from Fig. 4(e). 233

IV. STABILIZING LOAD SUBSYSTEM AND FONT-END 234

CONVERTER PERFORMANCE 235

The front-end converter remained unstable when combined 236

with the conventional load subsystem. This section discusses 237

the stability and the performance of the converter connected to 238

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Fig. 5. Conventional load subsystem. (a) Circuit diagram. Voltage mode control is employed to the load converter. The slope of the PWM ramp isSe = 1.8×105 V/s and the voltage feedback compensation is Fv (s) = 2.13×103(1+s/2π ·526)(1+s/2π ·1×103)/(s(1+s/2π ·1.9×104)(1+s/2π ·3×104)).(b) Load impedance |ZL |, input impedance of buck converter |Z ′

iC |, and input impedance of line filter |Zi F |. (c) Output impedance of front-end converter |ZoC |and load impedance |ZL |.

Fig. 6. Performance of the converter with conventional load subsystem.(a) Loop gain. (b) Step load response.

the second load subsystem, purposely designed to stabilize the239

front-end converter−−the stabilizing load subsystem. Detailed240

design procedures and selection of filter parameters for the241

Fig. 7. Load impedance |ZL | of stabilizing load subsystem and outputimpedance |ZoC | of front-end converter.

stabilizing load subsystem will be separately discussed later 242

in Section VI. 243

The stabilizing load subsystem is implemented by simply 244

adjusting the circuit components of the line filter in order 245

to modify the load impedance Z L , while using the same 246

buck converter downstream. The systematic selection of the 247

filter components, in consideration of ZoC characteristics and 248

filter structure, produces the load impedance that provides 249

the desired phase margin and transient performance for the 250


Fig. 7 shows the load impedance |Z L | of the stabilizing 252

load subsystem, along with the output impedance of the 253

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Fig. 8. Front-end boost converter with stabilizing load subsystem. (a) Block diagram. (b) Impedances at input port and minor loop gain Tmn1. (c) Impedancesat output port and minor loop gain Tmn2.

front-end converter, |ZoC |. Unlike the previous case of254

Fig. 5(c), |Z L | shows a considerable overlap with |ZoC |.255

As will be demonstrated later, the impedance overlap is the256

very source of the stabilizing effects of the load subsystem.257

Fig. 8(a) depicts the front-end boost converter coupled with258

the stabilizing load subsystem. The stability of the boost259

converter can be assessed through two different approaches.260

The first approach is to analyze the minor loop gain at the261

input port of the boost converter. The second approach directly262

evaluates the loop gain of the converter. This section analyzes263

the stabilizing effects via these two approaches.264

A. Minor Loop Gain Analysis265

Two distinct minor loop gains are identified for the boost266

converter in Fig. 8(a). The first minor loop gain is the267

impedance ratio at the input port of the boost converter,268

Tmn1 = ZoF/Z ′′iC , where ZoF is the output impedance of269

the input filter and Z ′′iC is the input impedance of the boost270

converter, evaluated at the presence of the stabilizing load 271

subsystem. The minor loop gain Tmn1 can be used to validate 272

the stabilizing effects based on the Nyquist stability criterion. 273

The second minor loop gain is defined at the output port of 274

the converter, Tmn2 = ZoC/Z L , where ZoC is the output 275

impedance of the nearly unstable boost converter, defined 276

earlier in Fig. 4(a), and Z L is the load impedance. As will 277

be clarified later, Tmn2 is not suited for adopting the Nyquist 278

stability criterion. Nonetheless, Tmn2 provides valuable infor- 279

mation for the design and analysis of the stabilizing load 280

subsystem. 281

Fig. 8(b) shows the magnitude plots of ZoF and Z ′′iC , 282

along with the polar plot of Tmn1 = ZoF/Z ′′iC . In order 283

to manifest the impacts of the stabilizing load subsystem, 284

the plots are shown together with the cases of the current 285

sink load. The magnitude plots clearly show the impacts of 286

the stabilizing load subsystem. The stabilizing load system 287

provides a substantial boost for |Z ′′iC |. As will be discussed in 288

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Appendix A, the amount and frequency range of the magnitude289

boost are determined by the overlap between |Z L | and |ZoC |.290

The boost in |Z ′′iC | creates a comfortable gap between |ZoF |291

and |Z ′′iC | for all frequencies. This impedance gap totally292

eliminates the detrimental interaction between the input filter293

and the boost converter [20], which plagued the converter294

performance with the current sink, as well as the case of the295

conventional load subsystem.296

The stabilizing effects of the load subsystem are further297

clarified in the polar plot of the minor loop gain. The polar298

plot of ZoF/Z ′′iC remains close to the origin and stays well299

inside the unit circle. The polar plot guarantees the stability300

of the converter coupled with the stabilizing load subsystem.301

This is in sharp contrast to the case of the current sink load,302

where the polar plot of ZoF/ZiC dangerously approaches the303

(−1, 0) point and makes the converter nearly unstable.304

Fig. 8(c) shows the information about the second minor305

loop gain, Tmn2 = ZoC/Z L . The |ZoC | and |Z L | show a large306

overlap, thus indicating a great degree of interaction between307

the boost converter and the load subsystem. This interaction308

is the source that transforms the nearly unstable converter into309

a stable converter.310

Unlike the first minor loop gain Tmn1, the Nyquist stability311

criterion cannot be applied to Tmn2. The Nyquist criterion312

is only valid when the front-end converter and the load313

subsystem are individually stable as a standalone functional314

unit. The nearly unstable front-end converter does not fully315

meet this assumption.316

Although not suitable for the Nyquist analysis, the polar317

plot of Tmn2 carries the important information for the design318

and analysis of the stabilizing load subsystem. The polar plot319

of Tmn2 is shown in Fig. 8(c). With the impedance overlap,320

the polar plot exits the unit circle at ω1 = 2π · 267 rad/s and321

later enters the unit circle at ω2 = 2π · 1.7 × 103 rad/s. Two322

different angles are identified at the unit circle crossing points323

of the polar plot. The first angle is denoted as PM1 = 68°324

at ω1. The second angle is defined as PM2 = 78° at ω2. These325

two angles are recognized as the phase margins for the second326

minor loop gain, Tmn2 [18]. The vital role of the phase margins327

in the design and analysis of the stabilizing load subsystem328

will be revealed in the following analysis.329

B. Converter Loop Gain Analysis330

An earlier publication [30] showed that the loop gain of the331

front-end converter with the load subsystem, TmL in Fig. 8(a),332

is given by333

TmL = TmC

1 + (1 + TmC ) ZoCZL

(1)334

where TmC is the loop gain of the boost converter terminated335

with a current sink. The loop gain expression is rewritten as336

TmL = TmC

1 + Tmn2 + TmC Tmn2(2)337

where Tmn2 = ZoC/Z L is the second minor loop gain defined338

at the output port of the boost converter.339

Fig. 9 shows the Bode plots of the transfer functions340

appearing in the loop gain expression of (2). In Fig. 9,341

Fig. 9. Loop gain analysis of boost converter combined with load subsystem.

ω1 and ω2 are the zero-dB crossover frequencies of |Tmn2|, 342

which are the same as the intersection frequencies between 343

|ZoC | and |Z L |, shown in Fig. 8. The notations of ω1 and ω2 344

will be used consistently throughout this paper. By incorporat- 345

ing the information in Fig. 9 into the expression (2), the loop 346

gain of the boost converter with the stabilizing load subsystem 347

is analyzed as follows. 348

From the low- to mid-frequency range, well beyond the 349

0-dB crossover frequency of |TmL |, the conditions 1 � 350

|TmC Tmn2| and |Tmn2| � |TmC Tmn2| prevail. Accordingly, 351

the loop gain expression is approximated as 352

TmL = TmC

1 + Tmn2 + TmC Tmn2353

≈ TmC

Tmn2 + TmC Tmn2≈ TmC

TmC Tmn2= 1

Tmn2. (3) 354

The above relation implies that, up to the 0-dB crossover 355

frequency, |TmL | follows the mirror image of |Tmn2| reflected 356

on the 0-dB axis, as highlighted in Fig. 9. 357

The converter loop gain is largely determined as the mirror 358

image of |Tmn2| reflected on the 0-dB axis. Accordingly, 359

the crossover frequency of the converter loop gain is almost 360

identical to that of the minor loop gain Tmn2. Furthermore, 361

the phase margin of the converter loop gain is approximately 362

the same as the phase margin of Tmn2 evaluated at ω1, 363

PM1 in Fig. 8(c). The phase margin of TmL is determined 364

by the s-domain locations of the solutions of the equation 365

1 + TmL = 0. Likewise, the phase margin of Tmn2 is decided 366

by the locations of the roots of 1 + Tmn2 = 0. Equation (3) 367

indicates that 1 + TmL = 0 is identical to 1 + Tmn2 = 0. 368

Therefore, TmL and Tmn2 have the same phase margin. 369

The results of the previous loop gain analysis are generally 370

applicable to the front-end converters which are coupled with 371

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another converter via a custom-designed intermediate line372

filter.373

1) The relation TmL ≈ 1/Tmn2 holds true when the condi-374

tion ω1 < ωc < ω2 is fulfilled, where ωc is the loop375

gain crossover frequency of the standalone front-end376

converter [15].377

2) The condition ω1 < ωc < ω2 can be met by controlling378

the resonant frequency of the line filter, because the loop379

gain crossover frequency ωc and |ZoC | characteristics380

are known at the design stage of the front-end converter.381

The previous analysis indicates that the loop gain of the382

front-end converter can be programmed into an intended383

structure by purposely designing the load subsystem. The load384

subsystem was designed to offer a 68°-phase margin for the385

converter loop gain at the zero-dB crossover frequency of386

ω1 = 2π · 267 rad/s. The phase margin of the converter loop387

gain is experimentally found as 58° at the aimed crossover388

frequency.389

C. Output Impedance and Step Load Response390

The stabilizing effects are also evident in the output391

impedance and step load response of the converter. Fig. 10(a)392

displays the output impedance of the converter, |ZoL|, at the393

presence of the stabilizing load subsystem, in comparison394

with the case of the current sink load, |ZoC |. The load395

impedance |Z L | is also shown in Fig. 10(a). With the current396

sink, the output impedance exhibited a sharp peaking due to397

the marginal phase margin. The output impedance with the398

stabilizing load subsystem is utterly reshaped and the peaking399

is completely removed.400

The output impedance of the converter with the load401

impedance Z L is described as402

ZoL = ZoC ‖ Z L = ZoC1

1 + ZoCZL

403

≈

⎧⎪⎨

⎪⎩

ZoCZoCZL

= Z L where |ZoC/Z L | � 1

ZoC where |ZoC/Z L | � 1.

404

The output impedance |ZoL| follows |ZoC | at low and high405

frequencies where |ZoC/Z L | � 1. On the other hand, |ZoL|406

tracks |Z L | in the frequency range of ω1 < ω < ω2, in which407

the impedance overlap between |ZoC | and |Z L | occurs.408

The output impedance |ZoL| exhibits the two peaks around409

ω1 and ω2, at which |ZoC | intersects with |Z L |. The peak410

can be transformed into an underdamped second-order term411

in the s-domain expression [31], which triggers a decaying412

oscillation in the time-domain response. The frequency of the413

oscillation coincides with the frequency of the peak. Because414

ω1 � ω2, the high-frequency oscillation at ω2 vanishes so415

fast that only the slow-decaying oscillation at ω1 dominates416

the time-domain waveform. Detailed discussions about |ZoL|417

and step load response are given in Appendix B.418

Fig. 10(b) compares the two transient responses of the419

output voltage of the boost converter. The upper waveform420

is the transient response of the converter combined with the421

stabilizing load subsystem, in response to the 3.1-A step422

Fig. 10. Output impedance and step load response of boost converter.(a) Output impedance with stabilizing load subsystem |ZoL |, outputimpedance with current sink load |ZoC |, and load impedance |ZL |. (b) Stepload responses.

load changes in the downstream buck converter. The lower 423

waveform is the transient response for the conventional load 424

subsystem, previously shown in Fig. 5(b). When the two 425

transient responses are contrasted, the effects of the stabilizing 426

load subsystem are evident. 427

As will be demonstrated in Appendix B, the transient 428

behavior of the output voltage is closely related with the phase 429

margin of the minor loop gain Tmn2 at ω1, PM1, and the 430

structure of the output impedance, |ZoL|. The phase margin 431

and output impedance are both controlled by the load sub- 432

system. Thus, the transient performance can be programmed 433

by the load subsystem. The design goal of the stabilizing 434

load subsystem was a 0.18-V maximum overshoot and 3.3-ms 435

settling time for the output voltage. The experimental output 436

voltage shows a 0.16-V maximum overshoot which settles 437

within 4 ms. 438

V. LOAD CONVERTER DYNAMICS−−IMPACTS OF 439

IMPEDANCE OVERLAP AT DC LINK 440

This section investigates the dynamics and performance 441

of the load converter employed in the conventional load 442

subsystem and also in the stabilizing load subsystem. The 443

impacts of the overlap between the output impedance of the 444

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Fig. 11. Load subsystem analysis. (a) Block diagram. (b) Impedance analysiswith conventional load subsystem. (c) Impedance analysis with stabilizing loadsubsystem.

front-end converter, |ZoC |, and the load impedance, |Z L |, are445

analyzed.446

A. Impedance Analysis447

Fig. 11(a) is the block diagram of the system seen by448

the load converter. The front-end converter is represented by449

the Thevenin’s form, where ZoC is the output impedance of the450

converter. The various impedances are defined at the input port451

and output port of the line filter. In particular, Zs is the source452

impedance seen by the load converter. The source impedance453

is given by454

Zs = (ZoC + Zser) ‖ Zpar (4)455

where Zser = sL f + Rl f denotes the series impedance and456

Zpar = 1/sCF + Rcf is the parallel impedance of the line457

filter. The load impedance Z L is expressed as458

Z L = Zser + (Zpar ‖ Z ′

iC

). (5)459

Based on (4) and (5), the plots of |Zs | and |Z L | are constructed460

in Fig. 11(b) and (c). Fig. 11(b) is the case of the conventional461

load subsystem, while Fig. 11(c) considers the stabilizing load 462

subsystem. 463

Referring to Fig. 11(c), the overlap between |ZoC | and 464

|Z L | provides an isolation between |Zs | and |Z ′iC |, as the 465

consequential effects of the basic circuit characteristics of 466

the low-pass line filter [32]. The impedance isolation blocks 467

the adverse impacts of the unstable front-end converter. The 468

deeper the impedance overlap at the output of the front-end 469

converter, the wider the impedance isolation at the input of 470

the load converter. With a larger overlap between |ZoC | and 471

|Z L |, or equivalently a greater isolation between |Zs | and 472

|Z ′iC |, the downstream load converter will closely replicate 473

the performance that was initially produced before being 474

combined with the front-end converter. 475

B. Load Converter Dynamics 476

This section validates the theoretical predictions of the pre- 477

ceding impedance analysis and demonstrates the performance 478

of the load converter. 479

1) Conventional Load Subsystem: Fig. 12 shows the dynam- 480

ics and the performance of the load converter in the conven- 481

tional load subsystem. Fig. 12(b) and (c) is the impedance 482

comparison at the input port and output port of the line filter. 483

The impedance isolation at the input port of the load converter 484

is |Zgap| = 14 dB. 485

Fig. 12(d)–(f) shows the performance of the load converter. 486

The loop gain and output impedance of the load converter 487

are displayed in Fig. 12(d) and (e), in comparison with 488

those of the standalone buck converter powered from an 489

ideal voltage source. The load converter shows some devia- 490

tions from the predictions of the standalone buck converter. 491

The 14-dB impedance isolation is not sufficient to completely 492

block the dynamic interaction from the front-end converter— 493

the unstable dynamics are partially penetrated into the load 494

converter. Fig. 12(e) shows the transient responses of the load 495

converter, in response to 1 A step current changes in the output 496

current of the load converter. The various waveforms indicate 497

that the load converter is on the verge of instability. 498

2) Stabilizing Load Subsystem: The dynamics of the sta- 499

bilizing load subsystem are illustrated in Fig. 13. As shown 500

in Fig. 13(b), the impedance isolation is increased to |Zgap| = 501

35 dB, thereby providing a substantial block from the front- 502

end converter dynamics. The load subsystem reveals a stable 503

operation in the steady state and transient period. In fact, 504

the performance of the load converter is practically indis- 505

tinguishable from the predictions of the standalone buck 506

converter. 507

The stabilizing load subsystem may require larger reactive 508

components, particularly a large filter capacitor, thereby slow- 509

ing down the dc link dynamics. However, the load converter 510

reacts as fast as the standalone buck converter, because the 511

impedance isolation offers a near-complete block from the 512

slow dc link dynamics. 513

VI. DESIGN OF STABILIZING LOAD SUBSYSTEM 514

The load subsystem affects the upstream converter through 515

the minor loop gain, Tmn2 = ZoC/Z L , or the impedance 516

overlap between |ZoC | and |Z L |. Given that ZoC is predefined, 517

IEEE P

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Fig. 12. Load converter dynamics in conventional load subsystem. (a) Block diagram. (b) Impedances at front-end converter output. (c) Impedances at loadconverter input. (d) Loop gain of load converter. (e) Output impedance of load converter. (f) Step load response of load subsystem.

Z L can be purposely designed so that Tmn2 has a specified518

phase margin. The resulting phase margin will become the519

phase margin of the front-end converter coupled with the load520

subsystem.521

The load impedance Z L is a cascaded connection of the522

filter impedance and the input impedance of the regulated523

load converter. The input impedance of a regulated converter524

behaves as a negative resistance, −RiC , up to the converter’s525

loop gain crossover frequency. The loop gain crossover fre-526

quency is usually increased beyond the input filter resonant527

frequency, in order to achieve fast converter dynamics. For528

that case, the input impedance of the regulated converter529

retains the negative resistance characteristics for the frequency530

range of practical importance. Under this assumption, the load531

converter is replaced with the negative resistance for the532

purpose of the load impedance evaluation. Fig. 14(a) and (b) 533

illustrates this concept. The value of the negative resistance is 534

given in [15] 535

−RiC = − VO

IO= −46

2= −23 � (6) 536

where VO is the output voltage of the front-end converter and 537

IO is the dc current flowing into the load subsystem. 538

From Fig. 14(b), the load impedance Z L is evaluated as 539

Z L = sL f + Rl f +(

Rd + 1

sC f

)∥∥∥∥ − RiC 540

= −RiC

1 + sQoωo

s2

ω2o

1 + sωp

(7) 541

IEEE P

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Fig. 13. Load converter dynamics in stabilizing load subsystem. (a) Impedances at front-end converter output. (b) Impedances at load converter input. (c)Loop gain of load converter. (d) Output impedance of load converter. (e) Step load response of load subsystem.

where542

ωo =√

Rl f − RiC

Rd − RiC

1

L f C f≈ 1

√L f C f

(8)543

Qo = 1

ωo

Rl f − RiC

L f + C f (Rl f Rd − RiC (Rl f + Rd ))544

≈ 1

Rl f + Rd

√L f

C f(9)545

ωp = 1

C f (Rd − RiC )≈ − 1

C f RiC(10)546

with the assumptions of RiC � Rd , RiC � Rl f , and547

C f (Rl f + Rd ) � L f /RiC . The ωp in (10) is a right-half-548

plane pole, which boosts � Z L by 90◦ while bringing down549

|Z L | by −20 dB/decade slope. The asymptotic plot of |Z L |550

is drawn in Fig. 15(a), along with the Bode plot of |ZoC | of551

the front-end boost converter.552

The frequency ω1 in Fig. 15(a) is the frequency553

at which |Z L | intersects with |ZoC |, previously shown554

in Figs. 8(c), 9, and 10. The following relationship555

holds at ω1 : 556

20 log RiC − 20 log

(ω1

ωp

)

= |ZoC |@ω1. (11) 557

The phase of Z L at ω1 is determined as 558

� Z L @ω1 = −180° + tan−1(

ω1

ωp

)

+ tan−1

(ω1/(Qoωo)

1 − ω21/ω

2o

)

. 559

(12) 560

As shown in Fig. 8(c), the phase margin of the minor loop 561

gain is defined at ω1 as [15] 562

PM1 = 180° − ( � ZoC @ω1 − � Z L @ω1). (13) 563

The expressions (11)–(13) are simultaneously solved to 564

eliminate ωp and to extract a direct correspondence 565

between ω1 and PM1, under the assumption that Qo and 566

IEEE P

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Fig. 14. Load impedance evaluation. (a) Load subsystem. (b) Circuit model.

ωo are preselected567

PM1 = −� ZoC @ω1 + tan−1(

Ric

10|ZoC |@ω1/20

)

568

+ tan−1

(ω1/(Qoωo)

1 − ω21/ω

2o

)

. (14)569

This relationship is converted into the ω1 − PM1 curve,570

which constitutes the design curve for the line filter.571

Fig. 15(b) is the ω1 − PM1 curve, constructed with Qo =572

0.814 and ωo = 2π ·697 rad/s. The selection of Qo = 0.814 is573

good engineering practice, while ωo can be selected differently574

based on the electromagnetic interference specifications [32].575

The ω1−PM1 curve specifies the attainable phase margin PM1576

and the associated value of ω1, for the given ZoC charac-577

teristics and line filter structure. The ω1 − PM1 curve is578

plotted for the frequency range of 2π · 10 rad/s < ω1 <579

2π · 500 rad/sec. When ω1 exceeds 2π · 500 rad/sec, the load580

subsystem would lose the stabilizing effects. For the experi-581

mental front-end converter, ω1 is selected at 2 π · 267 rad/s582

to obtain the phase margin of PM1 = 68°, as indicated with a583

dashed vertical line in Fig. 15(b). The required pole frequency584

ωp for this design is determined from (11)585

ωp = 10|ZoC |ω1

20ω1

Ric586

= 10−10.5

202π · 267

23= 2π · 3.46 rad/s. (15)587

From the given ωp , ωo, and Qo values, the filter compo-588

nents are determined as L f = 26 μH, Rl f = 0.015 �,589

C f = 2.0 mF, and Rd = 0.125 �, using (6) and (8)–(10).590

The above design procedures are formulated using the phase591

margin, PM1, of the minor loop gain, Tmn2. However, the loop592

gain analysis in Section IV-B confirmed that PM1 is a good593

approximation for the phase margin of the front-end converter.594

The accuracy of the ω1 − PM1 curve in Fig. 15(b), which595

served as the design curve for the stabilizing load subsystem,596

is assessed with both the simulation results and experimental597

data. The small squares represent the phase margins of the598

Fig. 15. Line filter design and front-end converter performance. (a) Linefilter design. (b) ω1 and phase margin PM1. (c) ω1 and maximum overshoot.(d) ω1 and settling time.

converter’s loop gain, obtained from the frequency-domain 599

simulations. The large square is the measured phase margin 600

of the converter. The experimental data revealed a 58° phase 601

margin at ω1 = 2π · 267 rad/s, while the design target was 602

PM1 = 68° at ω1 = 2π · 267 rad/s. 603

The phase margin PM1 in Fig. 15(b) functions as an 604

instrumental tool to predict other performance metrics of the 605

converter. In particular, PM1 provides good estimations of the 606

maximum overshoot and settling time of the output voltage of 607

IEEE P

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the front-end converter. Detailed predictions of the transient608

performance are given in Appendix B.609

Fig. 15(c) and (d) is the predictions and assessments of the610

maximum overshoot and the 5%-boundary settling time for the611

case of the 3.1-A change in the load current of the downstream612

buck converter. The theoretical curves are compared with both613

the simulation results and experimental data. The experimental614

data showed a 0.16-V overshoot and 4-ms settling time, while615

the theoretical design targets were the 0.18-V overshoot and616

3.3-ms settling time.617

VII. CONCLUSION618

The dynamic interaction between the upstream converter619

and the load subsystem is completely described by the620

impedance overlap between the output impedance of the621

converter and the input impedance of the load subsystem.622

This impedance overlap reshapes the input impedance, loop623

gain, and output impedance of the upstream converter, thereby624

utterly changing the small-signal dynamics of the converter.625

This change is not always detrimental. In fact, the impedance626

overlap can enhance the stability margin and performance627

of the upstream converter. Even an unstable converter could628

secure the desired stability margin and transient performance629

with aid of an adequate load subsystem, which offers the nec-630

essary impedance overlap. This paper analyzed and validated631

these stabilizing effects using the load subsystem, consisting632

of an intermediate line filter and a downstream buck converter.633

The impedance overlap at the output of the front-end con-634

verter produces an impedance isolation at the input port of the635

load converter. The resulting impedance isolation blocks the636

adverse interaction from the unstable front-end converter. With637

a sufficient impedance isolation, the load converter retains638

the stability and the performance that were aimed during the639

design stage as a standalone converter.640

This paper presented the design of the stabilizing load641

subsystem which provides the specified phase margin and tran-642

sient performance for the upstream converter. Once the output643

impedance of the upstream converter is known, the input644

impedance of the load subsystem can be designed, by only645

adjusting the parameters of the line filter, to implement the sta-646

bilizing load subsystem. The resulting load subsystem would647

offer the intended frequency- and time-domain performance,648

largely irrespective of the dynamics of the front-end converter649

upstream.650

This paper demonstrated the design procedures for a sta-651

bilizing load subsystem using the specific output impedance652

characteristics of a nearly unstable upstream converter. In prac-653

tice, however, the design of the stabilizing load subsystem can654

be implemented without the exact information about the output655

impedance of the upstream converter, as justified below.656

1) The upstream converter is initially designed assuming657

an ideal voltage source and current sink load, and658

will produce the initial output impedance under these659

operational conditions.660

2) The actual output impedance will vary from the initial661

output impedance when the converter is coupled with a662

practical source subsystem. Even so, the actual output663

impedance largely retains the characteristics of the initial664

output impedance, if current mode control is employed 665

to the converter [33]. Thus, the stabilizing load subsys- 666

tem is to be designed using the initial output impedance. 667

3) The stabilizing load subsystem, designed using the ini- 668

tial output impedance, will be equally functional and 669

effective for wide classes of practical source subsystems, 670

regardless of their respective small-signal dynamics. 671

The proposed design approach for the stabilizing load 672

subsystem is applicable to the cases where the upstream 673

converter was initially properly designed but later became 674

nearly unstable due to detrimental interaction originating from 675

unknown source subsystems. More importantly, the method is 676

also adaptable to build a reliable dc-to-dc power conversion 677

system, which retains the stability and performance in the 678

presence of considerable drifts in the small-signal dynamics 679

of the upstream converter. 680

APPENDIX 681

A. Input Impedance With Stabilizing Load Subsystem 682

The input impedance of the converter coupled with the load 683

impedance Z L is given in [26] 684

Z ′′iC = ZiC

1 + ZoCZL

1 + Z ′oC

ZL

685

where Z ′oC represents the output impedance of the converter 686

evaluated with the input port opened. For most cases, it can 687

be shown that |Z ′oC | � |Z L | so that |Z ′

oC/Z L | � 1. This 688

condition simplifies the Z ′′iC expression to 689

Z ′′iC ≈ ZiC

(

1 + ZoC

Z L

)

690

which can be further approximated to 691

Z ′′iC ≈

⎧⎨

⎩

ZiCZoC

Z L: for frequencies where |ZoC/Z L | � 1

ZiC : for frequencies where |ZoC/Z L | � 1.692

Thus, the amount of the impedance overlap between |ZoC | 693

and |Z L | is projected as a magnitude boost in |Z ′′iC | in the 694

frequency range of the overlap, ω1 < ω < ω2, as can be 695

confirmed from Fig. 8(b) and (c). 696

B. Step Load Response of Front-End Converter 697

From Fig. 10(a), the output impedance of the front-end 698

converter is approximated as 699

ZoL ≈ kds1

1 + sQ1ω1

+ s2

ω21

≡ Z̃oL (16) 700

only considering the low-frequency dynamics of ZoL , origi- 701

nating from the differentiation function and the double pole 702

around ω1, while ignoring the high-frequency dynamics. 703

This approximation will be reasonable under the assumptions 704

ω1 � ω2 and that the second-phase margin of the minor loop 705

gain, PM2, is sufficiently large [31]. 706

By relating |ZoL | plot in Fig. 10(a) and Z̃oL in (16), it can 707

be inferred that 708

Q1 ≈ 1√2 − 2 cos PM1

(17) 709

IEEE P

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Fig. 16. Step load response. (a) Prediction of (16). (b) Simulated outputvoltage waveform. (c) Experimental measurement.

because |ZoL| undergoes a peaking of 20 log (1/(2−710

2 cos PM1)1/2) around ω1 [26], while the second-order711

Z̃oL function also produces the peaking of 20 log Q1712

around ω1 [31].713

The leading coefficient kd in (16) is determined by714

equating |Z̃oL | to |ZoL| at low frequencies, for instance,715

ω = 2π · 10 Hz716

|kds|s= j2π ·10 = |ZoC |@2π ·10 = −37.6 dB717

⇒ kd = 10−37.6/20

2π · 10= 2.09 × 10−4. (18)718

When a step change of I ′step occurred in the output current719

of the load converter, whose dynamics are much faster than720

those of the intermediate line filter, the output voltage of the721

front-end converter is approximately expressed as722

vO (t) = L−1(

Z̃oLIstep

s

)

= L−1

⎛

⎝kd Istep

1 + sQ1ω1

+ s2

ω21

⎞

⎠723

= Istepkdω1√

1 − 1/(4Q2

1

)e− ω1

2Q1t sin

(ω1

√

1 − 1/(4Q2

1

))t (19)724

where Istep is the equivalent step current change, reflected to725

the output terminal of the front-end converter726

Istep = I ′step

V ′O

VO(20)727

with VO = 46 V being the output voltage of the front-end 728

converter and V ′O = 15 V being the output voltage of the load 729

converter. 730

The maximum overshoot of the output voltage 731

�vO(t)max = Istepkdω1e−(

1√4Q2

1−1tan−1

√

4Q21−1

)

(21) 732

occurs at 733

tp =tan−1

√

4Q21 − 1

ω1

√

1 − 1/(4Q2

1

). (22) 734

The 5%-boundary settling time, ts , of the output voltage is 735

evaluated as 736

e−

ω1

2Q1ts = 0.05 ⇒ ts ≈ 6Q1

ω1. (23) 737

The accuracy of the preceding analyzes is supported by 738

Fig. 16, which compares the theoretical plot of (19) 739

in Fig. 16(a), the simulated output voltage waveform 740

in Fig. 16(b), and the experimental measurement in Fig. 16(c). 741

REFERENCES 742

[1] W. A. Tabisz, M. M. Jovanovic, and F. C. Lee, “Present and future of 743

distributed power systems,” in Proc. IEEE Appl. Power Electron. Conf. 744

Expo., Feb. 1992, pp. 11–18. 745

[2] S. K. Pidaparthy and B. Choi, “Input impedances of PWM DC- 746

DC converters: Unified analysis and application example,” J. Power 747

Electron., vol. 16, no. 6, pp. 1–12, Nov. 2016. 748

[3] M. Cespedes, L. Xing, and J. Sun, “Constant-power load system 749

stabilization by passive damping,” IEEE Trans. Power Electron., vol. 26, 750

no. 7, pp. 1832–1836, Jul. 2011. 751

[4] M. Wu and D. D.-C. Lu, “A novel stabilization method of LC input filter 752

with constant power loads without load performance compromise in DC 753

microgrids,” IEEE Trans. Ind. Electron., vol. 62, no. 7, pp. 4552–4562, 754

Jul. 2015. 755

[5] M. Wu, D. D.-C. Lu, and C. K. Tse, “Direct and optimal linear active 756

methods for stabilization of LC input filters and DC/DC converters under 757

voltage mode control,” IEEE J. Emerg. Sel. Topics Circuits Syst., vol. 5, 758

no. 3, pp. 402–412, Sep. 2015. 759

[6] A. Riccobono, J. Siegers, and E. Santi, “Stabilizing positive feed-forward 760

control design for a DC power distribution system using a passivity- 761

based stability criterion and system bus impedance identification,” in 762

Proc. 29th Annu. IEEE Appl. Power Electron. Conf. Expo. (APEC), 763

Mar. 2014, pp. 1139–1146. 764

[7] J. Siegers, S. Arrua, and E. Santi, “Stabilizing controller design for 765

multi-bus MVDC distribution systems using a passivity based stability 766

criterion and positive feed-forward control,” in Proc. IEEE Energy 767

Convers. Congr. Expo. (ECCE), Sep. 2015, pp. 5180–5187. 768

[8] G. Sulligoi, D. Bosich, G. Giadrossi, L. Zhu, M. Cupelli, and A. Monti, 769

“Multiconverter medium voltage DC power systems on ships: Constant- 770

power loads instability solution using linearization via state feedback 771

control,” IEEE Trans. Smart Grid, vol. 5, no. 5, pp. 2543–2552, 772

Sep. 2014. 773

[9] X. Zhang, X. Ruan, and Q.-C. Zhong, “Improving the stability of 774

cascaded DC/DC converter systems via shaping the input impedance 775

of the load converter with a parallel or series virtual impedance,” IEEE 776

Trans. Ind. Electron., vol. 62, no. 12, pp. 7499–7512, Dec. 2015. 777

[10] X. Lu, K. Sun, J. M. Guerrero, J. C. Vasquez, L. Huang, and J. Wang, 778

“Stability enhancement based on virtual impedance for DC microgrids 779

with constant power loads,” IEEE Trans. Smart Grid, vol. 6, no. 6, 780

pp. 2770–2783, Nov. 2015. 781

[11] X. Zhang, Q. C. Zhong, and W. L. Ming, “Stabilization of cascaded 782

DC/DC converters via adaptive series-virtual-impedance control of 783

the load converter,” IEEE Trans. Power Electron., vol. 31, no. 9, 784

pp. 6057–6063, Sep. 2016. 785

[12] I. Cvetkovic et al., “Dynamic interactions in hybrid AC/DC electronic 786

power distribution systems,” in Proc. IEEE 8th Int. Conf. Power 787

Electron. ECCE Asia (ICPE ECCE), May 2011, pp. 2121–2128. 788

IEEE P

roof


[13] B. Wen, D. Boroyevich, R. Burgos, P. Mattavelli, and Z. Shen, “Small-789

signal stability analysis of three-phase ac systems in the presence of790

constant power loads based on measured d-q frame impedances,” IEEE791

Trans. Power Electron., vol. 30, no. 10, pp. 5952–5963, Oct. 2015.792

[14] S. K. Pidaparthy and B. Choi, “Designing control loop for PWM793

converters in DC-to-DC power conversion systems,” in Proc. 40th Annu.794

Conf. IEEE Ind. Electron. Soc. (IECON), Oct. 2014, pp. 5094–5100.795

[15] S. K. Pidaparthy and B. Choi, “Stability analysis of PWM converters796

connected to general load subsystems,” in Proc. IEEE 9th ICPE-ECCE797

Asia, Jun. 2015, pp. 1033–1040.798

[16] M. Hankaniemi, M. Karppanen, and T. Suntio, “Load-imposed instability799

and performance degradation in a regulated converter,” IEE Proc. Electr.800

Power Appl., vol. 153, no. 6, pp. 781–786, Nov. 2006.801

[17] P. Li and B. Lehman, “Performance prediction of DC-DC converters802

with impedances as loads,” IEEE Trans. Power Electron., vol. 19, no. 1,803

pp. 201–209, Jan. 2004.804

[18] C. M. Wildrick, F. C. Lee, B. H. Cho, and B. Choi, “A method of805

defining the load impedance specification for a stable distributed power806

system,” IEEE Trans. Power Electron., vol. 10, no. 3, pp. 280–285,807

May 1995.808

[19] S. K. Pidaparthy, B. Choi, H. Kim, and Y. Kim, “Stabilizing effects of809

load subsystem in multi-stage DC-to-DC power conversion systems,” in810

Proc. IEEE 17th Workshop COMPEL, Jun. 2016, pp. 1–7.811

[20] B. Choi, D. Kim, D. Lee, S. Choi, and J. Sun, “Analysis of input812

filter interactions in switching power converters,” IEEE Trans. Power813

Electron., vol. 22, no. 2, pp. 452–460, Mar. 2007.814

[21] X. Zhang, X. Ruan, H. Kim, and C. K. Tse, “Adaptive active capacitor815

converter for improving stability of cascaded DC power supply system,”816

IEEE Trans. Power Electron., vol. 28, no. 4, pp. 1807–1816, Apr. 2013.817

[22] X. Liu, A. J. Forsyth, and A. M. Cross, “Negative input-resistance818

compensator for a constant power load,” IEEE Trans. Ind. Electron.,819

vol. 54, no. 6, pp. 3188–3196, Dec. 2007.820

[23] J. Wang and D. Howe, “A power shaping stabilizing control strategy821

for DC power systems with constant power loads,” IEEE Trans. Power822

Electron., vol. 23, no. 6, pp. 2982–2989, Nov. 2008.823

[24] M. K. Zadeh, R. Gavagsaz-Ghoachani, S. Pierfederici,824

B. Nahid-Mobarakeh, and M. Molinas, “Stability analysis and dynamic825

performance evaluation of a power electronics-based DC distribution826

system with active stabilizer,” IEEE J. Emerg. Sel. Topics Power827


[25] M. K. Zadeh, R. Gavagsaz-Ghoachani, J.-P. Martin,829

B. Nahid-Mobarakeh, S. Pierfederici, and M. Molinas, “Discrete-830

time modeling, stability analysis, and active stabilization of DC831

distribution systems with multiple constant power loads,” IEEE Trans.832

Ind. Appl., vol. 52, no. 6, pp. 4888–4898, Nov. 2016.833

[26] B. Choi, Pulsewidth Modulated DC-to-DC Power Conversion: Circuits,834

Dynamics, and Control Designs. Hoboken, NJ, USA: Wiley, 2013.835

[27] R. Erickson and D. Maksimovic, Fundamentals of Power Electronics.836

Springer, 2001.AQ:1 837

[28] R. Ridley, Power Supply Design: Control. Bradenton, FL, USA:838

Ridley Engineering, Incorporated, 2011.839

[29] R. D. Middlebrook, “Input filter considerations in design and application840

of switching regulators,” in Proc. IEEE Ind. Appl. Soc., Oct. 1976,841

pp. 366–382.842

[30] B. Choi, J. Kim, B. H. Cho, S. Choi, and C. M. Wildrick, “Designing843

control loop for DC-to-DC converters loaded with unknown AC dynam-844

ics,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 925–932, Aug. 2002.845

[31] K. Ogata, Modern Control Engineering, 4th ed. Upper Saddle River, NJ,846

USA: Prentice-Hall, 2001.847

[32] B. Choi and B. H. Cho, “Intermediate line filter design to meet both848

impedance compatibility and EMI specifications,” IEEE Trans. Power849

Electron., vol. 10, no. 5, pp. 583–588, Sep. 1995.850

[33] D. Kim, B. Choi, D. Lee, and J. Sun, “Dynamics of current-mode-851

controlled DC-to-DC converters with input filter stage,” in Proc.852

IEEE 36th Power Electron. Specialists Conf. (PESC), Jun. 2005,853

pp. 2648–2656.854

Syam Kumar Pidaparthy (S’–) received the 855

B.Tech. degree in electrical and electronics engi- 856

neering from Acharya Nagarjuna University, Guntur, 857

India, in 2010, and the M.S. degree in circuits and 858

embedded systems engineering from Kyungpook 859

National University, Daegu, South Korea, in 2013, 860

where he is currently pursuing the Ph.D. degree. 861

His current research interests include modeling, 862

dynamic analysis, and control design of large-scale 863

dc-to-dc power conversion systems. 864

AQ:2

Byungcho Choi (S’90–M’91) received the B.S. 865

degree in electronics from Hanyang University, 866

Seoul, South Korea, in 1980, and the M.S. and 867

the Ph.D. degrees in electrical engineering from 868

Virginia Polytechnic Institute and State Univer- 869

sity, Blacksburg, VA, USA, in 1988 and 1992, 870

respectively. 871

In 1996, he joined the School of Electrical Engi- 872

neering and Computer Science, Kyungpook National 873

University, Daegu, South Korea, where he is cur- 874

rently a Professor. He has authored the book 875

Pulsewidth Modulated DC-to-DC Power Conversion: Circuits, Dynamics, and 876

Control Designs (John Wiley & Sons, 2013). His current research interests 877

include modeling and design optimization of high-frequency power converters 878

for portable electronics, computer power systems, and distributed power 879

systems. 880

Hansang Kim received the B.S. degree in elec- 881

tronics engineering and the M.S. degree in circuit 882

and embedded systems engineering from Kyung- 883

pook National University, Daegu, South Korea, 884

in 2015 and 2017 respectively. 885


dynamic analysis, and control design of power con- 887

verters for distributed power systems. 888

Yeonjung Kim received the B.S. degree in elec- 889

tronics from Kyungpook National, Daegu, South 890

Korea, in 2016, where he is currently pursuing 891

the M.S. degree in circuits and embedded systems 892

engineering. 893


dynamic analysis, and control design of dc-to-dc 895

power converters for consumer electronics. 896

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IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS 1

Stabilizing Effects of Load Subsystem in MultistageDC-to-DC Power Conversion SystemsSyam Kumar Pidaparthy, Student Member, IEEE, Byungcho Choi, Member, IEEE,

Hansang Kim, and Yeonjung Kim

Abstract— This paper investigates the impacts of the load1

subsystem on stability and performance of the upstream con-2

verter in multistage dc-to-dc power conversion systems. This3

paper demonstrates that an appropriate load subsystem can be4

constructed to provide both stability and intended performance5

for the upstream converter at the brink of instability before being6

coupled with the load subsystem. These stabilizing effects of the7

load subsystem are theoretically analyzed and experimentally8

validated using a two-stage power conversion system, consisting9

of an upstream boost converter, downstream buck converter, and10

two filter stages. This paper also presents the design procedures11

for the stabilizing load subsystem, along with the performance12

verification of the upstream boost converter and the downstream13

buck converter.14

Index Terms— DC-to-DC power conversion systems, dynamic15

interaction, load subsystem design, loading effects, minor loop16

gain, stability and performance.17

I. INTRODUCTION18

DC-TO-DC power conversion systems employ several cas-19

caded stages of converters and filters to achieve efficient20

and reliable power conversion [1]. Fig. 1 shows the structure21

of a two-stage power conversion system, where a front-end22

converter with an input filter is connected to the load converter23

via an intermediate line filter stage. The combination of24

the line filter and load converter is considered as the load25

subsystem for the front-end converter.26

As addressed in previous publications [2]–[11], the27

front-end converter in Fig. 1 is exposed to potential insta-28

bility due to detrimental interactions among the cascaded29

dc-to-dc converters and filter stages. Advanced techniques30

have been proposed to alleviate or eliminate the stability31

problem, such as active damping schemes [3]–[5], feedforward32

controls [6], [7], controller tunings [8], and virtual impedance33

implementations [9]–[11]. These techniques attempted to avoid34

instability using an extra feedback controller or sophisticated35

control circuit. This paper presents a new method to secure36

stability of the front-end converter by employing the load37

Manuscript received January10, 2017; revised March 12, 2017 andApril 22, 2017; accepted May 6, 2017. This work was supported by BasicScience Research Program through the National Research Foundationof Korea funded by the Ministry of Education under GrantNRF-2016R1D1A1B03931966. Recommended for publication by AssociateEditor Marta Molinas. (Corresponding author: Byungcho Choi.)

The authors are with the School of Electronics Engineering, KyungpookNational University, Daegu 41566, South Korea (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/JESTPE.2017.2707093

Fig. 1. Two-stage DC-to-DC power conversion system. Functional blockFv (s) represents the feedback compensation of the front-end converter. Loadconverter is also closed-loop controlled.

subsystem itself as a stabilizer. The proposed scheme is imple- 38

mented by redesigning the pre-existing line filter in the load 39

subsystem without any additional feedback controller or con- 40

trol circuit. This method is an application of the impedance- 41

based frequency-domain approach, which has been widely 42

used for dc-to-dc power conversion systems [2]–[11] and are 43

now emerging for stability analysis and control of ac power 44

electronics systems [12], [13]. 45

The front-end converter is designed and fabricated without 46

any prior information about the load subsystem [14]. When 47

combined with the load subsystem, the front-end converter 48

is exposed to the dynamic interaction originating from the 49

load subsystem. The consequential effects of this interaction 50

have been studied in previous publications [15]–[17]. The 51

prior publications mainly addressed the detrimental effects 52

of the load subsystem, implicitly presuming that the front- 53

end converter is subject to the performance degradation when 54

combined with the load subsystem [16], [18]. 55

This paper will demonstrate that, on the contrary to general 56

perception, an appropriate load subsystem can be constructed 57

to stabilize a nearly unstable front-end converter. It will be 58

shown that the front-end converter, on the verge of instability, 59

could secure stable operation and intended performance with 60

aid of an appropriately engineered stabilizing load subsys- 61

tem [19]. This paper analyzes and validates the stabilizing 62

effects of the load subsystem using a two-stage dc-to-dc power 63

conversion system. This paper presents the design procedures 64

for the stabilizing load subsystem, which provides a desired 65

phase margin and a specified transient response for the front- 66

end converter. This paper also investigates the dynamics and 67

performance of the downstream load converter in the stabi- 68

lizing load subsystem. Although a specific two-stage power 69

conversion system is considered, the results of this paper can 70

be extended to general multistage dc-to-dc power conversion 71

systems. Potential applications of the outcomes of this paper 72

would include the following. 73

2168-6777 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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Fig. 2. Two-stage power conversion system consisting of front-end boost converter and load subsystem. Peak current mode control is employed to thefront-end boost converter. Current sensing network (CSN) with the dc gain of Ri = 0.5, Se = 5.68 × 104 V/s is the slope of the compensation ramp, PMW,and Fv (s) = 4.8 × 103(1 + s/2π · 258)/(s(1 + s/2π · 9.135 × 103)) is the voltage feedback compensation.

1) The implementation of a reliable dc-to-dc power con-74

version system which maintains the desired stability75

margin and transient performance, regardless of consid-76

erable drifts in the small-signal dynamics of upstream77

converters.78

2) The stabilization or performance enhancement of79

upstream converters which were initially well designed80

but later became destabilized or unsatisfactory, due to81

the detrimental interaction coming from unknown source82

subsystems.83

3) the establishment of general design guidelines for mul-84

tistage dc-to-dc power conversion systems with pre-85

dictable and programmable performance metrics.86

II. TWO-STAGE DC-TO-DC POWER CONVERSION SYSTEM87

Fig. 2 shows the two-stage power conversion system,88

consisting of two closed-loop controlled converters and two89

filter stages. A peak current-mode controlled boost converter90

with an input filter is employed as the front-end converter.91

The parameters for peak current mode control are shown92

in Fig. 2, along with the circuit components of the con-93

verter. The front-end boost converter is connected to the94

load subsystem, composed of an intermediate line filter and95

buck converter. The buck converter employs voltage mode96

control. The parameters of the buck converter will be given97

later in Fig. 5. Both the front-end converter and load sub-98

system are individually designed and later integrated together99

to form the complete two-stage dc-to-dc power conversion100

system.101

A. Front-End Boost Converter With Input Filter102

The front-end boost converter is designed and tested using103

a current sink load. The boost converter is duly designed104

based on the standard procedure [14]. However, the input105

filter parameters are deliberately selected to place the converter106

at the threshold of instability [20], in order to highlight107

the stabilizing effects of the load subsystem using a simple108

dc power conversion system.109

While the purpose of selecting the specific filter parame- 110

ters is to demonstrate the stabilizing effects using a simple 111

example, as practiced in earlier publications [5], [9], [21], 112

there are certain operational instances which resemble the 113

presentation of this paper. Such instance is illustrated in Fig. 3. 114

Fig. 3(a) is the block diagram of the front-end converter cou- 115

pled with a source converter through a filter stage. A current- 116

mode controlled buck converter is employed as the source 117

converter. The output impedance of the source converter, |Zo|, 118

the source impedance, |Zs |, and input impedance, |ZiC |, of the 119

front-end converter are evaluated for two different cases. 120

Fig. 3(b) shows the impedances when the source converter 121

is in regulation mode. A sufficient gap exists between |Zs | 122

and |ZiC |. Fig. 3(c) is the case when the source converter 123

enters a duty-ratio limited operation. Although the source 124

converter is still stable, the converter now presents a large 125

output impedance |Zo|. As will be shown in Section V, 126

the increased |Zo| induces a peak in |Zs|, thus shrink- 127

ing the distance to |ZiC |. This situation yields the case 128

of the front-end converter. Additional discussions about the 129

impacts of an unregulated converter operation can be found 130

in [9]. 131

For another instance, a properly designed input filter could 132

encounter the operational environment of improper input 133

filters. At a rated load current, |ZiC | and |ZoF | secure a 134

sufficient magnitude gap. When the load current is increased, 135

the gap diminishes and the converter becomes less stable. 136

This could eventually destabilize an originally stable front- 137

end converter. The converter stability under influences of load 138

current changes was also addressed in [9] and [21]. 139

In addition, the use of electrolytic capacitors and resistive 140

damping is often prohibited in space/marine power systems 141

and military applications [22]–[25]. In such cases, the selection 142

of the input filter components would be similar to that of the 143


Fig. 4(a) is the functional block diagram of the boost 145

converter connected to the current sink. The performance of 146

the boost converter is shown in Fig. 4(b)–(e). Fig. 4(b) (top) 147

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Fig. 3. Front-end converter coupled with source converter through filter stage. (a) Block diagram. (b) Impedance comparison with regulated source converter.(c) Impedance comparison with duty-ratio limited source converter.

is the comparison between the output impedance of the input148

filter, |ZoF |, and input impedance of the boost converter, |ZiC |.149

The predictions of the small-signal analysis in Fig. 4, as well as150

other forthcoming Bode plots, are shown in comparison with151

the experimental data. The small-signal predictions are made152

from computer simulations using small-signal models of pulse153

width modulation (PWM) converters [26], [27]. The experi-154

mental data are obtained with an impedance analyzer using155

the measurement techniques reported in [28]. The magnitude156

comparison reveals that |ZoF | nearly touches |ZiC |. This is157

an indication of the severe destructive interaction between158

the input filter and boost converter, which jeopardizes the159

converter operation [20]. Fig. 4(b) (bottom) is the polar plot of160

the impedance ratio ZoF/ZiC , referred to as the minor loop161

gain [29]. The polar plot resides inside the unit circle, but162

it closely approaches the (−1, 0) point. The nearness to the163

(−1, 0) point indicates the marginal stability and also signifies164

the presence of underdamped complex poles in the closed-loop165

transfer functions of the boost converter [26].166

The loop gain, TmC in Fig. 4(c), confirms that the converter167

is almost unstable with a marginal phase margin. The output168

impedance of the converter, |ZoC | in Fig. 4(d), exhibits a169

large peaking due to the small-phase margin. The instability170

is apparent in Fig. 4(e), which exhibits the output voltage of171

the boost converter, in response to the 1-A step changes in the172

sink current, IO .173

When the sink current is IO = 2 A, the converter exhibits174

a sustained oscillation due to the |ZoF | nearly touching |ZiC |.175

As IO is stepped down to 1 A, |ZiC | increases by 6 dB176

at low frequencies because the low-frequency asymptote of177

|ZiC | is inversely proportional to IO . Thus, an adequate gap178

is created between |ZoF | and |ZiC |. The converter now exits179

from instability and the oscillation soon ceases. When IO is180

again stepped up to 2 A, the oscillation resumes as shown181

in Fig. 4(e).182

III. CONVENTIONAL LOAD SUBSYSTEM AND 183

FRONT-END CONVERTER PERFORMANCE 184

The nearly unstable front-end converter will be stabilized 185

when coupled with a specially designed stabilizing load sub- 186

system. Before discussing the stabilizing load subsystem, this 187

section first presents the performance of the converter com- 188

bined with a nonstabilizing load subsystem, which does not 189

offer the stabilizing effects. The nonstabilizing load subsystem 190

is designed following the conventional approach, commonly 191

accepted as a standard design method [29]. The nonstabilizing 192

load subsystem will be referred to as the conventional load 193

subsystem. 194

Fig. 5(a) is a simplified circuit block diagram of the con- 195

ventional load subsystem, consisting of the voltage source, 196

filter stage, and buck converter. The input impedance of 197

the load subsystem, denoted as the load impedance Z L , is 198

the most important parameter to investigate the influences 199

of the load subsystem [15]. Fig. 5(b) displays the load 200

impedance |Z L |, together with the input impedance of the 201

downstream buck converter, denoted as |Z ′iC |, and an open- 202

circuit input impedance of the line filter, labeled as |Zi F |. 203

As discussed in [15], |Z L | initially follows |Z ′iC | at low 204

frequencies, but it tracks |Zi F | at mid and high frequencies. 205

Thus, |Zi F | of the line filter determines the load impedance 206

|Z L | for the frequencies of practical importance. 207

The influence of the load subsystem can be judged by com- 208

paring |Z L | and the magnitude of the output impedance of the 209

front-end converter, |ZoC | defined in Fig. 4(a). If the condition 210

|ZoC | � |Z L | is met for all frequencies, the load subsystem 211

has only negligible effects on the front-end converter. Con- 212

ventionally, the line filter components are selected for a larger 213

|Zi F | so that |Z L | stays well above |ZoC | for all frequencies. 214

Fig. 5(c) shows |ZoC | and |Z L | of the conventional load 215

subsystem whose line filter parameters are selected for a large 216

|Z L |: L f = 168 μH, Rl f = 0.06 �, C f = 16.8 μF, and 217