switcheb-capacitor network synthesis...
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Switched-capacitor networksynthesis using leapfrog method
Item Type text; Thesis-Reproduction (electronic)
Authors Leonardi, Suryanto Felix, 1958-
Publisher The University of Arizona.
Rights Copyright © is held by the author. Digital access to this materialis made possible by the University Libraries, University of Arizona.Further transmission, reproduction or presentation (such aspublic display or performance) of protected items is prohibitedexcept with permission of the author.
Download date 11/07/2018 15:17:54
Link to Item http://hdl.handle.net/10150/558107
SWITCHEB-CAPACITOR NETWORK SYNTHESIS USING LEAPFROG METHOD
by
Suryanto Felix Leonard!
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCEWITH A MAJOR IN ELECTRICAL ENGINEERING
In the Graduate College
THE UNIVERSITY OF ARIZONA
1 9 8 9
2
STATEM ENT B Y A U TH O R
This thesis has been submitted in partial fulfillment of requirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the major department or the Dean of the Graduate College when in his or her judgement the proposed use of the material is in the interest of scholarship. In all other instances, however, permission must be obtained from the author.
APPROVAL B Y THESIS DIRECTO R
This thesis has been approved on the date shown below:
Lawrence P. Huelsman Professor of
Electrical and Computer Engineering
3
ACKNOWLEDGEMENTS
This work has been done at the suggestion of Professor Lawrence P. Huels- man, Professor of Electrical Engineering in the Department of Electrical and Computer Engineering at the University of Arizona. I wish to acknowledge my thanks to Professor Huelsman for his enthusiastic encouragement, supportive effort, and the patience he has shown me throughout the preparation of the manuscript.
I would also like to thank Dr. Kenneth W. Martin of the University of California at Los Angeles for discussing some possible solutions to the problems I have encountered in the design. Special thanks also go to Professor Douglas J.
Hamilton of the University of Arizona who has been helpful with suggestions, and
to Profs. Yannis P. Tsividis and Soon C. Fang of Columbia University for supplying the SW ITCAP program.
l am particularly indebted to Mr. James Sterling McGregor for his assistance. The support he has given me is genuinely and most sincerely appreciated.
Last, but not least, I am grateful to Ms. Barbara Jones who arranged for the supply of test equipment, to Mr. Mehran Massoumi who loaned me the breadboards
to start the project, and to Mrs. Susan Kinsey and Mr. Daniel Crowell who
proofread the manuscript.
4
TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS 6
A B STR A C T............................................ ............................................................ .... . 9
CHAPTER 1-INTRODUCTION.................................................... 10
CHAPTER 2-MQS INTEGRATED-CIRCUIT T E C H N O L O G Y ........................13
Section 2.1 MOS Integrated- Circuit Fabrication................................ . . 1 3
Section 2.2 n-channel Enhancement-Mode MOS D evices............................14
Section 2.3 The On and Off Resistance of NMOS Switch . . . . . . 17
Section 2.4 Capacitors in MOS Technology................ ................................19
CHAPTER 3-FIRST ORDER SC INTEGRATORS............................ 21
Section 3.1 SC Simulation of Equivalent R e s is to r ........................................21
Section 3.2 Basic Undamped SC Integrator Building B lo c k s ................... 25
Section 3.3 Stray-Insensitive Undamped Basic SC Integrators.................... 35
Section 3.3.1 Inverting SC I n te g r a to r ............................................................37
Section 3.3.2 Noninverting SC Integrator . .................................................... 42
Section 3.4 Effect of Op Amp Gain Bandwidth on theUndamped SC In tegrators................................ 46
Section 3.4.1 Transfer Function of Continuous Domain
Active-RC I n te g r a to r .................................................... 46
Section 3.4.2 Inverting SC Integrator ........................................ 49
Section 3.4.3 Noninverting SC Integrator............................ 59
Section 3.5 The SC Inverting Damped Integrator . ...................................61
CHAPTER 4-NONOVERLAPPING CLOCKWAVEFORMS GENERATOR . . . . ......................... 67
Section 4.1 Quad MOS S w itc h e s .................................... 68
Section 4.2 Design of Nonoverlapping Clock Waveforms
5
Generator C i r c u i t ........................................................................ 72
Section 4.2.1 Summary of Generator Circuit D esign ............................ . 7 6
CHAPTER 5-SECOND-ORDER SC N E T W O R K S.............................................77
Section 5.1 Second-Order SC Networks .....................................................77
Section 5.1.1 An Inverting Biquad.................................................................78
Section 5.2 The Process o f Obtaining the SC Biquadfrom the Active-RC B iq u a d .................................... 81
Section 5.3 Bilinear Transformation Method ......................................... . 8 6
Section 5.4 Design of Bandpass SC F i l te r s ....................................................88
Section 5.4.1 Geometric Sixth-Order Elliptic Bandpass SC
Filter Design Using Coupled-Biquads . . . .....................90
Section 5.4.2 Process for Obtaining a Block D ia g ra m ............................ 94
Section 5.4.3 An Eighth-Order General Stray-InsensitiveSC Elliptic Bandpass Filter D e s ig n ................................... 103
CHAPTER 6-FIFTH-ORDER SC ELLIPTICLOWPASS FILTER D E S IG N ............................................... 115
Section 6.1 Design of the Fifth-Order Lowpass
Elliptic SC Network F unctions............................................... 115
CHAPTER 7-CONCLUSIONS ................................................................... 132
APPENDIX A-LIST OF SW ITCAP PROGRAMS .............................................. 135
APPENDIX B-COMPONENT SPECIFICATION S..................................... 142
R E FFER E N C E S..................................................................... 150
6
LIST OF ILLUSTRATIONS
Figure Page
2.1 Gross-section of the enhancement-mode NMOS d e v ic e ....................................152.2 Circuit symbols for enhancement mode d e v ic e s ................................................162.3 Circuit symbols for n-channel depletion MOS device . .................................... 17
2.4 Rojv of NMOS with W /L as param eter............................................................ . 1 93.1 Nonoverlapping clock waveforms........................ .... . . . .............................22
3.2 Simulation of equivalent resisto r................ ........................................................233.3 Equivalent of basic SC during <f>i.................................... 24
3.4 Equivalent of basic SC during <f>2 . . . ........................................ 253.5 Miller SC integrator equivalent circuit , ..........................................................26
3.6 Capacitor plate charges.........................................................................................283.7 Charges enclosed by the surface . ............................................................. ... . 293.8(a) SC integrator during clock phase <f>2 . . . . ................................. .... 313.8(b) SC integrator during clock phase <f>\ . . . . . . . . . . . . . . . . 32
3.9 Stray-insensitive SC integrators ........................ 36
3.10 Two-phase clock waveform . . .........................................................................38
3.11(a) SC integrator during clock phase <f>i ................................................. 38
3.11(b) SC integrator during clock phase <J>2 39
3.12 Proper switch phasing of SC in teg rato rs........................ .... 43
3.13(a) SC integrator during clock phase fa ................................................. ... . 443.13(b) SC integrator during clock phase < ^ i ........................ ................................453.14 Continous domain active-RC inverting in teg ra to r............................................47
3.15 Magnitude and Phase plot of the active-RC inverting integrator . . . . 49
3.16 Inverting stray-insensitive SC integrator . . . . . . . . . . . . . . . 50
3.17(a) SC integrator during <2 • • • • • • • • • . . . • • • • • • • • • 513.17(b) SC integrator during clock phase <f>\ . . . ................................. .... . . 5 33.17(c) Equivalent circuit during clock period t= (n -l/2 )+T c . . . . . . . . 55
3.18 Noninverting stray-insensitive SC integrator . ....................... 59
3.18(c) Equivalent circuit during fa, at t= (n -l)T c . . . . . . .........................60
7
3.18(d) Equivalent circuit during <j>i................ ........................................................603.19 Active-RC continous domain damped inverting in te g ra to r ........................ 623.20 SC damped inverting in te g r a to r .....................................................................623.21(a) Equivalent damped integrator during <f>\........................ ........................63
3.21(b) Equivalent circuit during the clock phase <f> 2 ............................................ 64
4.1 Quad 1 MOS DPDT switch ..................................................................................684.2 Quad 1 MOS DPDT switch with terminal 3 is g ro u n d e d ............. 684.3 Quad 1 MOS DPDT switch with terminal 2 is g ro u n d e d ............. 694.4 Quad 2 MOS DPDT sw itch .............................................. 704.5 Quad 2 MOS DPDT switch with terminal 3 is g ro u n d e d .................... .... . 704.6 Quad 2 MOS DPDT switch with terminal 2 is g ro u n d e d ............................ 714.7 Simple basic nonoverlapping clock waveforms generator. . . . . . . . . 724.8 Nonoverlapping clock waveforms circuit................ ................................ ... 734.9 Proposed nonoverlapping clock generator circuit and its waveforms . . . . 74
5.1 Block diagram of the high-Q biquadratic system .............................................79
5.2 Active-RC biquad of Fig. 5 . 1 .............................................................................805.3 SC biquad network of Fig. 5 .2 ........................ ................................................ . 8 25.4 Block diagram of the exact z-domain of SC biquad .........................................83
5.5 Negative SC biquad n e tw o rk .............................................................................87
5.6 Compact form of Fig. 5 .5 .....................................................................................885.7 Unnormalized sixth-order elliptic bandpass re sp o n se .................................... 90
5.8 Unnormalized 3r<z-order elliptic LPP response................................................ 91
5.9 Normalized 3r<i-order elliptic LPP filter............................ ................................92
5.10 Required normalized 3rd elliptic LPP filte r........................................................925.11 Sixth-order bandpass prototype f i l t e r .................................... 94
5.12 Thevenin equivalent of F ig .5 .9 ............................................................................955.13 Block diagram of Fig. 5.11.................................................................................... 96
5.14 Equivalent block diagram of Fig. 5 .1 3 ........................................................ . 965.15 Modified block diagram of Fig. 5.14....................................................................975.16 Block diagram of sixth-order elliptic bandpass f i lte r ........................ 98
5.17 Sixth-order SC elliptic bandpass f i l te r ................................................................99
8
5.18 Hokenek and Moschytz’s version of Fig. 5.17 . . . . . . . . . . . . 1005.18(a) SW ITCAP simulation of Fig. 5.18 . . . . . ................................. . 1015.18(b) Passband attenuation of Fig 5.18(a) . ................................................. 1025.19 Passive eighth-order RLC asymmetric bandpass f i l t e r ............................ 1035.20 Block diagram of SC elliptic bandpass filter ............................................. 104
5.21 Circuit for the first transfer f u n c t io n .............................................................1055.22 Circuit for the second transfer fu n c t io n ................................................... 1065.23 Circuit for the third transfer fu n c tio n ....................................................... 1075.24 Circuit for the fourth transfer function . ............................................... 108
5.25 Circuit for the fifth transfer function ...................... 109
5.26 Circuit for the sixth transfer fu n c tio n ........................................................ 1105.27 Eigth-order general SC elliptic bandpass f i l t e r ........................................ I l l
5.27(a) SWITCAP simulation of Fig. 5.27 ..... ......................................... 1135.27(b) Passband attenuation of Fig. 5.27(a) ............................ 1146.1 Stray-insensitive inverting SC in te g ra to r .................... ................................ 115
6.2 Stray-insensitive noninverting SC integrator.................................................1166.3 SC building block used in leapfrog realizations.............................................1166.4 Fith-order LPP filte r........................................ .... ..................................... .... 1176.5 Leapfrog block diagram of Fig. 6 .4 ..................................................... 118
6.6 7-plane transformation of Fig. 6.4 ................................................................. 118
6.7 Fifth-order SC elliptic lowpass filter . . . . . . . ................................. 1196.8 Hardware realization of the fifth-order SC elliptic lowpass filter . . . . 127
6.9 Simulation of Fig. 6.8 using SWITCAP. .....................................................128
6.10 Passband attenuation of Fig. 6.9 ............................................. .... 1296.11 Laboratory result of Fig. 6.8 (10 d B ) .................... ....................................130
6.12 Laboratory result of Fig. 6.8 (1 dB) . ........................ 1316.13 Passband magnification of Fig. 6.11. .........................................................132
9
A B S T R A C T
This paper consists of a study of switched-capacitor circuits with empha
sis on the design of parasitic-insensitive switched-capacitor filters. Realizations of switched-capacitor bandpass elliptic filters consisting of cascaded biquad networks
are presented. The design of a fifth-order elliptic switched-capacitor lowpass filter is realized with discrete components. To accomplish this realization, a network which generates the required two-phase nonoverlapping clock waveforms is designed and analyzed. A simulation program for switched-capacitor circuit analysis, SWITCAP,
is used to verify the design and performance of the fifth-order switched-capacitor lowpass elliptic filter.
10
CHAPTER 1
INTRODUCTION
Switched-capacitor (SC) network synthesis is a new concept which represents a significant breakthrough in filter theory. SC techniques permit monolithic implementation of high precision filter designs by making use of current Metal-Oxide Semiconductor (MOS) and Large Scale Integrated-Circuit (LSI) technology.
In the past decade, filter designers have taken significant steps towards finding better circuits and design techniques for the development of SC filters [1]-[11]. Although the recent development of high-performance low-cost monolithic operational amplifiers makes active RC filters commercially possible, maintaining a relatively stable and precise time constant of an RC product in standard monolithic
processes is difficult to achieve. One reason for this is that the diffusion process is
not precise. As a result, component values cannot be controlled to achieve the required accuracy. High precision element values require careful trimming techniques, and such techniques are costly. This fact has discouraged widespread development of integrated analog signal processing functions. To get around this problem, some
companies use hybrid circuits. Another reason is that high resistor values require
a large surface area on the chip which reduces the number of devices per wafer.
Analog sampled-data techniques as implemented in SC networks, however, provide
a unique solution to the problems just described. This solution is to simulate the
behavior of resistors by utilizing only capacitors and MOS switches. The operation
of these circuits will be explored in detail in this paper.SC filter realizations, by and large, offer considerable advantages over active-
RC filters in the sense that they can be fully implemented in MOS integrated- circuit technology. It is, on the other hand, rather difficult, if not impossible to
realize economical active-RC filters in monolithic integrated-circuit form. Another advantage of SC circuits is that only an accurate ratio of capacitance values is required which can be easily obtained. The popularity of the SC technology has
11
continously gained momentum in the past decade, and the full impact of this new filter technology is now being realized and utilized by analog filter designers.
This paper presents a detailed treatment of the theory and design of SC filters. A brief review of MOS technology can be found in Chapter 2. The discussions are mainly concentrated on NMOS devices. An important characteristic of switching devices is the on and off resistance of the NMOS device which is reviewed in this chapter.
In Chapter 3 the basic analysis of the first-order SC integrators is explained in detail. The effect of the finite gain and bandwidth of the op-amp in undamped SC integrators is also included. Also treated is the SC inverting damped integrator.
This is of considerable importance in leapfrog network realizations.A suitable design of a nonoverlapping two-phase clock waveform generator
circuit is presented in Chapter 4. Such a design is a major contribution of this paper. The circuit takes into account the turn-on and turn-off time of the MOS analog switches which is of importance in the switching circuits. It can be used for any desired switching time by adjusting an external RC time constant. Another
advantage of this circuit is that it can be used to drive TTL compatible CMOS
analog switches such as the HI-201.
The design of second and higher-order filters is the subject of Chapter 5.
Circuits composed of biquadratic networks are primarily suitable for the implemen
tation of higher even-order filters. They are particularly attractive in the design
of bandpass filters, because they can be structured from second-order networks in cascade. Also presented are designs that are robust to implement and are insensi
tive to stray-capacitanCes [6], [7]-[11]. Though many papers propose different ways
to achieve parasitic-free SC filters, one particular method, which is covered in this
paper, is the realization of parasitic-insensitive SC networks that makes use of the
bilinear z-transformation method to obtain an exact design and analysis.
In Chapter 6 a thorough investigation of the active-ladder synthesis of a
fifth-order SC elliptic lowpass filter is presented. The leapfrog method is used in this design. This method requires the use of both damped and undamped inverting
12
integrators. The inverting damped integrators will normally be used at the beginning and at the end of the circuit. The design presented has been constructed and tested in the laboratory using discrete components. The operation of the circuit was compared with its simulation by SW ITCAP, a simulation program for SC analysis.
In the realizations presented in Chapter 5 and 6, advantage is taken of some of the results of modem filter theory. Specifically, the passive doubly-terminated RLC ladder network prototype, which is known to have low sensitivity to component variations, is used. This low sensitivity property is maintained in active filter network synthesis [12], [13], particularly in the design of higher-order filters. To obtain this minimum sensitivity, the active-ladder synthesis or leapfrog method, originated by Girling and Good [14], is utilized. This method requires repeated use of negative feedback. It is one of the most popular techniques used to simulate the operation of low-sensitivity doubly-terminated lossless ladder networks which is a
major topic in this paper.
13
CHAPTER 2
MOS INTEGRATED-CIRCUIT TECHNOLOGY
Two different types of field-effect transistors (FETs) are used in analog integrated circuits. These are the junction field-effect transistor (JFET) and the extremely high input impedance insulated-gate field-effect transistor (IGFET), more
commonly referred to as simply the metal-oxide semiconductor field-effect transistor or MOSFET. FETs are unipolar transistors, because their operation depends only on a single type of charge carriers, holes or electrons. The primary advantages of the FET are its high element density and low power consumption.
JFETs find their most use in integrated circuits not only as active devices but also as resistors and capacitors. Because the gate-source junction of the JFET is reverse biased, the input signal current is very small; in other words, the input
resistance is very high and little power is required.
However, MOSFETs are becoming increasingly important in the realization of analog integrated circuits. In MOSFETs, the input resistance may be as high as 1015a In recent years, all-MOS processes designed for high-volume digital circuits
have been used to realize analog functions on the same chip with digital functions. Such circuits are cost competitive with the more traditional bipolar integrated cir
cuits and have become an important class of analog integrated circuits.
Section 2.1 MOS Imtegrated-Ciroait Fabrication
Fabrication technologies for MOS integrated circuits span a considerably
wider spectrum of complexity and performance than those of bipolar technology. Most technologies in use at the present time fall into two categories, NMOS and
CMOS. NMOS technology provides two basic types of transistors, enhancement
mode n-channel MOS transistors with threshold voltages greater than 0 V, and depletion-mode n-channel transistors with threshold, voltages less than zero. The
14
latter are used primarily as passive load elements. CMOS technology also provides two basic types of devices, enhancement-mode n-channel and p-channel transistors.
Section 2.2 n-Channel Enhancement-Mode MOS Devices
Our interest in MOS devices is mainly concentrated on the enhancementmode n-channel MOS transistor (NMOS). A cross section of a typical NMOS device is shown in Fig. 2.1. Heavily doped n-type source and drain regions are fabricated
in a p-type substrate (often referred to as the body). A thin layer of silicon dioxide,
S ,0 2, is grown over the substrate material and a conductive gate material (metal or poly crystalline silicon) covers this oxide between source and drain.
G D
m e t a l /p o l y Si
Figure 2.1 Cross-section of the enhancement-mode NMOS device
In MOSFETs, a thin layer of Si02 insulates the gate contact from the chan
nel. The n-channel enhancement-mode NMOS device shown symbolically in Fig.
2.2(a) offers the highest performance. No channel is built into this device. A conducting channel is induced by the electric field established between the gate and the p-type substrate. With no gate voltage, very little current flows through the back-to-back pn-junctions. The device illustrated in Fig. 2.1 shows a significant
15
conduction between source and drain only when an n-type channel exists under the gate. So it is designated as the n-channel device. The term enhancement mode refers to the fact that no conduction occurs for V g s=0, and thus the channel must be enhanced to cause conduction. With a small positive gate voltage, majority carriers in the adjacent p materials are repelled and a depletion layer is formed. As
the gate potential is increased, an inversion layer of mobile electrons is formed at
the surface of the p-type region, which becomes an n-type. The conductivity of the
region has been enhanced, current can now flow between the source and the drain,
and thus the transistor is turned on.
d 6
(a)n-channel MOS (b)p-channel MOS
Figure 2.2 Circuit symbols for enhancement mode devices
The drain current is not proportional to Vbs, however. As the potential at
the drain end of the channel becomes more positive, the effective gate-to-channel potential along with the accompanying electric field are reduced substantially. The
carrier density in the inversion layer is reduced and the current levels off.
Similar p-channel devices using an n-type substrate with a p-type conducting
channel are widely used. Such devices are called enhancement-mode p-channel MOS
transistors (PMOS) shown symbolically in Fig. 2.2(b). The greater mobility of
electrons, however, permits smaller n-type channels and therefore lower capacitances
for the same resistances. Therefore, the NMOS transistor offers faster switching
speed in digital systems. It also has the advantage of higher frequency response in
amplifiers than the p-channel. In addition, the n-channel device is not susceptible
16
to thermal runaway. It operates with less signal distortion, a fact which is highly desirable in audio amplifier circuits. In terms of the size of the device, the MOS device is much smaller than the bipolar device.
Since the substrate of NMOS devices is p-type, and the source and the drain are n-type, the normal current is a flow of electrons from the source, through the channel to the drain, by a drift process. The low positive threshold voltage of NMOS devices permits the use of a 5 V power supply, and thus low power consumption. The manufacturing of the n-channel enhancement device is, however, more complicated than that of the p-channel because the positive charge of the S,02 layer tends to
create an inversion layer with zero gate voltage.
In NMOS technology, an additional device type called a depletion-mode de
vice, shown symbolically in Fig. 2.3, is usually available. It has a conducting channel
implanted between source and drain so that conduction occurs for Vcs = 0. It is
called a depletion-mode device because the gate is usually employed to reduce the
conduction of the built-in channel.The derivation of the transfer characteristics of the enhancement-mode
NMOS device as shown symbolically in Fig. 2.2(a) begins by noting that with
Vgs — 0, the source and drain regions are separated by the back-to-back pn- junctions. These junctions are formed between the n-type source and drain regions and the p-type substrate, resulting in an extremely high resistance (about 1012fi)
between drain and source when the device is off.
1 IdD <>
Figure 2.3 Circuit symbols for n-channel depletion MOS device
17
Section 2.3 The On and Off Resistance of NMOS Switch
Because of many attractive features NMOS devices can offer in analog and digital circuits, particularly in switching circuits, it is necessary to evaluate the most important properties of a NMOS device as a switch. These properties are the on and the off resistance of the NMOS device. To begin with, the drain current I d shown in Fig. 2.2(a), in terms of its channel length modulation parameter A, is defined as follows
k 'Wi d — [2(Vg5 - VT) - VDS]VDS(1 + \V DS) (2.1)
where
k ' = nnCox — (2.2)t 0xand
V ossat = Vgs — Ft (2.3)
where
A =the channel length modulation parameter of the
NMOS device (Volt-1 ).
6'=transconductance parameter of the NMOS device (A m ps/V olts2).
//n=surface mobility of the n-channel(cm2/V olt — sec).
Coz=capacitance per unit area of the gate oxide (Farad/cm 2).
eox=permeability of the gate oxide (Farad/cm).
VdSsat "saturation voltage between drain and source at saturation region.
Vy=threshold voltage of the device.
X=channel length of the device.
W =channel width of the device.
Assuming that the effect of the channel length modulation, A, can be ignored,
then I d of Eqn. (2.1) becomes
18
I d = - g j r [2(Vgs - Vt )Vd s - Vd s] • (2.4)
If 0 < Vd s < (Vbs — Vr) with no offset voltage is assumed, then the large-signal channel resistance between the source and the drain can be seen as
R on1
d lo /d V o s'k 'W
L (Vgs — Vt — Vd s ) (2.5)
Thus, the switch is in the on state when Vgs >V t’. The value of Ron depends on the dimension of the NMOS device on the silicon chip. Typically, Ron is in the
range from 30 to 1 Kfi. It is important that this on resistance is small so that the Ro n C time constant, r , is kept as short as possible. This will become apparent in Chapter 3. A plot of Ron as a function of Vg s /V t for various values of W /L is shown in Fig. 2.4. Here, V d s has been assumed to be at ground potential.
I K <•
100
Figure 2.4 Ron of NMOS switch with W/L as parameter.
When the NMOS switch is OFF, that is when Vg s < Vr, the transistor is always in the saturation region. Under saturation conditions, Eqn. (2.1) becomes
I d = - [Vgs — Vt]2(1 + AFbs); 0 < (Vgs — Vt ) < Vd s (2.6)
19
The off resistance value, R q f f , is given as
° F F d l o / d V D S a a t
Clearly from Eqn. (2.7), when Vq s = Vj1, the off resistance, R q f f , is ideally infinite. Realistically, its value is typically in the range of 1012fi. It is important that this value is large so that there will be a zero transmission in the desired output. As mentioned in Allen and Sinencio [32], the leakage current is an important off parameter. This leakage current is a combination of the subthreshold current, the surface leakage current, and the package leakage current. It is typically in the lOpA
range, and it doubles with an increase of each 10 °C.
Section 2.4 Capacitors In MOS Technology
As a passive component, capacitors play a much more important role in
MOS technology than they do in bipolar technology. Because of the fact that MOS transistors have virtually infinite input resistance, voltages stored on capacitors can
be sensed continously and nondestructively, using MOS amplifiers. As a result, capacitors can be used to perform many functions that are traditionally performed
by resistors in bipolar technology.As mentioned in Gray and Meyer [30], an important aspect of the capacitor
' structure is the parasitic-capacitance associated with each of the capacitor plates.
The largest parasitic-capacitance exists from the bottom plate to the underlying
layer, which could be either the substrate or, in the case of CMOS, a well diffusion
whose terminal is electrically isolated. This bottom-plate stray-capacitance is pro
portional to the bottom-plate area and typically has a value from 10 to 30% of the
capacitor itself.The top-plate parasitic is contributed by the interconnect metallization or
poly-silicon that connects the top plate to the rest of the circuit, plus the parasitic-
capacitance of the transistor to which it is connected. The minimum value that this
k 'W(Yg s — Vt ) (2.7)
20
parasitic can assume is dependent on the type of technology, but it is typically on the order of 5 to 50 fF. Because of the importance of this stray-capacitance in MOS devices, one must take it into account as a design consideration for monolithic MOS SC filter design. This is one of the topics discussed in Chapter 3. A more detailed treatment of SC integrated circuit design considerations can be found in Brodersen, Gray, and Hodges [2], and in Allstot and Black [22].
21
CHAPTER 3
FIRST ORDER SC INTEGRATORS
One approach to designing monolithic SC networks is by the use of integrator circuit blocks. This circuit is widely utilized as the basic element of monolithic SC filters because the synthesis of a desired filter frequency response is relatively straightforward, using basic SC integrators. This can be shown in the analyses
of Sects. 3.1 through 3.5. These analyses will be used as a tool to the SC filter realizations covered in Chapters 5 and 6.
Section 3.1 SC Simulation of Equivalent Resistor
As discussed in Hosticka, Brodersen, and Gray [1], one can replace a resistor with a capacitor and MOS analog switches driven by nonoverlapping two-phase clock waveforms, <1 and <f>2 , respectively odd and even waveforms. It is required
that (f>i and <f>2 have the same clock frequency. Fig. 3.1 shows the waveforms of the
50 % duty cycle nonoverlapping clock waveforms. These waveforms will be used in
the circuit analyses throughout this paper.
4>i5V
high>
low
— —C ------<
>
1
-------- j
<
>
»
— i
-------- O
>
<t>i 5 V
high
-6
O r-
low---- < I
■o
■6
o
■6
Figure 3.1 Nonoverlapping clock waveforms
Because the MOS transistor switches operate at TTL levels, the devices which
are used to generate clocks < i and (j>2 should also be TTLs. For this reason, the
amplitude of (f>i and <f>2 are set to approximately 5V, but should not be less than
22
the threshold voltage of the NMOS transistor, V j’, as discussed in Sect. 2.3. The even and odd period of the clock phase shown in Fig. 3.1 can be defined as the following:
* For an odd clock phase (f>i, it has the following duration:
[(n + i)Tc] < t < [(n + t + 1/2)TC] (3.1)
* For an even clock phase <f>2 , it has the following time period:
[(n + t + 1/2)TC] < t < [(n + i + 1)TC] (3.2)
where i= ...,-2,-1,0,1,2,... corresponds to the i-th clock period. Note that although the width of each waveform is Tc/2 length, one must specify if the end point of the waveform is included.
A basic SC circuit that simulates an equivalent resistor is shown in Figs.
3.2(a) and (b). In Fig. 3.2(a), resistor has been replaced by capacitor Ci, which is switched at the clock frequency fc. Switch Si is driven by the clock <f>i, and switch
S2 is driven by the clock <f>2. When S% is ON ((f>i is high), S2 is OFF (<f>2 is low).
Thus, when Si is closed, S2 will be open, and vice versa, without overlapping.
Si-o- A
4>-i1
C1 —i—
+ 0-
Vi
RivV\A -0+
va
-o —
(a) Basic switched-capacitor (b) Equivalent resistor
Figure 3.2 Simulation of equivalent resistor
To understand how the circuit in Fig. 3.2 operates, observe Fig. 3.3(a)
for its equivalent circuit representation during clock phase 4>i where S2 is an open
23
circuit (o.c.). If the input voltage, Vi, is assumed constant, then the potential of capacitor Ci, vcl, will increase exponentially as indicated in Fig. 3.3(b). For one time constant, r , vci will reach 63 % of its final value, and r is given as
r = R o n \C \. (3.3)
The smaller the Kqni > the shorter r is required for Ci to reach 63 % of its final value. In approximately four time constants, capacitor C% will be charged to the voltage Vi. This is extremely fast relative to the type of signals we normally deal with. For the case of an ideal switch, we can say that the capacitor is instantly charged to the input potential Vj. The charge which flows onto Ci is
qi = CiV\. (3.4)
R o n x o . c .-o—ZV\A— —o o-
VC1
(a) (b)
Figure 3.3 Equivalent of basic SC during (f>i
When S2 is ON, S\ is open, and C\ is discharged through R 0 N2 to potential
V2 as shown in Fig. 3.4. Therefore, the amount of charge on C\ that flows into V2
is
9i = Ci(Vi — V2 ). (3.4a)
If both switches are alternating on and off continuously until a steady-state condition is reached, then the average current flow from V\ to V2 is
iavg = C1(V1 - V 2)(fc) (3.4b)
24
which gives an effective resistance of
(Vi ~ %)l a v g
Therefore, using the charge transfer principle, the equivalent effective SC resistance, has a value of
R \ e f f1
ACiTc_Ci
(3.5)
where Tc is the period of the sampling frequency. Notice that the equivalent resis
tance is a clock frequency dependent element. The type of simulation shown in Fig. 3.2(a) is referred to as the parallel SC realization of a continuous resistor [32]. In parallel SC simulation, Vi and V2 must never be simultaneously coupled.
RoN2
Figure 3.4 Equivalent of basic SC during fa
The silicon area required for the implementation of a large resistance value is
greatly reduced through the use of SC resistors. The area decreases as the realized
resistance value increases. For example, let the required resistance value be
R\ = lOMfZ,
and let the clock frequency be
f c = lOOfc/f z,
25
then by using Eqn. (3.5) we may obtain a capacitor value of
C\ — IpF
which requires an area of about 0.001 m m 2. Compare this to a total chip area of
10-20 mm2 when using passive resistance.
Section 3.2 Basic Undamped SC Integrator Building Blocks
The design of a SC network consists of replacing the integrators in the active RC network by SC integrators. The SC integrator consists of an operational am
plifier, an integrating capacitor C2 , a sampling capacitor C%, and MOS transistor analog switches. The transistors axe driven by nonoverlapping clock signals having the phase of 4>\ and <2, an odd and even phase clocks respectively. The active-RC integrator or Miller integrator and its equivalent SC integrator is shown in Fig. 3.5.
>+v.
(a)Miller integrator circuit (b)Inverting SC integrator
Figure 3.5 Miller SC integrator equivalent circuit
Notice that the integrator of Fig. 3.5(a) has no D C. feedback path, and it is referred to as an undamped inverting integrator. The damped inverting integrator will be
discussed in Sect. 3.5.The steady-state voltage transfer function of the continous domain Miller
integrated circuit of Fig. 3.4(a) is
1sR\C2 ’
(3.6)
26
or it can be written asH( u ) = — r~, (3 .7)
where the bandwidth of the continuous time or active ladder undamped integrator
is defined as follows
WQ1
R i C2'(3 .8)
From Eqns. (3.5) and (3.8), the bandwidth of the discrete domain SC undamped integrator can be obtained as
Wosc
(3.9)
where a higher sampling rate than the analog signal is highly preferable.If / i is denoted as the highest analog signal frequency of the filter, then to
avoid aliasing that is inherent in the impulse invariance design, the clock frequency or the sampling frequency must meet the minimum Nyquist rate of:
fc > 2/i (3 .10)
If the switching time or the clock frequency is much larger than the analog
signal frequencies of interest, then the time sampling of the signal which occurs in this circuit can be ignored in the first-order analysis, and the SC can often be
considered as a direct replacement for a conventional resistance. If, however, the switch rate and the signal frequencies are of the same order, then sampled data techniques are required for analysis. As for any sampled data systems, the input
signal should be baudlimited as directed by the sampling theorem at the rate shown
in Eqn. (3.10).
27
The voltage transfer function of the continous domain undamped inverting integrator of Fig. 3.5(a) can alternatively be expressed as
H (iv) = —r~(l + e)eJ,s (3.11)JUJ
where e is the fractional magnitude error, and 0 is its corresponding phase shift error. Suppose that the fractional magnitude error e is much less than unity, that
is e < < 1, and the phase shift error is far less than 27r, then Eqn. (3.11) can be
approximated to be
% — -7- (1 + e) +[JUWo#w
(3.12)
In order to analyze the circuit of Fig. 3.5(b), the concept of charge con
servation analysis must be clearly understood. Only the capacitor plate in the SC network can store charge. A charge -fq is stored on one of its plates and a charge -q on the other plate as shown in Fig. 3.6. So the net charge on the capacitor is
equal to zero.
+ »
V
tv// 7 T T V
/- - -Vv
+ 9
- 9
Figure 3.6 Capacitor plate charges
Tsividis [34] illustrated this charge conservation by considering the capacitors
shown in Fig. 3.7(a) where va» vb, and vc are defined with arbitrary polarities. The charges on the capacitor plates are shown in Fig. 3.7(b), corresponding to the
28
convention of Fig. 3.6. Suppose that a closed surface is passed between the plates in such a way that it is not crossed by any conductors as shown in Fig. 3.7(b). The total charge enclosed by the surface will be given by
qtotal = [qA + QB ~ qo]- (3.13)
C B = : V B
- ia yg
Figure 3.7 Charges enclosed by the surface
Since resistors, switches, and voltage sources cannot store charge, these elements
can be included in the surface without affecting charge conservation.
Based on the above observation, Allen and Sinencio [32] defined the nodal
charge equations which are determined by the period of clock phase <f>i and fa as
follows:
* For an EVEN clock phase fa:
<z*2(<') = [«£(<) + qp'Hi)]; <' > < (3 .14)
* For an ODD clock phase <f>i:
5L, (*') = [gta(<) + 5?1'*, (<)]; < ' > < (3 . i 5 )
where
t'= tim e reference.
gL(t,)=charge left at particular node at equilibrium.
29
9m (<)=niemory charge from previous period.
9c(i)=contribution or injected charge.
For the SC integrator network of Fig. 3.5(b), if it is to be sampled at the falling
edge of clock phase 4>\, its voltage transfer function is given by:
C1/C2v? 1 (w) cos(u)Tc) - 1 + j sin(wT^)
(3 .16)
This transfer function can be expressed in the following form
= 1V f 1 (w) R(lo) + j X (w)
(3 .17)
where R(u>) and X(u>) are real values, and the Q-factor of the integrator is defined
as follows:
X (uR (u)
From Eqn. (3.18), the Q-factor of Eqn. (3.16) can be seen as
(3 .18)
n = _ sin(fa?Tc)R ( u ) cos((jjT c) — 1
(3 .19)
Comparing Eqn. (3.12) with Eqn. (3.18), the Q-factor of Eqn. (3.12) can be
obtained in terms of its fractional magnitude error e and its phase shift error 8 as
(3.20)
As Martin [6] pointed out, the Q-factor of Eqn. (3.18) is a measure of the phase
shift error between the ideal integrator and the actual integrator. The Q-factor
would ideally be infinite. Otherwise, an excess phase shift may cause undesirable
30
deviations in the filter transfer function. Note that if the clock frequency is increased, when the clock frequency relative to the analog signal frequency increases, it can be seen from Eqn. (3.19) that the Q-factor approaches infinity.
As mentioned in Jacobs, Allstot, Brodersen, and Gray [8], an important difference between the active-RC and SC integrators is that the SC integrator only samples the input signal once each clock cycle. So, there can be a time delay between the input signal and the integrator output of up to one full clock period. This time delay gives an excess phase shift through the integrator which results in Q-enhancement. This Q-enhancement, associated with a direct replacement of SC integrators for conventional active-RC integrators, has a detrimental effect on the transfer function of the state-variable filter or leapfrog filter. If this excessive phase shift happens, the low sensitivity properties of the passive doubly terminated lossless ladder network may be lost. Elimination of this Q-enhancement will be
discussed in the next section.Before leaving this section, a step-by-step procedure involved in the use of
charge conservation analysis to obtain Eqn. (3.16) will be described. This charge
conservation analysis will be used throughout this paper to obtain higher order network voltage transfer functions. First, observe how Fig. 3.5(b) looks during
clock phase period < 2, that is, at t = (n — l /2 )+Tc as shown in Fig.3.8(a), where the superscript + indicates the time just after t= (n — 1/2)TC.
c3
C l d :
Figure 3.8(a)SC integrator during clock phase <f>2
By using Eqn. (3.14) and Fig. 3.1, Fig. 3.8(a) can be analyzed as follows:
* charge left at equilibrium:
<zh(n - l /2 )+Tc] = C2v*2[(n - l /2 )+ Tc] (3.21)
* memory charge from the previous period:
qi' [(n - 1)TC] = C2v p [(n - 1)TC] (3.22)
* injected charge:
qp [(n - 1)TC] = - C ^ f ' [(n - 1)TC], (3.23)
The conservation of charge of Eqn. (3.14) for the clock phase <f>2 is equal to:
C2v p (n - 1/2) = C2v p (n - 1) - C ,v f l (n - 1). (3.24)
Taking the z-transform of Eqn. (3.24),
V /J(z )z -1/2 = V2*, ( z ) z -1 - § - y * 1(z )z -1 (3.25)V2
which is equivalent to
v * ’(z) = V /'(z )z -1/2 - ^ y * 1(z )z -1/ 2, (3.26)
ending the analysis of the circuit during clock phase </>2.During the next clock phase it begins at t = nTc, its equivalent circuit is
shown in Fig. 3.8(b) as follows
c3
Figure 3.8(b)SC integrator during clock phase <£i
32
Again, by using Eqn. (3.15) and Fig. 3.1, the charge conservation analysis yields the following:
* charge left during equilibrium:
q£[nTc] = C2v t 1[nTc]
* memory charge from previous period:
g*[(r> - 3/2)Tc] = C iv? \(n - l/2 )T e]
* the contribution charge is clearly zero:
= 0
(3.27)
(3.28)
(3.29)
which says that:
v p (n ) = v * \ n - \ ( 2 ) ,
and taking the z-transform of Eqn. (3.30) to get
(3.30)
V+'(z) = F2 ( z)z-1/2. (3.31)
By using Eqn. (3.31) into Eqn. (3.26), the following relation may be obtained:
V f '( z ) z xl 2 = V*x{z)z~l l2 - § - y / 1(z )z -1/2C2
(3.32)
rearranging terms in Eqn. (3.32):
V /l (z)[z1/2 - z - 1/2] = - ^ L v * x(z ) z -X/2.(/2
(3.33)
The voltage transfer function from Eqn. (3.33):
33
V * '(z)
z - l / 2
Z 1/2 _ 2- 1/2
, - l
1 — Z-1 (3 .34)
Eqn. (3.34) is called Type I DDI (Direct Discrete Integrator), after Bruton [9]. The
result is a transfer function having a full clock cycle. If z = e^u’Tc is substituted into Eqn. (3.34) and expanded using trigonometric identities:
Cic2
C l
c2
1e > T= - 1
_________ 1_________cos loTc + j sin lvTc — 1
(3 .35)
Eqn. (3.35) is equal to Eqn. (3.16). During the next cycle, Eqn. (3.31) can be used to obtain the following relation
Vf*(z) = V24,1(z)z 1 . (3 .36)
By using Eqn. (3.36) into Eqn. (3.26), the following relation is obtained:
C2v f 2(z) = C2y / 1(z )z" 1/ 2 - C1v f l ( z ) z - 1^ (3 .37)
rearranging terms:
C2F/ 2[1 - z " 1] = - C 1V f l ( z ) z -1f2.
The voltage transfer function of Eqn. (3.38) is
v + 2(z) / C A [ Z - V 2 '
y ^ ( z ) " W [ i - z - i /
(3 .38)
(3 .39)
34
Eqn. (3.39) is called Type ILDI (Lossless Discrete Integrator). This is an important result, first obtained by Bruton [9], in the investigation of digital ladder filters where a discrete-time integrator that has only a half cycle of delay has exactly the same phase shift as a continous-time integrator. On the contrary, the integrator
represented by Eqn. (3.34) has a significant phase shift error. The effect of this error will be examined qualitatively in the analysis of the integrators later in Sect. 3.3.1 where the stray-insensitive undamped SC integrators are explored in detail. This concludes the analysis of the voltage transfer function of the equivalent SC
undamped stray-sensitive inverting Miller integrator.As pointed out by Gregorian, Martin, and Temes [4], the basic inverting SC
integrator described in Fig. 3.5(b) suffers from an important shortcoming in that it is fairly sensitive to the stray capacitances. The performance of this circuit is sensitive to the parasitic capacitance Cp between the upper plate of the grounded capacitor C\ and ground as was discussed in Sect. 2.3. Node 1 is connected to the source or drain diffusions of M O Si and M O S 2 which has an appreciable capacitance to substrate. Moreover, the leads to M O Si, M O S2 , and Ci have parasitic capacitance to the substrate.
In both polySi-polySi capacitors and metal-Si capacitors, a sizeable parasitic
capacitance exists from the bottom plate of the capacitor to the substrate. Typi
cally this capacitance has a value of one-fifth to one-twentieth of the MOS capacitor itself, depending on technology. In addition, because the top plate of the MOS capacitor must be connected to the other circuitry, a small capacitance will exist from
the top plate to the substrate due to the interconnections. The two MOS transistors connected to Ci have a stray capacitance to ground of about O.OlpF each [2].
W ith a typical value for Ci of 0.5 to 2.5 pF [15], this stray capacitance becomes
the major source of capacitor ratio inaccuracies. Since these parasitic capacitances are unavoidable, s wit died- capacitor lay-outs must be designed so that they do not
degrade the performance of the filter. A large capacitor value of Ci must be utilized in order to attain the required accuracy. However, this increased capacitor
value means an increase in the required circuit area of the silicon chip. Improved
35
integrators which are insensitive to the parasitic capacitances and eliminating the Q-enhancement of the integrators are the topics of next section.
Section 3.3 Stray-Insensitive Undamped Basic SC Integrators
The key aspect to the performance of any frequency-selective filter is the accuracy and the reproducibility of the frequency response. For SC filters, they
require a certain level of accuracy in the ratio of the capacitances which can be easily controlled.
Since the switched-capacitor technology was first introduced, filter designers have been trying to produce better design techniques and to improve the effect of the parasitic-free SC filters network synthesis [4]-[8],[19]. The effects of stray-
capacitances can largely be eliminated by making use of the stray-insensitive inte
grator circuits shown in Fig. 3.9 [44].
The integrators of Fig. 3.9 differ by the connections of clocks <f>i and <f>2 - The reason for their insensitivity is that every capacitor terminal is either switched between low-
and virtual ground (having the same potential). The two types of stray-insensitive
integrator configurations described are
(a) Inverting SC integrator (b) Noninverting SC integrator
Figure 3.9 Stray-insensitive SC integrators
impedance nodes (that is ground and op-amp output) or switched between ground
36
1. Noninverting stray-insensitive integrator, first proposed in [1], shown in Fig. 3.9(b).
2. Inverting stray-insensitive integrator [6] for which a patent application has
been filed by Northern Research for the circuit of Figure 3.9(a).The integrators of Fig. 3.9 can be shown to have voltage transfer functions which possess only a half clock cycle delay in the forward path as the following:
# 1/2(2) Vi(z) ( l ) ( f r 1
If z = e^ujTc is substituted into Eqn. (3.40), it can be written as
ffV2(“ ) = H E ) = ± ( § ) ( > ^ )
wTc/2sin(a?Tc/ 2)
(3.40)
(3.41)
Eqn. (3.41) is called Type I Lossless Discrete Integrator. The Q-factor in Eqn.
(3.41) is infinite and independent of the clock frequency. The term between the brackets represents the error in the magnitude of the integrator transfer function
and is typically close to its ideal value of unity.
Furthermore, the integrators of Fig. 3.9 can be shown to have voltage transfer function which have a full clock cycle delay in the forward path. They are given by
Hfull(z)
If z = e ^ Tc is substituted into Eqn. (3.42), then
f f full(u) — Vq(w)%(w)
, / C A / I \ ra>rce - ^ / 2'\C tJ \ ju > T c) [2sin((vTc/2).
(3.42)
(3.43)
Eqn. (3.43) is called Type I Direct Discrete Integrator. Detailed analyses of the
above transfer functions and the operations of the circuit during each clock cycles
will be discussed next.
37
Section 3.3.1. Inverting SC Integrator (Qualitative Analysis)
Assume that an ideal op-amp is used and that the 50% duty cycle two-phase clock waveforms shown in Fig. 3.10 are used.
(n - l)T c n T c ( n + l ) T c
( n - 3 / 2 ) T c ( n - l / 2 ) T c ( n + l / 2 ) T c ( n + 3 /2 )T c
Figure 3.10 Two-phase clock waveform
The circuit of Fig. 3.9(a) can now be analyzed. Shown in Fig. 3.11 is an equivalent circuit corresponding to the clock phase period that is at [(n — 1)TC <
t < (n — 1/2)TC],
c3
Figure 3.11(a) SC Integrator during clock phase ^
Observe that discontinuity of vi(t) occurs from t = (n — 1)TC to t = (n — 1/ 2)“ TC.
Notice that v% is just a virtual ground due to an infinite op-amp gain. The charge
conservation analysis results in the following:
* charge left at node a at equilibrium state qi is:
q£ [(n - 1 /2 )-Tc] = C2v*' [(n - l /2 ) -T c] (3.44)
38
* memory charge from previous period qm is:
9m [(n " 1)+Tc] = C2vp[(n - 1)+TC] (3.45)
* contribution charge or injected charge qc into node a is:
g*1'*’ [(» - 1/2)TC] = 0. (3.46)
And conservation of charge yields:
g f' [(n - l /2 ) -T c] = 9*’ [(n - l ) +r c] + 9* ''* '[(" - 1/2)TC] (3.47)
That isC2vp(n- 1/ 2) - = C2v ^ (n - 1)+,
or
^ ' ( n — 1/2)“ = v p (n — 1) (3.48)
which ends the analysis of the circuit for period clock phase 4>\.Next, observe the integrator during the clock phase period <2, during [(n —
1/ 2)TC < t < nTc]. Its equivalent circuit is shown in Fig. 3.11(b) below:
Figure 3.11(b)SC Integrator during clock phase fa
Again, by charge conservation analysis which begins at t = (n — 1/2)TC , the fol
lowing prevail:
* charge left at equilibrium:
« £ (n - 1/2) = C2v p {n - 1/2) (3.49)
39
* memory charge qm:
9m1 (n - 1) = C2v f1(n - 1) (3.50)
* contribution charge:q f1( n - l ) = - C i v f 1( n - l ) . (3.51)
Again the charge conservation yields:
Civl^ip' 1/ 2) = C'2U 1 (fi — 1) — C\ v^1 (n — 1). (3.52)
Notice that during the clock phase period <f>\ ,the charge on C2 remains unchanged.
Therefore Eqn. (3.52) may be written:
v p (n - 3/2) = v f1 (n - 1), (3.53)
By taking the z-transform of Eqn. (3.53) we obtain
y / 1 ) = Vr/ 2(z)z"1/ 2. (3.54)
Now by taking the z-transform of Eqn. (3.52) and premultiplying it by z1/2,
' C2V+*(z) - C2V ^ { z ) z ~ 1 = - C 1V'>2(z). (3.55)
Then using Eqn. (3.54) in (3.55) results in
- ^_1] = - C 1V f 1( z ) z - 1 . (3.56)
From. Eqn. (3.56), the voltage transfer function is
y / 2(z) /<?, \ / z - i /2Vf l (z) \ c j \ l - z - i )
(3.57)
Eqn. (3.57) is referred to as Type I LDI (Lossless Discrete Integrator) after Bruton
[9]. For z = eja,Tc, Eqn. (3.57) is equal to
40
v ,H “ ) ( c 2) ( e l " T-/2 - e-i-TW 2)
_ ( — __________ :_____l __________________\ C 2J \cosa?Tc/2 + j sinwTc/2 — cosll>Tc/ 2 + j sincvTc/2
- ( ^ ) (iTihTZ^bTs)^ c /2 1
VC2y V i ^ cy [sina;rc/2 j(3.58)
which is that of Eqn. (3.41). This completes the analysis of the undamped inverting
integrator.
Suppose that the output of the SC is sampled at a clock period <f>2, then the transfer function of V^>2(z)/V i 2(z) may be obtained by using relation (3.54) into
(3.55) as follows
^ • ( * > - ( c ' ) ( 1 1 V /% ) \ C 2) \ l - z - ' )
(3.59)
Eqn. (3.59) shows that there is no delay in the forward path between the input
and the output signals. This type of integrator is referred to as Type II DDI
(Direct-Transform Discrete Integrator). If z = e-?u,Tc is substituted into (3.59) and expanded, one can show that
= _ f u,Tc/2 \ w) \ C 2) \ ju T c ) \sina)Tc/ 2 / '
If Eqn. (3.54) is written as the following
vt(*) = Vp(z ) (3 .6 1 )
and substituted into Eqn. (3.56), the voltage transfer function where its output is sampled only during the clock phase <f>i can be obtained. The result is a full clock
cycle transfer function shown as the following
41
v+ 'iz ) _ ( c a r z- 1 1 v f i i z ) . ^ I c J b - z - i J
(3 .62)
Eqn. (3.62) has the same form as Eqn. (3.42), and it is referred to as Type I DDI (Direct Discrete Integrator), also after Bruton [8].
As was mentioned earher, the transfer function of (3.62) having full clock cycle delay in the forward path contributes a significant phase error .To demonstrate this interesting result, we substitute z = e^uTc into Eqn. (3.62) and it is factored so that the term in the parentheses are the deviation from the response of a continous
time integrator given in Eqn. (3.8), and the term in the brackets is the deviation
from that response caused by the sampling process. This equation is
f f (o - )/ C A / 1 \ tjjTce ~ i“TcI2 \ C 2) \ju>Tc) 2 sinu;Tc/2
(3 .63)
The magnitude, error of the integrator bandwidth in Eqn. (3.63) is insignificant. It is equivalent to a small error in the component values. As discussed in Brodersen et
al [2], the most important aspect of this deviation is the delay term. The resulting
excess phase shift will distort the frequency response of the complete filter in a way
which is similar to the effects of having excess phase shift in conventional active- RC filters. Typically, this distortion takes the form of Q-enhancement in which
the response of the filter shows some undesired peaking. If the sample period in
Eqn. (3.63) is decreased, the magnitude of error also decreases. But increasing the
sample rate can be done to reduce the error at the expense of increased capacitor
ratios.The problem of excess phase due to sample data effects can be solved in
three ways as reported by Brodersen et al [2]. The filter can be predistorted so
that the desired response is obtained in the presence of the excess phase shift. The disadvantages of this approach are the increase of component sensitivity and the complication of the filter design that requires transmission zeros in the response.
A second approach is to use a more complex integrator which inherently has less
42
excess phase shift [8]. The third approach and perhaps the simplest approach is one based on earlier work by Bruton [9] on digital integrators. It was shown that the excess phase in the simple digital integrator could be removed by decreasing the delay time through the integrator block by precisely one half clock cycle. In active-RC ladder filters, one can alternatively remove a full unit of delay from every other integrator. As first reported by Jacob et al [8], this can be easily accomplished in SC filters by simply reversing the phase of alternate clocks in the ladder filter.
This clocking technique has been termed lossless digital integrator (LDI) clocking
by Bruton [9]. The proper phasing for the LDI clocking scheme is illustrated in Fig. 3.12 [8] as a two-integrator loop with correct switch phasing in order to minimize the phase errors.
Section 3.3.2 Noninverting SC Integrator (Qualitative Analysis)
The analysis of the noninverting undamped SC integrator is similar to that of
the inverting ones. For the sake of completeness, the analysis of its transfer function
will be elaborated. The behavior of the integrator during clock phase <f>2 can be seen in Fig. 3.13(a). The parasitic capacitances of Cp\ and CP2 in Fig. 3.13(a) can
be seen as:
* CP2 is shorted to ground, so it has no effect in circuit.
* Cpi & Ci will be charged to a potential Vi.
The charge analysis during the clock cycle <£2, (n-3/2)Tc < t< (n -l)T c, can be shown
as follows:
Figure 3.12 Proper switch phasing of SC integrators
43
* charge left on C2 at t = (n — 1) Tc :
q+'[(n - l ) - r c] = C2v$'[(n - l) -% ] (3.64)
* memory charge on C2 at t = (n — 3/2)-l"Tc :
9m [(n - 3/2)+Tc] = C2v*1 [(n - 3/2)+Tc] (3.65)
* clearly, the contribution or injected charge is:
g?2(<) = 0. (3.66)
Ca
Figure 3.13(a) SC integrator during clock phase fa
Thus charge conservation yields
«£’ (<') = g£, m + g?J(<)
or
4= (n - 1)" = (n - 3/2)+ (3.67)
which ends the analysis of the circuit during the clock phase <f>i.The integrator during the clock phase period of <f>i has an equivalent circuit
shown in Fig. 3.13(b). The parasitic capacitor CP2 has no effect since it is grounded,
and Cpi will be connected to a low impedance node of an op-amp so it has also no
44
effect in the circuit (vt- is a virtual ground). The following charges may be written as:
* the charge left on C2 at t = (n — 1)TC is
qt'[(n- 1)TC] = - 1)TC) (3.68)
* the memory charge on C2 at < = (n — 3/2)Tc is
q £ [ ( n - 3/2)Tc] = C2v*3 [(n - 3/2)7,] (3.69)
* the contribution charge is:
qp{{n - 3/2)7,] = +C ,v*3[(n - 3/2)7,]. (3.70)
Note that the polarity of capacitor C\ is inverted during discharging [27].
c.
4>i
Figure 3.13(b) SC integrator during clock phase <f>i
Thus, the total charge is
C2v*'(n - 1) = C2v p {n - 3/2) + C > ? 2(n - 3/2). (3.71)
Taking the z-transform and multiplying by z-1
C2v /'( z ) = C2y / 1(z )z -1/2 + C ,yi* '(z )z -1/2. (3.72)
During <f>2 the charge on C2 remains constant so,
45
vt 2(n — 1) = — 3/2)
or
V ? \z ) = z - xl 2V?l (z).
By simply inserting Eqn. (3.73) into Eqn. (3.72), we can obtain
CaV^COp. - S - 1] = C'1y / 2(z)z- 1/2
thereby its final transfer function is
K f 'W , f C A / ^~1/2 \F / 2(z) X ^ / \ 1 — Z:—1/
which is Type I LDI (Lossless Discrete Integrator) similar to that of Eqn During the next cycle, Eqn. (3.74) can be written as
y / 1^ ) = y / 2(z)z+1/2.
Substituting Eqn. (3.76) into Eqn. (3.72),
C2V^(z) = C2V ^ (z)z - 1 + C1Vf2(z)z-1 2.
Rearranging and collecting terms in Eqn. (3.77),
C2y / a(z)[l - z - 1] = C l v f i ( z ) z - 1.
The voltage transfer function from Eqn. (3.78) is
y / 2(z) + w 2y v - 2 -1 /
(3.73)
(3.74)
(3.75)
(3.44).
(3.76)
(3.77)
(3.78)
(3.79)
46
which is Type I DDI (Direct Discrete Integrator). It is necessary to mention that because the flexibility of reversing capacitors is lost in the series SC equivalent resistor, only inverting realizations preserve Type II DDI [32].
Section 3.4 Effect of Op-Amp Gainbandwidth on theUndamped Stray-Insensitive SC Integrators
In this section, the differential mode gain of the op-amp will be taken into account in the development of the transfer functions of SC integrators. The effect
of the finite gain and bandwidth of the op-amp will be included in the derivation
of their transfer functions. An exact equation of these basic integrators will be
analyzed qualitatively.
Section 3.4.1 Transfer Function of Continous Domain Active-RC Integrator
The active-RC continuous domain undamped inverting integrator shown in Fig. 3.5(a) is redrawn here as Fig. 3.14.
c3
. Figure 3.14 Continous domain active-RC inverting integrator.
The voltage transfer function of the integrator of Fig. 3.14 in terms of its differential
mode gain op-amp was discussed in Huelsman and Allen [17] and it is given as
follows:
47
where
(3 .80)
= E C ’(3 .81)
(3 .82)
G 5 = A 0u;a. (3 .83)
Expanding Eqn. (3.80) then we have the following:
u 0A 0LoaA (s) S2 + (tVo + Wg + U?a A())s + LOaU>o
For the condition where cva < u)0, A(s) is approximated to be:
(3 .84)
A0 ) = S2 + tv0s + 0JaUJo
Its magnitude is
A(jtv)^ WoGB
w(w2 + GB')
(3 .85)
(3 .86)
and its gainbandwidth product is
GB = A0cva. (3 .87)
The corresponding phase shift is
arg[A{juj)] = 7T — tan 1 ( ujGB
2 wAgw
CUB'
48
Several significant observations concerning the phase shift of Eqn. (3.88) are:
(1) A decrease in A 0 results in phase lead.
(2) An increase in ^ results in phase lag.
Since the second term of Eqn. (3.88) is much smaller than is the third, a cancellation is not practical. The Bode plots of the magnitude and phase shift of this integrator are shown in Fig. 3.15. The voltage gain for the frequency range of w and u 0 can be observed as
A(s) Vj(s) S + U>a(3.89)
Arff
u>rc G B 10GB
(a)Magnitude plot. (b)Phase shift plot.
Figure 3.15 Magnitude and Phase plot of the active-RC inverting integrator
For the frequency range of w* < w < GB, the gain is:
(3.90)
Eqn. (3.90) will be used to derive the voltage transfer functions of both inverting
and noninverting stray-insensitive SC integrators in the next section. These transfer
functions have been derived independently by Martin and Sedra [26] and Temes [15].
In Sect. 3.4.2, some details will be highlighted.
M *) =U q A c
sGB
49
Section 3.4.2 Inverting SC Integrator (Qualitative Analysis)
The inverting undamped SC integrator of Fig. 3.9(a) is redrawn here in Fig.
3.16 with the nonoverlapping two phase clock waveforms, <f>i and <2, for easy follow up.
»+va
( n - 3 / 2 ) T c (n —l / 2 ) 7 c ( n + l / 2 ) T c
(n —1)7*0 nTc ( n + l ) T c
(a)Inverting stray-insensitive SC integrator (b)Two phase clock waveform
Figure 3.16 Inverting stray-insensitive SC integrator.
Recall from the voltage gain transfer function of Eqn. (3.90), the gain is
Afs) - ~ uj°a ° -
In the continous time-domain, the Laplace Transform equivalent of Eqn. (3.90) is:
= - u aA 0vi(t)
= - G E v ^ t) (3.91)
From Eqn. (3.91), unless tq(t) contains impulses, V2 (t) is a continous function
of time. Thus, although ui(t) can be discontinous at the switching instants, the
output signal V2(t) will remain continous. Examination of the circuit in Fig. 3.17(a) reveals that vi(t) will be discontinous at the end of <f>\, that is at < = (n — 1/2)TC.
Throughout this section, the derivation of the transfer functions assumes
that the integrator is sampled at the end of the clock fa period. The result from
this derivation is compared to that obtained in Sect. 3.3. The effect of the finite
50
gain and bandwidth of the op-amp is treated, and the effect of the edge of the clock waveform is observed. During clock phase <2, the equivalent integrator circuit is shown in Fig. 3.17(a).
Figure 3.17(a)SC Integrator during <2
If Vi(t) remains constant during clock <f>2 , then by conservation of charge at the end of clock period <%!»2, a t f = nTc, it can be shown that
* the charge left at equilibrium is:
g h (n )T c] = C2u*! [(n)Tc] - C2v*2[(n)Tc] - (3.92)I
* the memory charge from previous period is:
q£ [(n - l /2 ) -T c] = C2v*' [(n - 1/2)~TC] - C2v*' [(n - 1/2)~TC] (3.93)
* the contribution charge or injected charge is:
t? 2[(n - l /2 )+Tc] = - C ,v f 2[(n -1 /2 )+ % ]. (3.94)
Thereby, the charge conservation yields
<?£’ [(»!)%] = q& [(n - 1/2)%] + q*> [(»)%] (3.95)
that is
— C2Vi(n) — CiVi(n) = C2^2( — 1/2) — C,2vi(n —1/2) — Ci vi(n — 1/2)^
51
rearranging and grouping terms
v2(n) - v2(n - 1/2) = t — ^ [vi(n) - Vi(n - 1/2)] (3 .96)
is obtained. Clearly, by differentiating Eqn. (3.96), the following relation is obtained:
dv2(t) _ / 'Cl + C2\ dvi( t) dt \ C2 ) dt
By letting
(3 .97)
(3 .98)
and substituting Eqn. (3.96) into Eqn. (3.91), and taking into account the fact
that a 50% duty cycle clock is used, then the following relation can be obtained:
K dv\ (t) dt
G BTCVl(t) (3 .99)
The differential equation may be written as:
dui(t) ,~ d T + (3 .100)
Clearly Eqn. (3.100) represents a homogeneous first-order differential equation
which can be easily solved as follows:
root
which has a characteristic solution of:
(3 .101)
v,(l) =
and C is just another constant.
(3 .102 )
52
Comparing Eqn. (3.102) with Eqns. (3.96) and (3.97) we see that:
vi(t) = vi(n - 1/2)'
equivalently
C e - ( ^ / ^ / ^ = u i ( n - l / 2 ) +
At (-7^ ) = 0, the result isC = u i ( n - l / 2 ) '
Therefore,
vi(n) = u,(n - l / 2)+e_(GB/,1')(7’';/2)
Finally, by substituting Eqn. (3.106) into Eqn. (3.96),
^2(71) = i?2(n — 1/2) — K v ifa — 1/2)+ 1 _ e- ^ ( T c/ 2)
which ends the derivation of the circuit during clock phase fa.During the next clock phase period of <1, that is during [(n
(n — 1/2)TC], its equivalent circuit is as the following:
c3
Figure 3.17(b) SC Integrator during clock phase <1
(3.103)
(3.104)
(3.105)
(3.106)
(3.107)
l)Tc < t <
53
From Fig. 3.17(b), it is clearly seen that the contribution charge from C\ is zero during <f>\ and <j>2 , i.e., = 0. The analysis starts at the clock period justbefore t — {n — 1/2)TC, that is at the end of clock phase <f>i, and it can be denoted as at < = (n — l /2 ) - Tc.
By charge conservation analysis, the following are obtained:
* charge left at equilibrium:
qpK n - 1 /2 ) T C] = C2v2[(n - 1/2)"TC] - C2ui[(n - l /2 ) -T c] (3 .108)
* memory charge:
9m [(n ~ l)^c3 = ^ ^ [ ( n — 1)TC] — C2ui[(n — 1)TC] (3.109)
* contribution charge or injected charge:
q t1’**® = 0. (3.110)
Therefore,
that is equal to
g h ( " - l / 2) -T J = g<?[(n - 1)TC] + g»*-*=(l) (3.111)
v2(n - 1/ 2) - - v ^ n - 1/ 2)- v2(n — 1) — vi(n — 1) (3.112)
rearranging and grouping equal terms
v2(zi — 1/2) — u2(n — 1) = t>i(n — 1/2) — vi(n — 1) (3.113)
Differentiating (3.113) to obtain
dv2 (t) _ dv\(t) dt dt
(3.114)
Then substituting Eqn. (3.114) into (3.91) and talcing into account of the 50% duty- cycle clock, the following relation may be obtained
~ dt~~ ~ ~ G B (y~ 2 ^ Vl^ (3.115)
Rearranging to get a first-order homogeneous differential equation:
+ GB ( y ) Wi (*) = 0 (3.116)
Solving Eqn. (3.116) we obtain:
vi(t) = Ce"GS(Tc/2) (3.117)
54
Comparing Eqn. (3.117) with Eqns. (3.116) and (3.113) we find the following relations
v i ( n - l / 2 ) ™ = u1( n - l ) (3.118)
and at f = (n — 1/ 2) Tc,
vi(*) = ui(n — 1) (3.119)
At GB=0,
Vi (n — 1) — C (3.120)
Therefore,
^ - 1 / 2 ) “ = u i(r a - l ) e ~ GB(r<=/2) (3.121)
By substituting Eqn. (3.121) into Eqn. (3.113)
V2(n — 1/ 2) = i>2(ra — 1) — vi(n — 1) 1 _ eGB(n/2) (3.122)
55
ending our analysis of the circuit during the clock phase < i.As mentioned above, the analysis is based on when the clock pulse is at
t = (n — l /2 ) - Tc, that is just prior to entering clock phase fa. We now would like to see what takes place at the switching instant during the period of £ = (n — l / 2)+Tc. First, noting that at £ = (n — l /2 )+Tc, capacitor Ci is connected to the inverting input terminal of the op-amp. The charge on Ci is now instantaneously distributed
between capacitors Ci and C2 according to Fig. 3.17(c).
' o
: C ,
sJ v 1( n - l / 2 ) -
Figure 3.17(c)Equivalent circuit during clock period < = (n — l /2 )+Tc.
Analysis by using the superposition principle reveals
V I (r. - 1/2)+ = ( p ^ y v,(n - 1 /2 )- + ( C l " 1 / 2 ) . (3.123)
Next by using Eqns. (3.121), (3.122), and (3.123) into Eqn. (3.107) we obtain the
following
1/2 (71) = V2 (n — 1) — Vi(n — 1/2) 1 — e i^ ’(Tc/2 )| —
1 _ e Tc / 2 ( G B / K + G B )t/i(n - 1)
Also by using Eqns. (3.121) and (3.122) into Eqn. (3.107), can get
(3.124)
g—Tc/2(GB/K+GB)j _j_
56
— G B T re 2 ii (3.125)
which ends the analysis during clock period t=(n-l/2)"*"Tc.The derivation of the final transfer function of the SC inverting integrator
can now be shown. The input voltage, has been defined previously, duringclock phase fa , to be constant throughout this clock period. Therefore one can
substituteVi{n — 1/2) = u,(n) (3.126)
into Eqns. (3.124) and (3.125) and take the z-transform of it to solve for the voltage
transfer function V2(z)/V,(z). First, define two constants as follows
and
(3.127)
(3.128)
From Eqn. (3.124), we can write
V2(z) = V2(z)z 1 - ^ £ r^ V i(z )(l - , —&1)- y i(z)z-1 . (3.129)
It can be written as
v,(z) = j f a r r [ ( § ) ( l - e-*')%(z) + (l - e_ fcl+&* )V,{z)z~l (3.130)
Similarly, from Eqn. (3.125),
57
ViOO ' { c r k y ^ .(3.131)
Substituting Eqn. (3.131) into Eqn. (3.130), the following equation results
V2(z) - 11 — z-1
(1_( c ,+ 'c j ) e klVi(z)i
-(&14-&2)Y-1
1 (c i+ C j) g— 1.
Solving for the transfer function
T^(z) —1Vi(z) ~ 1 - z - i (8)
1 A - - W
e~klz~ x
e - ( ik i+ & 2) .
(3.132)
(3.133)
Rearranging and regrouping Eqn. (3.133)
(3.134)
Finally the complete voltage transfer function of the inverting SC integrator in
terms of the effect of the gainbandwidth of the op-amp is shown as the following
58
V ;MVi(z)
C2C\ + C2
+
\ — e—(*1+^2)(3.135)
Since normally e (&1+&2) < < 1, the second-order error terms may be ignored. Thus, Eqn. (3.135) is simplified to
1 - e~kl +C2 \+ c2) (3.136)
By letting z — e ^ Tc in Eqn. (3.136) above, the result is:
V iH “® ) (gJwTc/2 \
1 + e'+ C22j sin w Tc/ 2 J
(coSu,Tc - l - ( ^ ^ ) , Sinu,Tc) (3.137)
Notice that as the term k\ in Eqn. (3.127) approaches a large value, which is in most cases, then Eqn. (3.137) can further be approximated to be
%(w) \ C 2) \ 2 j s m u T c/ 2 j(3.138)
which is exactly that of Eqn. (3.61) of Sect. 3.3. However, if one would begin the analysis of the transfer function with the assumption that the integrator is sampled at the end of clock period <j>i, then the result will be that of Eqn. (3.41) of Sect. 3.3 that is
( CA ( 1 V &Tc/2 \Vi(u) \ C 2J \ j u , T j \smwTc/ 2 j (3.139)
59
which is the equation of Type I LDL Eqn. (3.139) will be used throughout this paper.
Section 3.4.3 Noninverting SC Integrator (Qualitative Analysis)
The noninverting undamped SC integrator of Fig. 3.9(b) is redrawn in Fig. 3.18 with two-phase clock waveforms, <f>i and <2, for easy follow up.
c2
vi <P\ e-|
c1 C» ------- 9<f)2 <t>l
--------<f>2
►4>\
-------£<t>2
1( n —3 /2 )T c ( n - l / 2 ) T c ( n + l / 2 ) T c
( n - l ) T c n T c ( n + l ) T e
(a)Noninverting SC integrator (b)Two-phase clock waveform
Figure 3.18 Noninverting stray-insensitive SC integrator
Again, assume that the output of the integrator is sampled at the end of clock period (f>2 and the 50% duty cycle clock waveforms are used. A similar derivation to that used in the analysis for the inverting integrator can be performed. Its equivalent circuit during the clock period <f>2 is shown in Fig. 3.18(c).
c3
Figure 3.18(c) Equivalent circuit during <2, at < = (n — 1)TC
60
Observe that the discontinuity in ui(t) occurs at < = (n — l ) r c, that is during the clock period fa. Capacitor C\ will now be charged to potentiM V\. Next, the equivalent circuit during clock period (f>i is shown in Fig. 3.18(d).
c.
Figure 3.18(d)Equivalent circuit during (f>i
Note that during the clock period <f>i, the voltage across C\ is applied to
the inverting input of the op-amp having finite gain and bandwidth. As derived in Martin and Sedra [26], the voltage transfer function of this noninverting SC integrator, if its output is sampled at the end of clock period of fa [at t = (n —1)“ TC],
is given by:
Vi(z)
c2C\ 4* C2 )
g—(&1+&2)1 +1 -
(3.140)
In the normal case where e *2 < < 1, Eqn. (3.140) can be expressed as
M i )Vi(z)
= + (8 ) ( r W (3.141)
61
By letting z — e*wTc into Eqn. (3.141),
Vi(u>) \ C 2J \ 2j sinwTc/ 2/ [ + C2 J (3.142)
may be obtained. Again, notice that as the term k\ approaches infinity, which is in most cases, Eqn. (3.142) can be further reduced to be
k , ( C i \ ( e- ^ / 2 \Vi(u>) V2isinwTc/ 2 ;
(3.143)
which is exactly that of Eqn. (3.43) or Eqn. (3.62) with the sign being positive. Notice that Eqn. (3.143) contributes to a significant phase shift error as discussed
previously.
Should one begin the analysis of the transfer function with the assumption
that the integrator output is sampled at the end of clock period <f>i, the result of
the transfer function will be that of Eqn. (3.45) of Sect. 3.3, that is
V iM \ C 2J \ j u T c) \sino?Tc/2 y(3.144)
Eqn. (3.144) is the equation that will be used throughout this paper.
Thus, complete derivation of the parasitic-insensitive SC integrator has been
shown in this section. The effect of the finite op-amp gain and bandwidth has
been treated. Temes [15] pointed out that the analysis being presented so far has not yet taken into account the effects of the slew rate and the settling time of the
amplifier. Often these, and not the finite-gain bandwidth product, represent the ultimate limitation on the highest achievable switching rate.
Section X§> The SC Inverting Damped Integrator
Another useful type of integrator in the leapfrog network realization is the
inverting SC damped integrator. The voltage transfer function of this integrator
62
will be derived in this section. The analysis begins with the active-RC continuous domain damped inverting integrator as shown in Fig. 3.19. As quoted in Huelsman and Allen [17], the term undamped corresponds to the pole location at the origin of the s-plane, and the term damped corresponds to the fact that the pole location is shifted from the origin in the s-plane.
*3
Figure 3.19 Active-RC continous domain damped inverting integrator
The integrator shown in Fig. 3.19 posseses the following transfer function
R ^/R l1 + jw Rs C2
The equivalent SC network of Fig. 3.19 is shown in Fig. 3.20 as follows
(3.145)
d»3 <P2
(a) W ith unshared switches (b) Simplified network
Figure 3.20 SC damped inverting integrator
63
In Fig. 3.20(a), the SC damped integrator with unshared switches is shown. The switched-capacitor elements are a direct replacement of the resistors in the active-RC damped integrator. In Fig. 3.20(b), a simplified circuit of Fig. 3.20(a) is shown. Some of the switches have been shared. Both circuits have equal response. The analysis of Fig. 3.20(b) can now be done.
The analysis starts by observing the equivalent circuit in Fig. 3.20(b) during
the clock phase period <f>i, that is during [(n — 1)TC < t < (n — 1/2)TC], as shown in
Fig. 3.21(a).
c3
Figure 3.21(a) Equivalent damped integrator during (f>i.
The charge conservation analysis reveals that:
* the charge left at equilibrium state is:
q$'{(n - l /2 ) - T c) = C2v*'[(n - 1 /2)-% ] (3.146)
* the memory charge from the previous period is:
«£[(n - l)Te] = C2v h ( n - 1)%] (3.147)
* the contribution or injected charge is:
?£''*’(«) = 0 (3.148)
which yields the following relation:
64
v% \n - 1/ 2) = v p (n - 1)
having the z-transform of
V/'(2) = V*l{z)z'l2
which ends the analysis of the circuit during the clock phase period of <f)\
During the next clock phase period <2, that is during period of [(n — t < nTc], its equivalent circuit is shown in Fig. 3.21(b).
c.
Figure 3.21(b) Equivalent circuit during the clock phase <2-
The charge conservation analysis gives the following:
* the charge remained at equilibrium state is
q t’ Kn - 1/2)T«] = (C2 + C z)vt% n - 1/2)TC]
* the memory charge from previous period is
qt[(n - l)T c l = Czvi[(n - 1)TC]
* the contribution charge or injected charge is
- l/2)Tc] = - l / 2) r c]
(3.149)
(3.150)
1/2)TC <
(3.151)
(3.152)
(3.153)
then the charge conservation analysis yields
65
(C^ + Cz )v2 ^(ji — 1/2) — C2 V2 1 (.n — 1) — Civ^2(n — 1/2) ■<f>2 I (3 .154)
Taking the z-transform of Eqn. (3.154),
(C2 + C3)V24,2(z)z- 1/ 2 = C2V ^ t ( z ) z - 1 - C1V f 2( z ) z - 1 2 (3 .155)
Rearranging Eqn. (3.155) to give
V'/2( z > - 1/2 c 2(C*2 + Cz)
V * ' ( z ) z - ' - Ci(O2 -h Cz)
V f 2( z ) z - 1/2, (3 .156)
Using Eqn. (3.150) into Eqn. (3.156) to get
V } l (z) = irt ^ - Cl n V f 2z~ l f2(C2 + C3 ) (C2 + C3 )
(3 .157)
The result of the transfer function is immediate
V f ‘ ( z )V f ( z )
5 l „ . - l / 2(Cg-j-Gg)
1 C2+C3 f 1Cl
(C2 + C3)z1/2 _ C72z- 1/2 (3 .158)
By substituting z = eJwTc into Eqn. (3.158),
v f ' MV?’(w)
c,(C2 + C/s ) [cos l?Tc/2 + J sin ujTc /2] — 6 2 [cos /2 — j sin tvT^/2]
C2 %j sin tvTc/2 + C3 [cos ujTc/2 + j sin tv2^/2]
- ® ) j"2 sinwTc/2 + (•^ ) [coswTc/2 + j sin wTlc/2](3 .159)
66
which ends the analysis for the SC inverting damped integrator. This type of integrator will be widely used in the leapfrog network synthesis, particularly for the first and the last circuit blocks. Chapter 5 and 6 will cover its use.
67
CHAPTER 4
NONOVERLAPPING CLOCK WAVEFORMS GENERATOR
Some important properties of the NMOS transistor as a switch have been discussed in Sect. 2.3. To prepare for the hardware realization, reliable MOS analog
switches which have relatively low on-resistance, fast switching time, and low power dissipation are needed. TTL compatible switches are highly desirable, particularly with the use of TTL compatible circuits.
The MOS analog switches such as those of MC14066B or CD4016BC are inexpensive, and they are largely available in the current market. The problem
with this type of switch is that it has high on-resistance value, about 300 0 at 15 V
power supply (refer to Appendix B). Another factor is that this switch is not TTL
compatible.The high quality HI-201 quad analog QMOS switches from HARRIS Cor
poration meet the specifications for hardware realization. They posses attractive
features of having low on-resistance (550), fast tum-on time (185ns), low power
dissipation (15mW), low crosstalk among switches, and most importantly they are
TTL/C M O S compatible. They also operate with ±15V power supply which coin
cide with the choice of an operational amplifier type LF356N (See Appendix B for
detail specifications).A brief discussion of the applications of quad MOS analog switches in terms
of how the switches should be connected in the circuit will be presented in Sect.
4.1. Different ways of representing the switches as to what they do in this particular
configuration will be examined.
The design of a nonoverlapping clock waveform generator circuit suitable for TTL circuits will be realized in Sect. 4.2. The use of this waveform generator circuit is highly desirable because it can be operated at any clock frequency by adjusting an external RC time constant. This circuit will be used later in the actual circuit
realizations in Chapter 6.
68
Section 4.1 Quad MOS Switches
The choice for using quad MOS switches is practical in the stray-insensitive SC circuit realizations. The quad MOS switches can be used as a double-pole double-throw (DPDT) switch. Assuming that the MOS switches are driven by the nonoverlapping two-phase clock waveforms, there are several different ways in which these switches can be connected.
1 O-
3A A o 3
= Ci
2 ȴ
2¥4>i
■o 4
1 O
2 o
■o 3
■o 4
(a) MOS DPDT switch connection (b)Conventional notation
Figure 4.1 Quad 1 MOS DPDT switch
The MOS DPDT switch connection shown in Fig. 4.1 can be used in two applica
tions. These applications are
[i] First, set terminal 3 to ground potential. The connection is shown in Fig.
4.2.
v3
(a)MOS DPDT switch (b)Convention of (a) (c)Equivalent of (a)
Figure 4.2 Quad 1 MOS DPDT switch with terminal 3 is grounded
69
Observe that prior to the closure of the switches that are driven by the clock phase < i, capacitor Ci is charged to a potential given by
vci = Vi — V2 . (4.1)
After the closure of the switches, the output voltage uq is the opposite sign of Eqn.
(4.1), that is
vq = —vci = v2 — vi (4.2)
which is performing the differential mode.
[ii] Next, if terminal 2 is set to ground potential, then the output voltage, u0, can be observed from its equivalent circuit shown in Fig. 4.3.
*1
1 y f 3
*3 4>i
1 JL c i 4
VlC l i v c i
1 1 ♦ 11. ? °Vl J "Cl 1
C i =r " c i
r* 1H L J h »
4 h
<t>2Y 44>i
2_[— > \ 9 r + ? T
(a)MOS DPDT switch (b)Convention of (a) (c)Equivalent of (a)
Figure 4.3 Quad 1 MOS DPDT switch with terminal 2 is grounded
The switches driven by clock phase <2 are now in position. The potential on Ci is
vci = th (4.3)
When the switches driven by the clock phase <f>i are taken place, the output voltage
is equal to
Vq = —Vci = —Vl (4.4)
70
which is performing the inverting mode. The term “inverting” does not correspond to an inverting integrator output. In fact, the connection to the inverting input of the op-amp will produce a non-inverting integrator having a positive voltage gain.
Another quad MOS DPDT switch connections differ by the connections of
< i and (f>2 is shown in Fig. 4.4
4>1
*1 <h
(a)MOS DPDT switch (b)Conventional notation
Figure 4.4 Quad 2 MOS DPDT switch
The configuration of Fig. 4.4 also has two useful applications. They can be observed
as the following:
[i] Let set terminal 3 to ground potential. Let the output terminal be that of terminal 2. The equivalent configuration is shown is Fig. 4.5.
<t>2 4>\A 3 1 / 3
4>2. / A . ^
Cii : t/d4
». ' Y " 4C l ± vciL " i
4>iV y«4>2
2 Vo2*V?
(a)MOS DPDT switch (b)Convention of (a) (c)Equivalent of (a)
Figure 4.5 Quad 2 MOS DPDT switch with terminal 3 is grounded
71
When the switches driven by clock phase fa are in position shown in Fig. 4.5(a), the voltage of Ci is
vci = Vi — V2. (4.5)
After the closure of the switches that are being driven by the clock phase < i, the
output voltage is equal to
Vq = v2 — Vi. (4.6)
[ii] Next, terminal 2 is set to ground potential. Observe the potential at terminal
4. The set up is shown if Fig. 4.6.
(a)MOS DPDT switch (b)Convention of (a) (c)equivalent of (a)
Figure 4.6 Quad 2 MOS DPDT switch with terminal 2 is grounded
After the closure of the switches driven by clock phase ^ i, a discontinuity occurs
at the output, thus
v2 = 0. (4.7)
On the other hand, before the closure of the switches stated above, capacitor 0%
has a potential of
vci = Vi — t>2-
If the capacitor is initially uncharged, vci = 0, then
(4.8)
72
t>2 = Ul
which says that the output voltage is a noninverting copy of the input voltage. Again, the term noninverting does not correspond to the output of the noninverting
integrator. Its connection with the inverting input of the operational amplifier results in an inverting integrator having a negative voltage gain. Throughout this paper, the conventional way of representing a switch will not be used, but rather the full figure of the switches itself will be drawn just as in Figs. 4.2(a) or
4.2(c) above.
Section 4.2 Design of Nonoverlapping Clock Waveforms Generator Circuit
In order to execute the hardware realization, one must design the nonoverlapping two-phase clock waveform generator. A simple basic circuit for the generation of such waveforms is shown in Fig. 4.7.
Figure 4.7 Simple basic nonoverlapping clock waveforms generator
The disadvantage of this circuit is the fact that it can only be used for ideal MOS
switches having very fast turn-on and turn-off time. In practice, this is unrealistic.
Since the turn-on and turn-off time of the MOS switch remains the same regardless
the variation of the clock frequency, the use of this particular circuit is limited only
to the particular fixed frequency.
73
Allen and Sinencio [32] showed different circuits for generating the two-phase nonoverlapping clock waveforms. One of these circuits is shown in Fig. 4.8. Although the circuit of Fig. 4.8 is more acceptable than that of Fig. 4.7, the disadvantage of this circuit is that it has a fixed time constant in order to maintain a constant duty cycle. If the main clock frequency of the square wave is varied, this circuit is not useful. Because of its inflexibility to clock frequency variations, this
circuit is not desirable for general use.
_n_n_-i
—1:: :
Q Q Q Qi i i i4>i & &
Figure 4.8 Nonoverlapping clock waveforms circuit.
The proposed design of the nonoverlapping two-phase clock waveforms generator is shown in Fig. 4.9. The tum-on and turn-off time of the switches have
been included. This circuit design has not been included or discussed. It will be
explained in detail next.The discussion of the circuit shown in Fig. 4.9 begins by first recognizing
that the MOS analog switches driven by clock phase <f>\ and fa should never turn
on at the same time. At the same time, the MOS switches should be operated at
TTL levels so the devices generating both <j>i and <2 must be TTLs. Somehow the
incoming clock rate must be used with a delay applied to insure that the switches
are completely turned off before the next clock phase comes on. Since the turn-off
time is longer than the turn-on time, one has to make sure that the switch is turned off entirely. To do this, a sufficient time must be given for the switch to turn off. The maximum turn-off time of the HI-201 is about 500 nsec (see Appendix B); thus,
a pulse having a minimal width of approximately 550 nsec must be produced.
74
J U T -T L
7 4 L S 2 2 1 N
7 4 L S 2 2 1 NC L K
C L K
high
SV
low
4>iH
5 V ------
L
Figure 4.9 Proposed nonoverlapping clock waveforms circuit
75
To insure that the switch is off completely, a pulse of 700 nsec is used. However, will this disrupt the performance of the switches given a delay pulse of 750 nsec? The answer depends on the clock frequency. If, for example, a 5kHz clock frequency is used, then a delay of 700 nsec is small compared to the period of
the clock of 200 //sec. The delay period is, in this particular case, relatively small compared to the period of the incoming signal that we are looking at. If the highest analog frequency of the filter is at 2 kHz, the maximum pulse delay that can be used with 5 kHz incoming clock frequency will be 50 //sec. Therefore the lower the analog frequency of the filter, the less problem it is.
Regardless what the clock rate is, the turn off time of the switches remains unchanged. Therefore the delay that is being generated would be independent of
the clock rate variation.W hat we need are versatile devices to generate clock phase <j>i and <f>2 and to
perform the required delay. Referring to Fig. 4.9, there are actually three different
level controls for the monostable vibrator (JC ia and IC \b )- One may trigger the one shot with a positive going waveform. Similarly, by the modification of three input modes, the one shot can be triggered on the negative going pulse as desired.
Notice that the IC ia (one shot) triggers on the positive input clock. Then
the fall of IC ia will be used to toggle IC 2A (JK FF) which generates clock phase
<j>\. As the master clock triggers IC i a , when it falls it triggers clock phaseThe clock phase <f>i now remains on until the master clock goes negative.
When it goes negative, it resets IC 2A (JK FF). Though IC 2A is reset, a delay of a few nanoseconds will occur. Soon after that, there will be a long turn off time of
the switches which is about 500 nsec. At the instant the master clock goes negative,
we also trigger TC\b (one shot) off the negative-edge of the clock which generates
another pulse delay. At the end of the pulse, the IC \b triggers IC 2B (JK FF) and
IC 2B produces clock phase fa which will stay on until the next time the clock goes
positive and IC ia (one shot) is triggered. The Q of IC ia then comes over and resets fCgg. Again, there is an insignificant delay (about 2 nsec). And thus the
process is repeated.
76
Section 4.2.1 Summary of Generator Circuit Design
(1) Determine the input clock master frequency to be used in the circuit.
(2) On the rising edge of the master clock, we remove the reset from IC 2A and at the same time we apply a positive trigger to IC ia which causes IC \a to produce a pulse width whose width is determined by the external RC time
constant. (The formula is obtained from the manufacturer specifications)
(3) When IC \a fires, we get a positive going pulse of about 700 nsec on the output pin for Q. The negative going pulse of equal duration is on Q.
(4) The positive pulse now goes to IC 2A that is used to clock that JK flip- flop and the clock is now set. Since the IC 2A is a negative-edged triggered flip-flop, it turns on on the falling edge of IC ia and the clock phase is generated.
(5) When the clock goes negative, we apply a negative voltage to the reset pin
which resets IC 2A and <j>\ is turned off. At the same time, IC \b has received a trigger on its negative-edged input and it fires. And IC ib drives input to
IC 2B and just on the safe side, the J of IC 2B is connected to the Q of IC 2A because IC 2A must be set before IC 2B can reset and generate clock phase
<f>2. It is used just to insure that the clock phases <1 and <f>2 do not come on
at the same time.
(6) The pulse period of IC ib is controlled by the external RC time constant which should be close to that of the time constant of IC ia of about 700
nsec.
(7) Notice the difference in the reset between IC 2A and IC 2B- The reset of IC 2A comes from the master clock itself while the reset of IC 2B comes from the Q
of the IC 2A-
r
77
CHAPTER 5
SECOND AND HIGHER-ORDER SC NETWORKS
The analyses of first-order integrators have been given in Chapter 3. In
this chapter, higher-order networks will be examined, particularly the bandpass
filter realizations that consist of second-order SC building blocks. Two methods for obtaining the second-order SC building blocks will be the topic of discussions. These methods are presented in Gregorian, Martin, and Temes [4] and in Martin
and Sedra [7].
Section 5.1 Second-Order SC Networks
A second-order continous domain active-RC and its equivalent SC network will be covered in this section. This second-order network is commonly referred to as biquadratic network (biquad). The general form for the continous domain
biquad voltage transfer function is:
V 2 ( s ) ___fl2g2 a l s ftpVi(s) b2s2 + Zqs + b0
It can be denoted as
(5.1)
ViM+ (% •)*+ ‘4
s2 + (%;)* + “}(5.2)
where:
k is a constant,
u>z and u>p are the zero and the pole undamped frequencies,
Qz and Qp are the Q’s of the complex zeroes and poles.
Thus, the transfer functions for the lowpass, highpass, and bandpass filters can
be obtained from Eqn. (5.2). Further discussions and various realizations for the
78
continuous domain active-RC biquad network functions can be found in Huelsman and Allen [17].
Because an inverting biquad is mostly used in the realization of the leapfrog
circuit, we shall focus our attention on the inverting biquad only. The biquadratic filter functions, however, can be designed for use in low-Q (Q<1) and high-Q (Q >>1) transfer functions. The realization of a high-Q transfer function is the main topic of this section. The transfer function of the biquad in the z-domain is
%(z)' % (;)
By using the following approximation
#2* 4" #lZ d" Uq
Z>222 + b\z + 1(5.3)
z = esT 2*1 + sT,
in Eqn. (5.3), the following relation is obtained:
^ ( s ) ( 25 + d\S + doK W = _ [ ^ + ( ^ + ^ 2
If the pole is sp = <jp + j u p, then
(5.4)
(5.5)
Wo \sp \ = \ / ai + (5.6)
Q - 2|4l “ 2>/1 + ^ / <7 2-
The block diagram of a continuous-time system consists of two cascaded integrators
and coupling branches can now be constructed by expanding Eqn. (5.5) as follows:
s21/2(s) = —[dz^2 + d\s + do] Vi (s) — V2(s) (5.8)
79
Dividing both sides of Eqn. (5.8) by s2 and collecting terms:
{d ' + d 2S)Vl(s) - ^ - v 2(s ) -s Qs s* s*
—d2Vi(s) — f - jV i(s ) H— - ^ ( s ) ----- 1\ S S ^2 / T + - ” ^ ( s )
—d2V i ( s ) ---- - (d0 + dis)Vi(s) — ^ ( s )
^ V ^s) — + wo^ ^ ( s )do dis (5.9)
As one can see, Eqn. (5.9) is arranged so that all elements are a function of wg. If
V’l is set to be:
do + d\^ V ^s) + + wo^l^(s) (5.10),
then
^2 (-5) = - ~ d2(s) — woVi(s) (5.11)
Fig. 5.1 shows the system block diagram of Eqn. (5.9) for a high-Q continous-
domain biquad network realization.
W o
Figure 5.1 Block diagram of the high-Q biquadratic system
80
From this figure the equivalent continous domain active-RC hi quad circuit is obtained and shown in Fig. 5.2.
Figure 5.2 Active-RC biquad of Fig. 5.1
The process for obtaining the block diagram, as suggested by Gregorian et al [4], is not unique. There are many other ways one can achieve this block diagram. The
state variable of the system block diagram of Fig. 5.1 can be analyzed by first
defining the following parameters:
y = V2(s) and r = Fi(s)
Then identify the following:
i = r f — + — 1 + yu0 + !/ f 7;^) \wo wo J W /
1 / . \ 1x = — (x) = ----s s
d0 dis----- 1-----Wo Wo
+ y
(5.12)
(5.13)
(5.14)
y = d2sr + x (—ui0)
We can observe that
y = disr + (?)do d\ s z , \ lr -----1------ + yw0 + yl 7: 1wq wo \ Q J
(5.15)
(5 .16)
81
But y = —\ y or y = — j/5, so it can be writen as
{—s)y = d2sr +
Rearranging terms of Eqn. (5.17) to obtain
r [ * + ^ i + ya£ + <£oj
S' m . 5 Q \
y —d2r ----s a, + sWo . WoT + 0
(5.17)
(5.18)
If T^(s) and Vi(s) are substituted back as y and r respectively into Eqn. (5.18),
then
Vi(s) ~d2Vi(s) — (5.19)
which is the form of Eqn. (5.9).
Section 5.2 The Process for Obtaining the SC Biqmad
The SC Biquad network just being discussed can be constructed directly
from the continous time active-RC biquad of Fig. 5.2, as outlined by Gregorian et
al [4], using the following step-by-step procedures:
(i) Expand the transfer function I/2(s)/Vi(s) of the active-RC biquads to obtain
the block diagram of a continuous system containing two cascaded integrators
and coupling branches which are constructed from h2(s)/hi(s). [see Fig. 5.1]
(ii) Next, obtain an equivalent active-RC circuit based on (i). [see Fig. 5.2]
(iii) Each resistor in the active-RC section is then replaced by an equivalent SC
branch containing a capacitor and quad MOS analog switches. The resulting
82
equivalent SC biquad network is shown in Fig. 5.3 below. By (ii) above, the value of the SC Ci replacing the resistor R{ is given by
C{ = (5.20)Ki
The resulting SC biquad network is shown in Fig. 5.3 as follows:
4>\
Figure 5.3 SC biquad network of Fig. 5.2
The element values can be obtained from using the approximation of Eqn. (5.20).
They are:
C, ~ — = (4)voTe = |Aok,rcWo XW 5 '
(5.21)
C2 — C3 — w0rc (5.22)
(5.23)
£5ckWo
(5.24)
83
Cq — C?2 (5.25)
Ao in Eqn. (5.21) is the constant dc gain, normally |Ao| >1. The capacitance spread of the hi quad, for Q>1, is
Ca _ 1C2 UqTc
(5.26)
The corresponding exact z-domain block diagram operation of the SC biquad can
be obtained and shown in Fig. 5.4 [4].c3
Figure 5.4 Block diagram of the exact z-domain of SC biquad
The exact voltage transfer function of the SC biquad in the z-domain can be found
from Fig. 5.4 to be
Vz(z) _ C§z2 + (C1C3 + C5C3 — ‘1Cg)z + (Ce — C5C3)Vi(z) z2 -}- (C2C3 + C3C4 — 2)z + (1 — C3C4)
(5.27)
Comparing Eqn. (5.27) with Eqn. (5.3), the following capacitance values are
obtained:
C6 0262
(5.28)
84
, (Cg ~ I f ) (q2 - ap) 5 C3 (b2 C3)
„ ~ C'sC's + 2C76)Gi = -------------------------
(gp + ai +02)(b2C3)
(5.29)
(5.30)
(5.31)
C2C3 ( h ~\ hC3C4 + 2 (&1 + &2 + 1)
b2(5.32)
As mentioned in Martin and Sedra [7], in order to maximize the dynamic range of the system, it is usually a good practice to set the time constants of the biquad to be equal. Here, capacitance C2 is set to be qua! to C3, 02=03. Eqn. (5.32) can
now be written as
C. = f l g n (5.33)
Capacitor value O3 can now be found, and the rest of the capacitor values can be
easily obtained.The biquad shown in Fig. 5.4 is universal. It can be used to obtain low-pass
response, high-pass response, the notch and bandpass characteristics as well. This
can be done as follows:
L For LOWPASS response;
To obtain a lowpass response, the factors d% and d2 in Eqn. (5.5) must be equal to
zero, that is,
d\ = d2 = 0 (5.34)
85
then
which gives
C5 = Ce = 0
a 0 = g 2 = 0
(5.35)
(5.36)
II. For HIGHPASS response:
From Eqn. (5.5), a highpass response can be realized if
do = dj = 0 (5.37)
SO
Ci = C5 — 0 (5.38)
then eh1II<NQ110Q (5.39)
III. For BAND REJECT (NOTCH) response:
Similarly, to obtain a notch response, the factor di of Eqn. (5.5) must be set to
which gives
then
<Zi = 0
C5 = 0
02 = #0
(5.40)
(5.41)
(5.42)
with a pair of complex conjugate zeros occurs on the unit circle.
IV. For BANDPASS response:
86
Clearly, the factors do and dg in Eqn. (5.5) must be set to zero a bandpass response, that is
in order to obtain
£• II S- II o (5.43)
This gives
P II P II o (5.44)
so
# 2 = 0 #1 = —#0 (5.45)
Thus, the zeros are at z=oo and z= l.
Section 5,3 Bilinear Transformation Method
Another method for obtaining a second-order biquad transfer function is by the use of bilinear transformation relationship. The method, as discussed in Martin and Sedra [7], will be presented in this section. Again, this is the case for a high-Q inverting biquad. The bilinear transformation from the continous s-domain into a
discrete z-domain can be denoted as the following
s =z - 1
2 + 1(5.46)
The general form of continous-time second-order system has been given in
Eqn. (5.3). If the coefficient b^ in Eqn. (5.3) is unity, then by substituting Eqn.
(5.46) into Eqn. (5.3), the following relation is obtained
y2(z) ° a ( ^ ) .
Vl(z) ( s i ) 2 + 6 . ( s i ) + 6 o
#2(2^ — 2z + 1) + cii(z2 — 1) + <3o(z2 + 2z + 1) (z2 - 2 z + 1) + h i z 2 ~ 1) + b0(z2 + 2 z + 1)
— (qq -f- + Q2)^2 4- 2 z(ao — 02) 4" (Qo ~~ ai ^2)(1 + 60 + 61 )^ 2 + 2z(6q — 1) + (1 — 61 + 60)
If we let
87
m I + 60 + 61’(5.48)
by inserting Eqn. (5.48) into Eqn. (5.47), the transfer function of the z-domain inverting second order filter may be written as:
^2(2) _ m(a0 + ai + a2 )z2 + 2m(a0 — 02)2 + (ap — ai + a2 )m V\ ( 2 ) 2 2 + 2m(60 — 1)2 + m (l — 61 + 60)
Eqn. (5.49) represents an inverting high-Q biquad transfer function. One can show a similar transfer function for the noninverting biquadratic system with a positive multiplying value.
The circuit shown in Fig. 5.5 is a negative SC biquad network. It is capable
of realizing the bilinear z-transform of any second order having a transfer function
of Eqn. (5.49). Fig. 5.5 is similar to Fig. 5.3 of Sect. 5.2.
(5.49)
1 ATiCx
Figure 5.5 Negative SC biquad network
88
Fig. 5.5 can be redrawn in compact form and is shown in Fig. 5.6.
KaC,
apply feed b a ck
K i C i <t>i /cascade or
goto V,
Figure 5.6 Compact form of Fig. 5.5
Section 5.4 Design of Bandpass SC Filters
Since the bandpass filter is only of an even order, it is much simpler to use
the coupled-biquad in the implementation process, particularly for a higher than
second-order bandpass filter. For a given bandpass filter specifications and desired
clock frequency, the specifications must be first prewarped in order to obtain a
suitable normalized lowpass prototype passive RLC network. This can be done by
using the following scaling factor, Cl, defined as:
(5.50)
where
w= desired frequencies.
Cl= unnormalized frequencies of the prototype passive RLC filter.
r J '
’( v x ls s iw ^ 9 |
0^0 W\\S1W(K JYSVK
fV\(>fO^\LNj
90
summing circuit is required in the process of leapfrog circuit design. The reason for the additional summing circuit will be explained in Sect. 5.4.1.
Section 5.4.1 Geometric Sixth-Order Elliptic Bandpass SC Filter Design Using Coupled-Biquads
To illustrate the procedures described in Sect. 5.4, the design of a geometric six-order SC elliptic bandpass filter using blocks of coupled-biquads will be carried
out in this section. Let the design specifications be:
* Passband frequencies: 1.8kHz-2.2kHz with attenuation of IdB.
* At all frequencies outside 0.8kHz bandwidth, the function should have a
minimum attenuation of 34.454 dB.
* Clock frequency: 10kHz.
First, using Eqn. (5.50) to prewarp all frequencies, we obtain the unnormalized
bandpass response shown in Fig. 5.7.
Figure 5.7 Unnormalized sixth-order elliptic bandpass response
The unnormalized frequencies of Fig. 5.7:
Qo=unnormalized center frequency=0.7265425 rad/sec.
£lpl=unnormalized lower-pass band frequency=0.6346192 rad/sec.
flpu=unnormalized upper-passband frequency=0.8272719 rad/sec.
91
BW \=Q.pu — Qp/=0.1926527 rad/sec.
Q = -^1=3.7712552.
After prewarping, the Q-factor has a value of 3.7713 while the actual design Q-factor
is exactly 5.Next, the normalized bandpass function may be obtained by making the
center frequency equal to a unity value and scaling other frequencies by kfi =
fl0 =0.7265425 to obtain the following normalized values:
Oon=l rad/sec.fipLn =0.8734783 rad/sec.
topt/n=1-138642 rad/sec.
BT47n=0.2651637 rad/sec.
Q„ = 5^=3.7712552.
Since the bandwidth of the bandpass filter is equal to the bandwidth of the lowpass filter, the unnormalized response of the third-order LPP filter can be seen in Fig.
5.8.
Id B
34 454dB ........
B W n = 0.2652rad/ te c
Figure 5.8 Unnormalized 3rd-order elliptic LPP response
from which its normalized values can be obtained, that is by factor scaling of k f2 =
B lFn=0.2651637, and results in:
92
l3
0 .2 2 5 9 FC i ± 1 .8 5 2 F 1 .8 5 2 F
1 O hm
Figure 5.9 Normalized 3rd-order elliptic LPP filter
Now table look-ups can be used to obtain a suitable passive ladder LPP that meets the requirements as described in Fig. 5.9. The normalized case for a
third-order LPP filter [17] is shown in Fig. 5.10.
l3
0 .85193C i ± 6 .9 S 4 3 F 6 .9 S 4 3 F
1 Ohm
Figure 5.10 Required normalized 3rd-order elliptic LPP filter
The LPP of Fig. 5.10 has the following poles and zeros locations:
poles:-0.539958 and -0.217034+jO.981575
zeros:± j 2.270068
passband attenuation of IdB
stopband attenuation of 34.454dB.
93
The corresponding transfer function of Fig. 5.10 is:
M i l = ^ 2 + 5.153209) .V1(s) (s + 0.539958)(s2 + 0.434067s + 1.010594) 1 '
where k = multiplicative constant = 0.1058909.
Since the prewarping of the design specifications of the sixth-order SC elliptic
bandpass filter according to the desired clock frequency results in having an actual Q-factor of Qn=3.7712563 rather than a Q of 5, the element values of Fig. 5.10 must be scaled by a factor of Qn=3.7712552. These element values are:
R i = J?2=l Ohm.
Ci = <73=6.9843289 F.
<72=0.8519267 F.
X 2 =3.2396222 H.
The next step is to obtain a normalized sixth-order bandpass filter* where Oon=l rad/sec, BW „=0.2651636 rad/sec, and Qn=3.7712563, by making use of the lowpass to bandpass transformation. The resulting circuit is shown in Fig. 5.11
having the following element values:
R i = Jf?2=l Ohm.
Ci = <73=6.9843289 F.
= 2/3=0.1431776 H.
<72=0.8519267 F.
T2 =1.1738099 F.
L2 =3.239622 H.
<7^=0.3086779 F.
Because the prewarping process has shifted the actual Q from being 5 to 3.7713, the
center frequency of the bandpass filter is also shifted from 1 rad/sec to 0.7265425
rad/sec. Therefore, the normalized bandpass element values must be denormalized
94
by a scaling factor n o=0.7265425 rad/sec to obtain the following final element values:
R i = R 2=1 Ohm
Ci =C 3=9.6131043 F
L’1=L ,3=0.1970672 H
C2= l .1725765 F
L’2=1.6156107 H
12=4.4589573 H
€ ’2 =0.4248586 F
Ca=C6=Ci+C2=C2+C3=10.78568 F
1 O hm
1 O hm
Figure 5.11 Sixth-order bandpass prototype filter
Section 5.4.2 Process for Obtaining a Block Diagram
The process for obtaining a block diagram of the sixth-order SC elliptic
bandpass filter is described in this section. The Thevenin equivalent network of
Fig. 5.8 can be drawn in Fig. 5.12. By linearity, Kirchoff’s voltage law (KVL) and
current law (KCL) can be applied to Fig. 5.12 and obtain:
Vo = Vin - Vx (5.52)
95
h Vo_Ri
I2 = h — h
+ 0---- sAAA
V,n
Figure 5.12 Thevenin equivalent of Fig. 5.9
Vi = / 2
= h
-1s{C\ + C'2)
+ v3 Ci + c2
V2 = Vi - v3
A = V2( 1 / s L 2 )
V3 = A
h = h — h
-1s(C2 + C3)
J4( ^ ) +Vb
C24-Vi
C2 + C3
(5.53)
(5.54)
(5.55)
(5.56)
(5.57)
(5.58)
(5.59)
(5.60)h Voutr 2
V3R 2
Vout = VZ (5.61)
The leapfrog block diagram of the sixth-order elliptic bandpass filter can berepresented as shown in Fig. 5.13.
Figure 5.13 Block diagram of Fig. 5.11.
The equivalent block diagram of Fig. 5.13 can be redrawn in Fig. 5.14.
Figure 5.14 Equivalent block diagram of Fig. 5.13
97
Note that the new path linking Vi and V3 shown in Fig. 5.14 presents a problem because both voltages are op-amp outputs, thus it is not suitable for summing without an additional operational amplifier. Therefore, this block diagram must be modified. This justifies the additional summing circuit needed in the leapfrog
realization. The modified block diagram is shown in Fig.5.15.
Figure 5.15 Modified block diagram of Fig. 5.14
In Fig. 5.15, the constant term, k, is defined as:
k= the ratio of the maximum gain of desired SC bandpass filter to the maximum
gain of the passive LPP.
The constant factor, k, is used to maximize the dynamic range of the final SC
bandpass filter.Therefore,
m axim um gain o f B P F m axim um gain o f lossless L P P F (5.62)
Next, apply the lowpass to bandpass transformation by letting
sCJq
~BW(5.63)
or
98
s(B W )
where: BW=u>3dB frequencies.
(5.64)
The following transfer functions can then be obtained
T l ( s ) - R l / / Z 2 -(5.65)
(5.66)
T . M - R J / - * - s2 + 3 W + u i o (5.67)
(5.68)
The corresponding block diagram of the sixth-order elliptic bandpass filter is shown
in Fig. 5.16
Figure 5.16 Block diagram of sixth-order elliptic bandpass filter
99
The circuit schematic diagram of the sixth-order elliptic SC bandpass filter is shown in Fig. 5.17. A suitable summing circuit has not yet been found. For the time being, some studies of a similar circuit presented by Hokenek and Moschytz [19] shown in Fig. 5.18 will be given. The design of sixth-order geometric SC elliptic bandpass presented in [19] has been verified with a SW ITCAP analysis.
Figure 5.17 Sixth-order SC elliptic bandpass filter
100
4>2
Figure 5.18 Hokenek and Moschytz’s version of Fig. 5.17
101(*) : vdb(26)f req
i nn+n?- 6 0 . 0 0 1 __—
- 4 0 . 0 0 oO H
OOO•0<N1
3 . 24+0211 *
3 . 50+02 1 *3. 78+02 1 *4 . 0 8 + 02 1 *4 . 4 1 + 02 1 *4 . 76+02 1 *5. 14+02 1 *5 . 55+02 1 *5 . 99+02 1 *6. 47+02 1 *6 . 99+02 1 *7 . 55+02 1 *8. 15+02 1 *8. 81+02 1 *9 . 51+02 1 *1. 03+03 1 *1. 11+03 1 *1. 20+03 1 *1. 29+03 1 *1 . 4 0 + 03 1 *1 . 51+03 1 *1. 63+03 1 *1. 76+03 1 *1 . 90+03 1 *2. 05+03 1 *2 . 22+03 1 *2 . 39+03 1 *2 . 58+03 1 *2. 79+03 1 *3. 01+03 1 *3. 26+03 1 *3. 52+03 1 *
3. 80+03 1 *4. 10+03 1 *4. 43+03 1 *4. 78+03 1 *5. 17+03 1 *5. 58+03 *6. 02+03 1 *6. 51+03 1 *7. 03+03 1 *7. 59+03 1 *8 . 19+03 1 *8 . 85+03 1 *9. 56+03 1 *1. 03+04 1 *1. 11+04 1 *1. 20+04 1 *1. 30+04 1----------------
f r e q - 6 0 . 0 0 - 4 0 . 0 0 - 2 0 . 0 0 0 . 0 0 2 0 . 0 0( * ) : v d b ( 2 6 )
Figure 5.18(a) SW ITCAP simulation of Fig. 5.18
102f req
R R 7 + f) 9- 1 0 . 0 0 1- - __ 1 1 1
1 1
00
<- •
* o
1
o
1 1
( * ) : v d b ( 3 2 ) - 6 . 0 0 - 4 . 0 0
1 1 1 l 1 M O O 0 . 0 0
8 . 89+0211 *
8 . 92+02 1 *
8 . 94+02 1 *
8 . 96+02 1 *
8. 99+02 1 *
9 . 01+02 1 * 1
9. 04+02 1 * 1
9. 06+02 1 * 1
9 . 08+02 1 * 1
9 . 11+02 1 * 1
9. 13+02 1 *
9. 16+02 1 *
9 . 18+02 1 * 19. 21+02 1 * 1
9. 23+02 1 * 1
9. 25+02 1 * 1
9. 28+02 1 * 1
9. 30+02 1 * 1
9 . 33+02 1 * 1
9. 35+02 1 * 1
9. 38+02 1 * 1
9. 40+02 1 * 1
9. 43+02 1 * 1
9. 45+02 1 * 1
9. 48+02 1 * 1
9. 50+02 1 *
9. 53+02 1 *
9 . 55+02 1 *
9 . 58+02 1 * 1
9 . 60+02 1 * 1
9. 63+02 1 * 1
9. 66+02 1 * 1
9. 68+02 1 * 1
9. 71+02 1 * 1
9. 73+02 1 - * 1
9. 76+02 1 * 1
9 . 78+02 1 * 1
9. 81+02 1 * 1
9. 84+02 1 * 1
9. 86+02 1 *
9 . 89+02 1 *
9 . 91+02 1 * 1
9. 94+02 1 * 1
9. 97+02 1 * 1
9. 99+02 1 * 1
1. 00+03 1 *
1. 00+03 1 *
1. 01+03 1 *
1 01+03 I1f req - 1 0 . 0 0 1 00 o o i <n o 0 1 fk o o - 2 . 0 0 0 . 0 0
( * ) : v d b ( 3 2 )
Figure 5.18(b) Passband attenuation of Fig. 5.18(a)
103
Section 5.4.3 An Eighth-Order General Stray-Insensitive SC Elliptic Bandpass Filter Design.
In this section, the design of the assymmetric elliptic bandpass filter using the method proposed by Yoshihiro, Nishihara, and Yanagisawa [24] is presented.
The proposed method yields a highly desirable result. The component values of the circuit are not obtained from the table look-ups. This circuit is originally designed and presented by Martin and Sedra [7]. Here, the detailed analysis of the circuit is studied and evaluated. The result is then verified with SW ITCAP. The following are the design specifications:
Passband: 0.9kHz-lkHz.
Passband attenuation: 0.25 dB maximum deviation.
Upper Stopband: A> 50 dB for /o > 1.05 kHz.
Lower Stopband: A> 38 dB for fo < 0.95 kHz.
Clock frequency: / c = 8 kHz.
The passive ladder RLC network of this general bandpass circuit is shown in Fig. 5.19.
Li Li L*
Figure 5.19 Passive eighth-order RLC asymmetric bandpass filter
The component values have been prewarped according to Eq. (5.42). The sim
ulation of this passive eight-order RLC assymmetric bandpass filter using SPICE
results in the following peak voltages:
Vi =0.817 V; V3 =0.376 V; V5 =0.125 V; V0=0.019 V.
104
The equivalent block diagram of the SC elliptic bandpass filter as proposed by
Yoshihiro et al [24] can be seen in Fig. 5.20.
3
Figure 5.20 Block diagram of SC elliptic bandpass filter
where the ratios of the peak voltages are:
^ = 0.023256; |? = 0.460220; = 2.172872;
#■ = 0.332447; # = 3.008: %■ = 0.152; £ = 6.578947.
The above ratios of peak voltages will be used to scale the active realization of SC
network in order to maximize dynamic range. The transfer function of each biquad
second order network can be achieved as follows:
I. T H E F IR S T B IQ U A D T R A N S F E R F U N C T IO N S
In the continuous-domain, the first hi quad network consists of two transfer
functions.
1.1 T he first tra n s fe r function
The first transfer function Tn(s) is equal to the ratio of Vi(s) to Vi(s) and
can be achieved by setting V3 to ground potential that is
T„(s) y .ooVi(s)
Vs(a)=0
which can be easily obtained by observing the equivalent circuit of Fig.5.21.
(5.69)
105
)I
p c3:
Figure 5.21 Circuit for the first transfer function
The equivalent shunt impedance Z lc (&) can be obtained as:
s/C2 s/C2S 2 + C^U HU) S 2 +
and the voltage transfer function is the voltage divider:
(5.70)
Til 00%LC
Z lc + Rt( r ] c 7 )
+ s ( r^ 7 ) +R' c ’ c r« (* fc )(5.71)
From Eqn. (5.71) with Eqn. (5.3) (b2 = l) , the following parameters can be obtained:
K2=0.06725 , K3 =0.023558166 , K4=0.7006577=K5 , K6=K 2=0.06725 , and Ki=0.
1.2 T he second tra n s fe r function
The second transfer function T3 i(s) is equal to the ratio of Vi(s) to y3(s)
with Vi(s)=0;
r „ ( s ) Y i i f l% (j)
(5.72)V<(*)=0
where the equivalent circuit under this condition is shown in Fig. 5.22.
106
Zlc
z r l 0 1'5
Figure 5.22 Circuit for the second transfer function
Again by using the voltage divider principle, the result is immediate
r„(s) s l + L2C2
s 2 + s { ^ ) + ^ & T ) '
(5.73)
From Eqn. (5.73) with Eqn. (5.3) (b2=l), the following parameters are obtained:
K i=0.5714912 , K2=0 , K3=0.953816 , K4=K5 =0.7006577 , K6=0.06725.
II. TH E SECOND BIQ UAD T R A N SFE R FU N C TIO N S
The second continuos-domain biquad network also consists of two transfer
functions.
II .1 The third transfer function
The third transfer function 7i3(s) is equal to the ratio of V^s) to Vi(s) with
1 5(5) is set to ground potential:
Tn(s) V(*)3Vi(s) V5(*)=0
which can be achieved by observing the equivalent circuit of Fig. 5.23.
(5.74)
107
C3 ~ C4 3
Figure 5.23 Circuit for the third transfer function
The voltage transfer function is:
T,3(S)( C2
y C2 + C3 + C4
+ L2C2s2 + (c2+c3+c<) ( ^ : )
(5-75)
From Eqn. (5.75) with Eqn. (5.3) (b2= l) , the following parameters are obtained:
Ki =0.0776512 , K2=K 6=0 , K3=0.1347876 , K4=K5=0.7287041.
II.2 The fourth transfer function
The fourth transfer function 253(3) is equal to the ratio of V^s) to Vs(s)
with Vi(s) is set to ground potential:
r„(s) V3(s)v,(.)=o
(5.76)
W ith the equivalent circuit shown in Fig. 5.24, the transfer function 753(5) can be
obtained.
108
Figure 5.24 Circuit for the fourth transfer function
The transfer function from Fig. 5.24 is
*2 + '_____ ________ )C*2 + C3 + C4 J
LaCaS 2 +
( C 2 + C 3 + C 4 ) ( - ^ ^ ) -
(5.77)
From Eqn. (5.77) with Eqn. (5.3) (b2=l), the following parameters are obtained
K i=0.6510526 , K2=K 6=0 , K3 =0.7312512 , K4=K 5=0.7287041.
III. THE TH IRD BIQ UA D T R A N SFE R FU N C TIO N S
Similar to the second biquad network, the third biquad consists of two trans
fer functions.
II I .l The fifth transfer function
The fifth transfer function 735(5) is equal to the ratio of V^s) to V^s) with
Vq{ s ) is set to zero.
T35WM i )V3(s)
Vb(#)=0
(5.78)
which again can be easily obtained by observing the equivalent circuit of Fig.
5.25.
109
c8 i c« 3 L«
■o +
V8
Figure 5.25 Circuit for the fifth transfer function
The voltage transfer function is:
T 3s ( s )CU
C4 + C5 + Cq
s2 + L4C4S 2 +
( C 4+ C , + C e ) ( i ' + t , ) -
(5.79)
From Eqn. (5.79) with Eqn. (5.3) (b2=l), the following parameters are obtained:
K i=0.0950718 , K2=K6=0 , K3=0.1096816 , K4=K5=0.748472.
I I I .2 T he s ix th tran s fe r function
The sixth transfer function is equal to the ratio of Vs(s) to Vq( s ) with ^ ( s ) is set to zero.
V„(s)(5.80)
Va(»)=0
Where its transfer function can be obtained from the equivalent circuit of Fig. 5.26.
---- 1
Figure 5.26 Circuit for the sixth transfer function
110
And the transfer function is
C6C4 + C5 + Cg s2 +
^2 + T f e 1
(C4+C'6+C6) ( - ^ ^ ) ■(5.81)
From Eqn. (5.gl) and Eqn. (5.3) (b2= l) , the following parameters are obtained:
Ki =0.6534003 , K2=K 6=0 , K3 =0.6597829 , K4=K5 =0.748472.
IV . TH E FOURTH BIQ UA D T R A N SFE R FU N C T IO N
Finally, the last transfer function of the fourth biquad can be expressed as
the following:
, T 5Q( s )VoV5
C6
Cg + cvs 2 + 1
_s2 + S R L (C6+ C 7) + (C6+C-7) ( 4 ^ ) -(5.82)
From Eqn. (5.82) and Eqn. (5.3) (b2= l) , the following parameters are obtained:
Ki =0.050920801 , K2=0 , K3= 0.050146014 , K4=K5 =0.7299531 , Kg=0.07233406.
Vo THE SUMMARY OF THE FINAL ELEMENT VALUES
I. For biquad 1:
* A4,i = -Ki ( - | ) - 0.2630
*K 4 ,i = K | ( S ) = 0.4390
* K o , i = K i [&(&)] =0.08233
*Ko,2 = K i [ & ( ^ ) ] = 0.02884
* J$Ti)2 = Ff2 1 = K 5 = K 4 = 0.7007 (both 1 & 2)
* K i = Kg = 0.06725 (both 1 & 2)
I l l
II. For biquad 2:
* 1 4,3 = Kz,i — K 4 — K 5 = 0.7287 (both 3 & 4)
* K 2 = Ke = 0 (open)
4 =Jif33( ^ ) =0.2929
* JiC6,3 = = 0.2164
* Jif2, 3 = F f i ( ^ ) = 0 . 1 6 8 7
* #6,4 = #3 (% ) = 0,2431
III. For biquad 3:
* Ke ,5 = K b,6 = K 4 = K 5 — 0.7485 (both 5 & 6)
* K 2 — K q = 0 (open)
* K 4>6 = JV35( S ) = 0.3299
* X 8,5 = iif16( ^ ) = 0.09932
* #4,5 = # f ( ^ ) = 0.2860
= 0.1003
IV. For biquad 4:
* iiTsj = K 7jS = K l = K l = 0.7300 (only 7)
* K 7 = K l = 0.0724
* i r 6)8 = K37( S ) =0.3299
* l f 6,7 = J f + l 7( S ) = 0.3350
This concludes the total capacitance values needed in the realization of eifghth-order
general SC elliptic bandpass filter. The schematic diagram is shown in Fig. 5.27.
The SW ITCAP simulation of the circuit of Fig. 5.27 is shown in Fig. 5.27(a). The passband attenuation of Fig. 5.27(a) is shown in Fig. 5.27(b).
112
K o ,x C x
• K4,&C&
Figure 5.27 Eighth-order general SC elliptic bandpass filter
20.00f r e q - 8 0 . 0 0I
i CT\ O • O O
( * ) : v d b ( 32)- 4 0 . 0 0 - 2 0 . 0 0 0 . 0 0
16 . 11+02 1 *6. 23+02 1 *6 . 35+02 1 *6 . 47+02 1 *6. 59+02 1 *6. 71+02 1 *6. 84+02 1 *6. 97+02 1 *7. 10+02 1 *7. 23+02 1 *7. 37+02 1 *7. 51+02 1 *7. 65+02 1 *7. 80+02 1 *7. 94+02 1 *8 . 09+02 1 *8. 25+02 1 *8. 40+02 1 *8. 56+02 1 *8. 72+02 1 *8. 89+02 1 *9 . 05+02 1 *9 . 22+02 1 *9 . 40+02 1 *9. 58+02 1 *9. 76+02 1 *9. 94+02 1 *1. 01+03 1 *1. 03+03 1 *1. 05+03 1 *1. 07+03 1 *1. 09+03 1 *1. 11+03 1 *1. 13+03 1 *1. 15+03 1 *1 . 1 8 + 03 1 *1. 20+03 1 *1. 22+03 1 *1 . 24+03 1 *1. 27+03 1 *1. 29+03 1 *1. 32+03 1 *1. 34+03 1 *1. 37+03 1 *1. 39+03 1 *1. 42+03 1 *1. 44+03 1 *1. 47+03 1 *1. 50+03 1---------- i i i i + i i i i i i i i i i i + i i 1 i 1 i i i i i i + i
f r e q - 8 0 . 0 0 - 6 0 . 0 0 - 4 0 . 0 0 - 2 0 . 0 0 0 . 0 0 2 0 . 0 0( * ) : v d b ( 3 2 )
Figure 5.27(a) SWITCAP simulation of Fig. 5.27
114(* ) : v d b ( 26)Ereq - 1 . 5 0 0 - 1 . 2 5 0 - 1 . 0 0 0 - 0 . 7 5 0 - 0 . 5 0 0 - 0 . 2 5 0 0 . 0 0 0
1 . 34+03 1 . 37+03 1 . 40+03 1 . 4 2 + 03 1 . 4 5 + 03 1 . 4 8 + 03 1 . 51+03 1 . 54+03 1 . 57+03 1 . 61+03 1 . 64+03 1 . 6 7 + 03 1 . 71+03 1 . 74+03 1 . 78+03 1. 81+03 1. 85+03 1 . 89+03 1 . 93+03 1 . 97+03 2 . 0 1 + 03 2 . 05+03 2 . 0 9 + 03 2 . 13+03 2 . 1 7 + 03 2 . 22+03 2 . 26+03 2 . 31+03 2 . 3 6 + 03 2 . 41+03 2 . 45+03 2 . 50+03 2 . 56+03 2 . 61+03 2 . 66+03 2 . 71+03 2 . 77+03 2 . 83+03 2 . 88+03 2 . 94+03 3. 00+03 3 . 06+03 3. 13+03 3. 19+03 3. 25+03 3. 32+03 3. 39+03 3. 46+03 3 . 53+03 3. 60+03
f r e q - 1 . 5 0 0 - 1 . 2 5 0 - 1 . 0 0 0 - 0 . 7 5 0 - 0 . 5 0 0 - 0 . 2 5 0 0 . 0 0 0( * ) : v d b ( 2 6 )
Figure 5.27(b) Passband attenuation of Fig. 5.27(a)
115
CHAPTER 6
FIFTH-ORDER SC ELLIPTIC LOWPASS FILTER DESIGN
In this chapter, the fifth-order SC elliptic lowpass filter design presented by Datar and Sedra [35] will be studied. The design technique given in Scanlan [27] is used. Because of the systematic approach given by this technique in the design of SC circuits, it is worth looking into. The final design of the lowpass filter will be verified with the simulation of SW ITCAP and an actual realization using discrete
components.
The design of the circuit will begin with the transfer functions of both Type I LDI SC stray-insensitive inverting and noninverting integrators derived in Chapter
3 as basic bulding blocks. The stray-insensitive SC inverting integrator shown in
Fig. 3.9(a) is redrawn as Fig. 6.1 for completeness.The transfer function of the SC stray-insensitive inverting integrator of Type I LDI shown in Eqn. (3.57) is
rewritten here as:
Section 6.1 Design of the Fifth-Order Lowpass Elliptic SC Network Functions
( 6 . 1 )
4>2 $3 |------It
V,
Figure 6.1 Stray-insensitive inverting SC integrator
116
Similarly, The stray-insensitive noninverting SC integrator shown in Fig. 3.9(b) is redrawn here as Fig. 6.2. Its transfer function of Type I LDI given Eqn. (3.75) is rewritten as:
Vo(z) ZC,v ^ ) = + l ^
( 6 .2 )
Ca
Figure 6.2 Stray-insensitive noninverting SC integrator
Fig. 6.3 shows a useful SC circuit building block which will be utilized in the leapfrog circuit realization. The transfer function of the circuit shown in Fig. 6.3 can be obtained by combining Eqns. (6.1) and (6.2) using the superposition principle.
Fig. 6.3 SC building block used in leapfrog realizations
117
With these in mind, a transfer function of Fig. 6.3 can be obtained as:
Vojz) _ —C\ — Cafe1/2 — z 1/2) — C4 ViOO “ (Cf 4- C)zV2 _ c 2—1/2
_ —C\ — 2 C3 7 — C4
7 (2 C + C /) + /iCf
where the complex variables 7 , / i , and A as defined in Scanlan [27] are
7 = ^ ( z 1 /2 - 2 ' 1/2) = s in h ( ~ ^ ) =
H = l ( z 1/2 + z-1/2) = c o s h ^ ^ ^ =
Azl/2 _ z-l/2 zl/2 + z-l/2
(6.3)
(6.4)
(6.5)
t a n h ( ^ ) = j t a n ^ ^ ^ , (6.6)
Fig. 6.4 shows the fifth-order continuous-domain lowpass prototype filter that will be used in the SC circuit design.
L a l «
Figure 6.4 Fifth-order LPP
The leapfrog block diagram of Fig. 6.4 is shown in Fig. 6.5.
118
Figure 6.5 Leapfrog block diagram of Fig. 6.4
The transformation from Fig. 6.4 to its 7 -plane circuit representation is shown in Fig. 6.7.
r. y.1 ■***• | ■
v.O
■r~> -0 +Vo
r.h
Fl7 r-L:]
t - j u ."Cl c3 j
L 4 —r: C3 c; C5 : n
Ca = c3+(l//3) v° c;=c4+(i/i4)
Xc'2 V3
ci=Ci+C3 c = C3+Ca + c<
Figure 6.6 7 -plane transformation of Fig. 6.4
119
From which its equivalent fifth-order SC elliptic lowpass filter is derived and is shown in Fig. 6.7.
<t>i
Figure 6.7 Fifth-order SC elliptic lowpass filter
120
The following equations can then be obtained from Fig. 6.7 as:
v ,, , = Ciz'I'VKz) - 2C16V>,(^)T1 7(2^3 + C^) + fiC3
K (z )Ctz-WViiz) + Csz'WVjiz)
7(2C6)
(6.7)
(6 .8 )
- C 7zW V j(z ) - C s z ^ V K z ) - 2C15l V;(z) - 2 Q 7 ^ '( z )} 7(2(79) ’ ( }
vl ( z) =
= v i
Cuz-WVjiz) + C u z-W V jiz ) . 7(2<712)
_ —C l 3 ^ ^ ^ V Z (^ ) ~ 2 ( 7 1 8 7 ^ 3 ( 2 )
7(2(7i4 + C/) + fiCi
(6.10)
(6.11)
From Fig. 6.4, we can obtain the following equations
Tr — v h +
1 _ 7c; + m( * ) ’
M )Vl —P3
l h
v _ (^ 2 ) - (n h ) + 74^1 + 74^5
W )^3 — ^5
7J4 ’
^0 = ^5( //J 4 ) + 'YC4V 3
i c5 + p (7;)
(6.12)
(6.13)
(6.14)
(6.15)
(6.16)
Comparing Eqns. (6.7)-(6.11) with Eqns. (6.12)-(6.16) we can obtain the following equations
121
(a) From Eqn. (6.12)
yVi - r s jv h ) + idlTeVz7 c ira
and from (6.7)
Also
VI _Ca 7 ( 2 C g c ^ + //
w _ - 2 % ^ - z ^ v i - 2 ^ y 3'7 C2 7 ( ^ ) + ^
and
and
VI2<7i 6
Vi = (7^ : ) ^ - ( ^ ) + 7 V3
4 7 ( f ) + / < ( * )
By equating the 7-plane directly, it is easily seen that
(i) From Eqns. (6.17) with (6.18), we can obtain
( 208+ C ^ = c > .V c.and
( t )
(6 .17)
(6.18)
(6.19)
(6 .20 )
(6 .2 1 )
(6 .2 2 )
(6.23)
where K is the ratio of the desired gain o f the SC network to the gain of the
passive ladder R LC network.
(ii) From Eqns. (6.19) and (6.12), we can get
122
( 2 £ l± ^ ) = c',
(iii) From Eqns. (6.20) and (6.21) we obtain
2C3 + Os
(b) From Eqn. (6.8) we may write
, z - ' v y ; , z - ^ v '
2 ™ 7 <e) 7 ( e )Comparing this with Eqn. (6.13), we obtain the following relation
'2C6\ f2 C 6\*2 •
(c) We may rewrite Eqn. (6.9) as follows
Viz - V 2Vi iV { 7 Vi
7 ( e ) 7 ( e ) 7 ® ) 7 ( e ) '
and we may also rewrite Eqn. (6.14) as follows
7 V1 7F5+ +7C3 7 ( f ) 7 ( f )
Comparing Eqn. (6.27) with Eqn. (6.28) in the 7-plane, we can get
(6.24)
(6.25)
(6.26)
(6.27)
(6.28)
(6.29)
(6.30)
(6.31)
123
(d) From Eqn. (6 .10) we may rewrite as follows
v[ — - xi2v i z - ^ v i+
Comparing Eqn. (6.32) with Eqn. (6.15) we get
f 2C i2\ f 2C'i2N\ ,l e d - ( c ir j - h -
lV z
(e) Eqn. (6.16) can be decomposed as follows
V o = V 5 = 1 + ' i7 4 n + » 7 ^ + ^ ( X )
Similarly, dividing Eqn. (6.11) by Ci we get
=%*zll2Vl
7 (2S * fca) + M ‘
However, Eqn. (6.11) can also be written as follows
V ’o - z x/2Vl iV i
7 ( ^ ) + / - &
(6.32)
(6.33)
(6.34)
(6.35)
(6.36)
The next step is to compare the above equations in the 7-plane as follows
(i) From the left-hand-side terms of Eqn. (6.34) with Eqn. (6.35) we obtain
2C14 + C/X
e Ci )can (6.37)
(ii) Comparing Eqn. (6.36) with Eqn. (6.16) we get
f 2Ch + CA _ ,V c u J - Cs (6.38)
(hi) Comparing the right-hand-side terms of Eqn. (6.34) with Eqn. (6.36)
we get
124
f ?£i±±£i\ — sk.V 2 C 18 J - c f A
From the above equations, one may obtain the following design component values
In order to obtain suitable values for the capacitors based on the available technology, we may need to rescale the values to the minimum value permitted by the technology. Lee, Temes, Chang, and Ghaderi [21] have given the following set of rules. They are:
(1) For an N op-amp SC filter, divide all capacitors into N nonoverlapping sets; capacitors in the j-th set Sj are connected or switched to the inverting input terminal of the j-th op-amp.
(2) Find the smallest capacitor Cjmin in each of the Sj. Let the smallest capacitance that practical (fabrication) restrictions permit be Cmin.
(3) Multiply all the capacitors in each Sj by rrij = CminIC jmin.
(6 .39)
The result is as following
[BLOCK 1]
The scaling constant k\ required for first block is:
CminCjmin
1Cie
10.4486514
2.2289019
and the new component values for the first block are
Ci = 0.4762&1 = 1.0614031
Ca = l&i = 2.2289019
C3 = 1.3090855&1 = 3.1001797 C2 = 1.7619047Aq = 3.9271127
Cie = 1.0
[BLOCK 2]
The scaling constant &2 required for the second block is:
k2dminC j min
1c 5
and the new components values are:
10.4324324
2.3125001
C A = 0.5675675^2 = 1.31249999
Cg = 1.0
[BLOCK 3]
The required constant k% for the third block is:
k* = CminC j m i n C n 0 .2660514
which gives new components values as follows
3.7586721
C 6 = 0.63035&3 = 1.4577
C 7 = 2 .3 1 2 5 ^ = 8 .6919294
Cg = 1.875*3 = 7.0475103
Cg = 2.8739874*3 = 10.802376
C i 5 = 0.7728721*3 = 2 .9049728
Ci 7 = 1.0
[BLOCK 4]
The constant *4 required for the fourth block is:
@minCjmin
1C11 0.33333
which gives new values of
C10 = 0.53333*4 = 1.6 C n = 3.0
126
C i 2 = 0.70625&4 = 2.11875
[B L O C K 5]
The required constant of the fifth and last block is:
CminCjmin
1.46823120.6810916
from which we obtain following new components values:
C\z = S&s = 4.4046938
C 14 = 1 .33328236s = 1.9575667
Ci g = 1.0
Cl = libs = 1.4682312
The circuit has been realized with the discrete components described in Chapter 1 and is shown in Fig. 6.8. The result has also been compared with a SW ITC A P
simulation as shown in Fig. 6.9. The passband attenuation of Fig. 6.9 is shown in Fig. 6.10. The laboratory test result of Fig. 6.8 for 10 dB scale on the HP 3580A spectrum analyzer is shown in Fig. 6.11. The 1 dB result is shown in Fig. 6.12. Finally, the passband of Fig. 6.11 is shown in Fig. 6.13.
127
Figure 6.8 Hardware realization of the fifth-order SC elliptic lowpass filter
128f req
? n n + r v ?- 1 0 0 . 0 1 00
-
o o
(*- 6 0 . 0
): v d b ( 36) - 4 0 . 0 - 2 0 . 0 0 . 0 20.
2 . 11+02 *2. 23+02 *2. 36+02 *2. 49+02 *2. 64+02 *2. 79+02 *2. 94+02 *3. 11+02 *3. 29+02 *3. 48+02 *3. 67+02 *3. 88+02 *4. 10+02 *4. 34+02 *4. 58+02 *4 . 84 + 02 *5. 12+02 *5. 41+02 *5. 72+02 *6. 04+02 *6. 38+02 *6. 75+02 *7. 13+02 *7. 53+02 *7. 96+02 *8. 42+02 *8. 89+02 *9. 40+02 *9. 93+02 *1. 05+03 *1.11+03 *1. 17+03 *1.24+03 *1. 31+03 *1. 38+03 *1. 46+03 *1. 55+03 *1. 63+03 *1. 73+03 *1. 82+03 1 *1. 93+03 *2. 04+03 *2. 15+03 *2. 28+03 *2. 40+03 *2. 54+03 *2. 69+03 *2. 84+03 *3. 00+03
f req - 1 0 0 . 0
o0 001 o0ID1 - 4 0 . 0 - 2 0 . 0 0 . 0 20.
(* ) : vdb (36)
Figure 6.9 Simulation of Fig. 6.8 using SWITCAP
0 . 0 0 0 2.000( * ) : v d b ( 3 6 )
f r e q - 8 . 0 0 0 - 6 . 0 0 0 - 4 . 0 0 0 - 2 . 0 0 0n nn + nnH 1 — _ _L _ j. . *
2 . 1 6 + 0 1 1 *4 . 3 3 + 0 1 1 *6 . 4 9 + 0 1 1 *8 . 6 5 + 0 1 1 *1 . 0 8 + 0 2 1 *
1 . 3 0 + 0 2 1 *
1 . 5 1 + 0 2 1 *
1 . 7 3 + 0 2 1 *1 . 9 5 + 0 2 1 *2 . 1 6 + 0 2 1 *2 . 3 8 + 0 2 1 *2 . 6 0 + 02 1 *2 . 8 1 + 0 2 1 *
3 . 0 3 + 0 2 1 *3 . 2 4 + 0 2 1 *
3 . 4 6 + 0 2 1 *
3 . 6 8 + 0 2 1 *
3 . 8 9 + 0 2 1 *
4 . 1 1 + 02 1 *
4 . 3 3 + 0 2 1 *
4 . 5 4 + 0 2 1 *
4 . 7 6 + 0 2 1 *
4 . 9 8 + 0 2 1 *
5 . 1 9 + 0 2 1 *
5 . 4 1 + 0 2 1 *
5 . 6 2 + 0 2 1 *
5 . 8 4 + 0 2 1 *
6 . 0 6 + 02 1 *
6 . 2 7 + 0 2 1 *
6 . 4 9 + 0 2 1 *
6 . 7 1 + 0 2 1 *
6 . 9 2 + 0 2 1 *
7 . 1 4 + 0 2 1 *
7 . 3 6 + 0 2 1 *
7 . 5 7 + 0 2 1 *
7 . 7 9 + 0 2 1 *
8 . 0 0 + 0 2 1 *
8 . 2 2 + 0 2 1 *
8 . 4 4 + 0 2 1 *
8 . 6 5 + 0 2 1 *
8 . 8 7 + 0 2 1 *
9 . 0 9 + 0 2 1 *
9 . 3 0 + 0 2 1 *
9 . 5 2 + 0 2 1 *
9 . 7 3 + 0 2 1 *
9 . 9 5 + 0 2 1 *
1 . 0 2 + 0 3 1 *
1 . 0 4 + 0 3 1 *
1 . 0 6 + 0 3 1_________1f r e q - 8 . 0 0 0 - 6 . 0 0 0 - 4 . 0 0 0 - 2 . 0 0 0 0 . 0 0 0 2 . 0 0 (
( * ) : v d b ( 3 6 )
Figure 6.10 Passband attenuation of Fig. 6.9
130
Fig. 6.11 Laboratory result of Fig. 6.8 (10 dB)
131
Fig. 6.12 Laboratory result of Fig. 6.8 (1 dB)
132
C m 35 BOA SPECTRUM ANALYZERV V I E T T . P A C K A R D
FREQUENCY
Fig. 6.13 Passband attenuation of Fig. 6.11
133
CHAPTER 7
CONCLUSIONS
The concept of SC network synthesis offers great promise in the future de
velopment of high-performance filters. Because SC circuits contain only capacitors and MOS switches, they can be fully implemented in MOS integrated-circuit technology. Thus, one solution to realizing economical active-RC filters in monolithic integrated-circuit form is through the use of SC techniques.
The bandpass and lowpass SC elliptic filters designs have been presented. The fifth-order SC elliptic lowpass.filter design has been studied and implemented. This particular design method is systematic and straightforward. However, there are few problems encountered in the design process which yielded undesirable fil
ter response. Therefore, the ultimate goal was to locate and to find the solution
to the the problem; also to achieve a working circuit condition. The design was first simulated using the SW ITCAP program. Although there were three uneven peaks shown in the passband attenuation, there was about 32 dB flat response in the stopband. To justify the findings, the circuit was then realized using discrete components and tested using a HP 3580A spectrum analyzer. The laboratory result agreed with the SW ITCAP simulation. These results suggested that further
modifications in the design are needed.
Initially, there was an additional SC circuit located between the track and
hold (T/H ) circuit and the first damped inverting integrator input. Its purpose was
to double the input frequency. Because the fact that both phases could not be nulled at the same time, at the same frequency, it presents a problem in the design. The filter was also found to be input sensitive so that a great care should be considered
into the design. Because of the sensitivity in the in the input variations, it is making
them difficult to utilize in a discrete form.
Some modifications in the mathematical design equations were given. These
modifications produced a changed in the capacitor value Ci by twice of its original
value. The rest of the element values in the circuit remain unchanged. By using the
134
new value of Ci in the simulation of S W IT CAP, it produced an excellent response. But this was not the case in the laboratory testing. Doubling the value of 0% did not give a working circuit condition. After the clock phase in the H /T circuit was changed from <2 to <f>i and after relentless trials, the actual discrete circuit was finally working. It produced a desired design response. The circuit is also no longer
sensitive to the input variations. This marks a significant improvement from the previous design.
It is important that Type I LDI inverting and noninverting SC integrators be
used in the design. Notice that Type I DDI integrator only exists in the inverting SC integrator. There does not exist a full period cycle response in the noninverting SC integrator case. This is the reason for using Type I LDI SC integrators throughout the design process.
Although the circuit is presently working in the laboratory testing and has been justified with the simulation, some further works are still needed to correct the
passband attenuation. This can be done by obtaining correct constant coefficients in the poles and zeros locations of the fifth-order elliptic lowpass transfer functions thru the optimization process or using the Gauss elimination method.
As final words, just when we thought that the world of electronics would stop
until the inductorless filter was discovered, welcome to resistorless and inductorless world of electronics. We are now entering the new era of SC concept of electronics
using MOS LSI technology.
APPENDIX A
LIST OF SWITCAP PROGRAMS
T I T L E : EIGHTH- ORDER SC E L L I P T I C B A N DP A SS F I L T E R C I R C U I T ( DYNAMIC R A N G E ) ;
/ * T H I S C I R C U I T C O N S I S T S OF FOUR SECON D- ORDER BI QUA D C I R C U I T S THAT FORM / * AN EIGHTH- ORDER SC E L L I P T I C B P F NETWORK U S I N G A METHOD PROPOSED BY / * Y O S H I H I R O ' S WITH THE FOLLOWING S P E C I F I C A T I O N S : [ 7 ] F I G . 5 . 2 7 ./ * * P A SS B A N D FREQUENCY : 0 . 9 KHZ - 1 . 0 KHZ HAVING A R I P P L E OF/ '* 0 . 2 5 0 DB I N THE P A S S B A N D ./ * * UPPER STOPBAND: A > 5 0 DB FOR F > 1 . 0 5 KHZ/ * * LOWER S TOP BAND: A > 3 8 DB FOR F < 0 . 9 5 KHZ/ * *THE CLOCK FREQUENCY I S AT 8 KHZ./ * *THE CENTER FREQUENCY I S AT 0 . 9 5 KHZ./ * * N OTI CE THAT AT A CLOCK FREQUENCY OF 8 KHZ, THE ACTUAL/ * Q UALI TY FACTOR OF THE C I R C U I T I T S E L F I S 0 = 8 . 4 7 RATHER/ * THAN A Q OF 9 . THE E F FEC T OF T H I S P A RTI CULA R D E S I G N WILL/ * BE OBSERVED H E R E .
T I M I N G ;P E RI OD 1 . 2 5 E - 0 4 ;CLOCK CLK 1 ( 0 1 / 2 ) ;END;
C I R C U I T ;/ * FOR THE F I R S T B I Q U A D : * /
5 1 ( 4 0 ) CLK;5 2 ( 3 4 ) #CLK;5 3 ( 2 8 ) #CLK;5 4 ( 8 0 ) CLK;5 5 ( 9 0 ) CLK;5 6 ( 7 9 ) #CLK;5 7 ( 5 6 ) CLK;5 8 ( 5 0 ) #CLK;C l ( 2 3 ) 3 . 3 E - 0 9 ;C2 ( 6 7 ) 3 . 3 E - 0 9 ;C8 ( 1 2 ) 2 . 7 1 6 8 9 E - 1 0 ;C9 ( 1 6 ) 9 . 5 7 2 E - 1 1 ;CIO ( 4 5 ) 2 . 3 1 2 3 1 E - 0 9 ;C l l ( 2 7 ) 2 . 2 1 9 2 5 E - 1 0 ;C 1 2 ( 8 9 ) 2 . 3 1 2 3 1 E - 0 9 ;C 1 3 ( 8 1 7 ) 8 . 6 7 9 E - 1 0 ;C 1 4 ( 6 1 6 ) 1 . 4 4 8 7 E - 0 9 ;E l ( 3 0 0 2 ) 2 E + 0 5 ;E2 ( 7 0 0 6 ) 2 E + 0 5 ;V I ( 1 0 ) ;
/ * FOR THE SECOND B I Q U A D : * /5 9 ( 1 3 0 ) CLK;5 1 0 ( 1 2 1 3 ) # C L K ;5 1 1 ( 1 1 1 0 ) #CLK;5 1 2 ( 1 0 0 ) CLK;5 1 3 ( 1 7 0 ) CLK;5 1 4 ( 1 6 1 7 ) # C L K ;5 1 5 ( 1 4 1 5 ) CLK;5 1 6 ( 1 4 0 ) ()CLK;
136
137
V I ( 1 0 ) ;
/ * FOR THE SECOND B I Q U A D : * /
5 1 2 ( 1 5 0 ) #CLK;5 1 3 ( 1 5 1 6 ) CLK;5 1 4 ( 1 7 1 8 ) #CLK;5 1 5 ( 1 8 0 ) CLK;5 1 6 ( 1 9 0 ) CLK;5 1 7 ( 1 2 1 9 ) #CLK;5 1 8 ( 1 4 1 3 ) #CLK;5 1 9 ( 1 4 0 ) CLK;C8 ( 1 3 1 2 ) 9 . 2 9 4 4 ;C9 ( 1 8 1 9 ) 1 8 . 0 1 5 ;CIO ( 1 7 1 6 ) 3 1 . 1 7 3 ;C l l ( 1 5 1 4 ) 2 . 9 4 4 ;C 1 7 . ( 1 0 1 3 ) 1 . 0 ;C 2 0 ( 8 1 8 ) 1 1 . 7 4 2 5 ;C 2 1 ( 1 3 2 6 ) 3 . 9 6 1 4 ;E3 ( 1 6 0 0 1 7 ) 2 E + 0 5 ;E 4 ( 1 2 0 0 1 3 ) 2 E + 0 5 ;
/ * FOR THE T H IRD B I Q U A D : * /
5 2 0 ( 2 3 0 ) # CLK;5 2 1 ( 2 3 2 2 ) CLK;5 2 2 ( 2 1 2 0 ) #CLK;5 2 3 ( 2 0 0 ) CLK;5 2 4 ( 2 7 0 ) CLK;5 2 5 ( 2 6 2 7 ) # CLK;5 2 6 ( 2 4 2 5 ) # CLK;5 2 7 ( 2 4 0 ) CLK;C 1 2 ( 2 5 2 6 ) 5 . 4 1 2 ;C 1 3 ( 2 4 2 7 ) 1 . 0 ;C l 4 ( 2 0 . 2 7 ) 3 . 7 8 7 ;C I S ( 2 1 2 2 ) 1 5 . 4 8 2 ;C 1 6 ( 2 3 2 4 ) 2 . 3 5 2 5 ;C 2 2 ( 1 2 2 5 ) 6 . 3 7 3 ;C 2 3 ( 1 9 2 0 ) 1 . 0 ;C 2 4 ( 1 8 2 7 ) 1 . 0 ;E 5 ( 2 2 0 0 2 1 ) 2 E + 0 5 ;E6 ( 2 6 0 0 2 5 ) 2 E + 0 5 ;
/ * THE END OF THE C I R C U I T .END?
/ * S TE A DY - S T A T E A N A L Y S I S : * /
ANALYZE S S S ?INFREQ 3 0 0 1 3 0 0 0 LOG 5 0 ?SET V I AC 1 . 0 0 . 0 ;PLOT V D B ( 2 6 ) ;END;
* / END;
138TITLE:SIXTH-ORDER SC ELLIPTIC BANDPASS FILTER CIRCUIT ;
/ * [ 1 9 ] E . HOKENEK AND G . S . MOSCHYTZ, " D E S I G N OF P A R A S I T I C - I N S E N S I T I V E * // * TRANSFORMED ADMITTANCE SCALED ( E T T A S ) SC LADDER F I L T E R S , " * / ■/ * ' I E E E T RA N S. C I R C U I T S S Y S T . , V O L . C A S - 3 0 , P P . 8 7 3 - 8 8 7 , D E C . 1 9 8 3 * // * D ES I G N S P E C I F I C A T I O N S : [ F I G . 5 . 1 8 ] * // * * P A SS B A N D FREQUENCY : 1 . 4 KHZ - 3 . 4 KHZ HAVI NG A R I P P L E OF * // * 0 . 1 7 7 DB I N THE P A S S B A N D . * // * *THE FUNCTION SHOULD HAVE A MINIMUM A TTEN UATI ON OF 3 0 . 4 1 DB * // * AT THE UPPER AND LOWER S T O P B A N D S . * // * *THE CLOCK FREQUENCY I S AT 3 2 KHZ. * // * *THE CENTER FREQUENCY I S AT 2 . 4 KHZ. * / '/ * * NO T I C E THAT AT A CLOCK FREQUENCY OF 3 2 KHZ, THE ACTUAL * // * QUALI TY FACTOR OF THE C I R C U I T I T S E L F I S Q = 1 . 1 5 RATHER * // * THAN A Q OF 1 . 2 . THE E F F EC T OF T H I S P AR TI C UL A R D E S I G N WILL * // * BE OBSERVED H E R E . * /
T I M I N G ;P E RI OD 3 . 1 2 5 E - 0 5 ; CLOCK CLK 1 ( 0 1 / 2 ) ; END;
C I R C U I T ;
FOR THE F I R S T BI QU A D:
S I ( 1 2 ) #CLK;S 2 ( 1 7 ) #CLK;S 3 ( 7 0 ) CLK;S 4 ( 5 0 ) #CLK;S 5 ( 4 5 ) CLK;S 6 ( 3 9 ) #CLK;S 7 ( 9 0 ) CLK;S 8 ( 8 0 ) CLK;S 9 ( 1 0 8 ) #CLK;S 1 0 ( 6 1 1 ) #CLK;S l l ( 6 0 ) C L K ; .C l ( 7 6 ) 1 . 0 ;C2 ( 6 8 ) 1 . 4 6 8 ;C3 ( 1 1 1 0 ) 4 . 0 7 5 ;C4 ( 8 9 ) 1 . 6 2 4 6 ;C5 ( 3 4 ) 3 . 1 3 6 5 ;C6 ( 5 6 ) 3 . 1 3 6 5 ;Cl ( 2 3 ) 1 . 0 ;C 1 8 ( 1 1 1 2 ) 1 . 0 9 6 ;C 1 9 ( 9 1 9 ) 1 . 2 1 5 5 ;E l ( 4 0 O ' 3 ) 2 E + 0 5 ;E2 ( 1 0 0 0 1 1 ) 2 E + 0 5 ;
139
C3 ( 1 2 1 1 ) 2 . 0 E - 0 9 ;C 4 ( 1 6 1 5 ) 2 . 0 E - 0 9 ;C I S ( 7 1 5 ) 5 . 8 5 8 E - 1 0 ;C 1 6 ( 1 3 1 4 ) 1 . 4 5 7 4 E - 0 9 ;C l 7 ( 1 0 1 7 ) 1 . 4 5 7 4 E - 0 9 ?C I S ( 9 1 0 ) 3 . 3 7 4 E - 1 0 ;C 1 9 ( 1 0 2 5 ) 4 . 3 2 8 E - 1 0 ;C 2 0 ( 1 5 2 4 ) 4 . 8 6 2 E - 1 0 ;E 3 ( 1 2 0 0 1 1 ) 2 E + 0 5 ;E 4 ( 1 6 0 0 1 5 ) 2 E + 0 5 ;
/ * FOR THE T HI RD B I Q U A D : * /5 1 7 ( 2 1 0 ) C L K ;5 1 8 ( 2 0 2 1 ) # CLK;5 1 9 ( 1 9 1 8 ) # CLK;5 2 0 ( 1 8 0 ) CLK;5 2 1 ( 2 5 0 ) CLK;5 2 2 ( 2 4 2 5 ) #CLK;5 2 3 ( 2 2 2 3 ) CLK;5 2 4 ( 2 2 0 ) # CLK;C5 ( 2 0 1 9 ) 2 . 0 E - 0 9 ;C6 ( 2 4 2 3 ) 2 . 0 E - 0 9 ;C 2 1 ( 1 6 2 3 ) 6 . 5 9 8 E - 1 0 ;C 2 2 ( 2 1 2 2 ) 1 . 4 9 7 E - 0 9 ;C 2 3 ( 1 8 2 5 ) 1 . 4 9 7 E - 0 9 ;C 2 4 ( 1 7 1 8 ) 5 . 7 2 E - 1 0 ;C 2 5 ( 1 8 3 3 ) 1 . 9 8 6 4 E - 1 0 ;C 2 6 ( 2 3 3 2 ) 2 . 0 0 6 E - 1 0 ;E 5 ( 2 0 0 0 1 9 ) 2 E + 0 5 ;E 6 ( 2 4 0 0 2 3 ) 2 E + 0 5 ;
/ * THE FOURTH B I Q U A D ; * /5 2 5 ( 2 9 0 ) CLK;5 2 6 ( 2 8 2 9 ) #CLK;5 2 7 ( 2 6 2 7 ) #CLK;5 2 8 ( 2 6 0 ) CLK;5 2 9 ( 3 3 0 ) CLK;5 3 0 ( 3 2 3 3 ) #CLK;5 3 1 ( 3 0 3 1 ) CLK;5 3 2 ( 3 0 0 ) # C L K ;C 7 ( 2 7 2 8 ) 2 . 0 E - 0 9 ;C8 ( 3 1 3 2 ) 2 . 0 E - 0 9 ;C 2 7 ( 2 4 3 1 ) 6 . 5 9 8 E - 1 0 ;C 2 8 ( 2 9 3 0 ) 1 . 4 6 E - 0 9 ;C 2 9 ( 2 7 3 2 ) 1 . 4 4 8 E - 1 0 ;C 3 0 ( 2 6 3 3 ) 1 . 4 6 E - 0 9 ;C 3 1 ( 2 5 2 6 ) 6 . 7 1 2 E - 1 0 ;E 7 ( 2 8 0 0 2 7 ) 2 E + 0 5 ;E 8 ( 3 2 0 0 3 1 ) 2 E + 0 5 ;END;
/ * S T E A D Y - S T A T E A N A L Y S I S : * /ANALYZE S S S ;
I N F R E Q 6 0 0 1 5 0 0 LOG 5 0 ;S E T V I AC 1 . 0 0 . 0 ;PLOT V D B ( 3 2 ) ;END;
END;
TITLE: FIFTH-ORDER SC ELLIPTIC LOWPASS FILTER CIRCUIT ; 140
/ * T H I S I S THE F I F T H - O R D E R SC E L L I P T I C L P F NETWORK [ F I G . 6 . 8 ] * / / * U S I N G LEAPFROG D E S I G N HAVING THE FOLLOWING S P E C I F I C A T I O N S : * / / * * P A SS B A N D FREQUENCY : 1 KHZ HAVING A R I P P L E OF 1 DB I N * / / * THE P A S S B A N D . P A S S B A N D G A I N OF U N I T Y * / / * *AT ALL F R E Q U E N C I E S O U T S I D E A 1 . 5 KHZ BANDWIDTH, THE * / / * FUNC TI ON SHOULD HAVE A MINIMUM ATTEN UATI ON OF 6 0 . 0 D B . * / / * *THE CLOCK FREQUENCY I S AT 5 KHZ. * / / * COMPONENT VALUES U S E D ARE THOSE OF M I N I M I Z E D TOTAL C A P A C I T O R S . * /
T I M I N G ;P E R I O D 2 E - 0 4 ;CLOCK CLK 1 ( 0 1 / 2 ) ; END;
C I R C U I T ;S I ( 1 2 ) CLK;S 2 ( 4 5 ) # C L K ;S 3 ( 4 9 ) CLK;S 4 ( 7 8 ) CLK;S 5 ( 6 7 ) # C L K ;
S 6 ( 5 0 ) CLK;
S 7 ( 6 0 ) CLK;S 8 ( 9 0 ) # C L K ;
S 9 ( 8 0 ) # C L K ;S 1 0 ( 7 1 8 ) CLK;S l l ( 1 7 1 6 ) CLK;S 1 2 ( 1 7 0 ) # C L K ;S 1 3 ( 1 8 0 ) # C L K ;S 1 4 ( 7 1 0 ) CLK;S 1 5 ( 1 0 0 ) # C L K ;S 1 6 ( 1 1 0 ) # C L K ;S I 7 ( 1 1 1 2 ) CLK;S 1 8 ( 1 2 1 3 ) CLK;
S 1 9 ( 1 4 . 1 5 ) # C L K ;S 2 0 ( 1 3 0 ) #CLK;S 2 1 ( 1 4 0 ) CLK;S 2 2 ( 1 5 2 4 ) # C L K ;
S 2 3 ( 2 3 2 2 ) CLK;S 2 4 ( 2 4 0 ) CLK;S 2 5 ( 2 3 0 ) # C L K ;S 2 6 ( 1 6 1 9 ) CLK;S 2 7 ( 2 0 2 1 ) CLK;S 2 8 ( 1 9 0 ) #CLK?
S 2 9 ( 2 0 0 ) #CLK;
5 3 0 ( 2 1 3 0 ) CLK;5 3 1 ( 2 9 2 8 ) CLK;5 3 2 ( 3 0 0 ) #CLK;5 3 3 ( 2 9 0 ) #CLK;5 3 4 ( 2 2 2 5 ) CLK;5 3 5 ( 2 6 2 7 ) #CLK;5 3 6 ( 2 5 0 ) # C L K ;5 3 7 ( 2 6 0 ) CLK;5 3 8 ( 2 7 3 8 ) #CLK;5 3 9 ( 3 7 3 6 ) CLK;5 4 0 ( 3 8 0 ) CLK;5 4 1 ( 3 7 0 ) #CLK;5 4 2 ( 2 8 3 1 ) CLK;5 4 3 ( 3 2 3 3 ) CLK;5 4 4 ( 3 1 0 ) #CLK;5 4 5 ( 3 2 0 ) #CLK;5 4 6 ( 3 3 3 4 ) CLK;5 4 7 ( 3 5 3 6 ) CLK;5 4 8 ( 3 4 0 ) #CLK;5 4 9 ( 3 5 0 ) #CLK;CO ( 2 0 ) 2 . 0 ;C I A ( 5 6 ) 0 . 0 ;C l ( 9 8 ) 2 . 1 2 2 8 ;CS ( 1 0 1 1 ) 2 . 2 2 8 9 0 1 9 ; C2 ( 1 8 1 7 ) 3 . 9 2 7 1 1 2 7 ; C3 ( 7 1 2 ) 3 . 1 0 0 1 7 9 7 ;C4 ( 1 3 1 4 ) 1 . 3 1 2 4 9 9 9 ; C5 ( 2 4 2 3 ) 1 . 0 ;C6 ( 1 5 1 6 ) 1 . 4 5 7 7 ;Cl ( 1 9 2 0 ) 8 . 6 9 1 9 2 9 ;C8 ( 3 0 2 9 ) 7 . 0 4 7 5 1 0 3 ; C9 ( 2 2 2 1 ) 1 0 . 8 0 2 3 7 6 ; CI O ( 2 5 2 6 ) 1 . 6 ;C l l ( 3 8 3 7 ) 1 . 0 ;C 1 2 ( 2 7 2 8 ) 2 . 1 1 8 7 5 ; C 1 3 ( 3 1 3 2 ) 4 . 4 0 4 6 9 3 8 ; C 1 4 ( 3 3 3 6 ) 1 . 9 5 7 5 6 6 7 ; C 1 5 ( 1 2 2 1 ) 2 . 9 0 4 9 7 2 8 ; C 1 6 ( 7 2 2 ) 1 . 0 ;C 1 7 ( 2 1 3 6 ) 1 . 0 . ;C I S ( 2 2 3 3 ) 1 . 0 ;CL ( 3 4 3 5 ) 1 . 4 6 8 2 3 1 2 ; E l ( 4 0 2 4 ) 2 E + 0 5 ;E2 ( 1 2 0 0 7 ) 2 E + 0 5 ;E 3 ( 1 6 0 0 1 5 ) 2 E + 0 5 ; E 4 ( 2 2 0 0 2 1 ) 2 E + 0 5 ; E 5 ( 2 8 0 0 2 7 ) 2 E + 0 5 ; E 6 ( 3 6 0 0 3 3 ) 2 E + 0 5 ; V I ( 1 0 ) ;END;
/ * S T E A D Y - S T A T E A N A L Y S I S ; ANALYZE S S S ;
INFREQ 2 0 0 3 0 0 0 LOG 5 0 ; SET V I AC 1 . 0 0 . 0 ;SAMPLE I N P U T HOLD 1 1 / 2 + ; PLOT V D B ( 3 6 ) ;END;
END;
APPENDIX B
COMPONENT SPECIFICATIONS
2) HARRIS
143
HI-201Quad SPST CMOS Analog Switch
Features• Analog Voltage Range........................................... ±15V• Analog Current Range........................................ 80mA• Turn-On Time........................................................ 185ns• Low Rqn ...................................................................550• Low Power Dissipation ...................................... 15mW• TTL/CMOS Compatible
A pplica tion s» High Frequency Analog Switching• Sample and Hold Circuits• Digital Filters• Operational Amplifier Gain Switching Networks
D escrip tionHI-201 is a monolithic device comprising four independently selectable SPST switches which feature fast switching speeds (185ns) combined with low power dissipation (15mW at +25°C). Each switch provides low “ON" resistance operation for input signal voltages up to the supply rails and for signal currents up to 80mA. Employing Dielectric Isolation and CMOS processing, HI-201 operates without any applications problems induced by latch-up or SCR mode phenomena.All devices provide break-before-make switching and are TTL and CMOS compatible for maximum application versatility. HI-201 is an ideal component for use in high frequency analog switching. Typical applications include signal path switching, sample and hold circuit, digital filters, and op amp gain switching networks.HI-201 is available in a 16 lead Dual-In-Line package. HI-201-2 is specified from -55°C to +125°C while HI- 201-5 operates from 0°C to +75°C. HI-201 is functionally and pin compatible with other available "200 series" switches.
PinoutH M - 2 0 1 - X
T O P V IE W
O U T 1
— 13
O U T 4
8 - - O '1
A2O U T 2
IN 2
V*
V R E F
IN 3
O U T 3
A 3
Functional Diagram
TYPlCAl SWITCH
IN
SWITCH OPEN FOR 10GIC HIGH
C A U T IO N T h e s e d e v i c e s a r e s e n s i t i v e to e l e c t r o s t a t i c d i s c h a r g e P r o p e r I C h a n d U n g p r o c e d u r e s s h o u l d b e lo A o w e d
144
S p ec ifica tio n s H I-201
Absolute Maximum RatingsS u p p l y V o l t a g e B e t w e e n P i n s 4 a n d 1 3 ...................................... 4 4 V ( ± 2 2 )
V r e f 10 G r o u n d ............................................................................................ + 2 0 V . - 5 V
D ig i ta l I n p u t V o l t a g e ....................................................................♦ V g u P P L Y + 4 V
- ^ S U P P L Y - 4 VA n a lo g I n p u t V o l t a g e ( O n e S w i t c h ) ..............................+VSUPPLY + 2 OV
- V g u P P L Y - 2 0 VA n a lo g C u r r e n t — C o n t i n u o u s . P e a k ................................... 3 0 m A . B O m AT o ta l D i s s i p a t i o n * ............................................................................................... 7 5 0 m W
Operating Temperature RangeH I - 2 0 1 - 2 ......................................................................................... - 5 5 ° C to + 1 2 5 ° CH I - 2 0 1 - 4 ............................................................................................ - 2 5 0 C to + 8 5 ° C
H I - 2 0 1 - 5 .................................................................................................... 0 ° C to + 7 5 ° C
S t o r a g e T e m p e r a t u r e .............................................................. - 6 5 ° C t o + 1 5 0 ° C
'D e r a t e 8 m W / ° C A b o v e T a " 7 5 ° C
Electrical Specifications U n l e s s o t h e r w i s e S p e c i f i e d S u p p l i e s = ♦ 1 5V . - 1 5 V ; V r e f = O p e n ; V a h ( L o g ic L e v e l H ig h ) = 2 4V .
V a l ( L o g ic L e v e l L o w ) = + 0 8 VF o r T e s t C o n d i t i o n s C o n s u l t P e f o r m a n c e C h a r a c t e r i s t i c s
P A R A M E T E R T E M P
H I - 2 0 1 - 2
- 5 5 ° C t o + 1 2 5 ° C
H I - 2 0 1 - 5 * *
0 ° C t o + 7 5 ° C
U N I T SM IN T Y P M A X M IN T Y P M A X
A N A L O G S W IT C H C H A R A C T E R I S T I C S
V g , A n a lo g S ig n a l R a n g e F u ll - 1 5 - + 1 5 - 1 5 - + 1 5 V
R O N - O n R e s i s t a n c e ( N o te 1) + 2 5 ° C - 5 5 7 0 - 5 5 8 0 nF u ll - 8 0 1 0 0 - 7 5 1 0 0 n
•S (O F F )- O ff I n p u t L e a k a g e C u r r e n t ( N o te 6 ) + 2 5 ° C - 2 5 - 2 5 0 nA
F u ll - - 5 0 0 - - 2 5 0 nA
ID (O F F )- O ff O u t p u t L e a k a g e C u r r e n t ( N o te 6 ) + 2 5 ° C - 2 5 - 2 5 0 nA
F u ll - 3 5 5 0 0 - 3 5 2 5 0 n A
'D (O N )- O n L e a k a g e C u r r e n t ( N o te 6 ) + 2 5 ° C - 2 5 - 2 5 0 nA
F u ll - - 5 0 0 - - 2 5 0 nA
D IG IT A L IN P U T C H A R A C T E R I S T I C S
Va l - I n p u t L o w T h r e s h o l d F u ll - - 0 8 - - 0 .8 V
VA H - I n p u t H ig h T h r e s h o l d F u n 2 4 - - 2 4 - - V
Ia - I n p u t L e a k a g e C u r r e n t (H ig h o r L o w ) ( N o te 2 ) F u ll - - 1 .0 - - 1 .0 UA
S W IT C H IN G C H A R A C T E R I S T I C S
'O P E N - B r e a k - B e f o r e M a k e D e la y ( N o te 3 ) + 2 5 ° C - 3 0 - - 3 0 - n s
'O N - S w i t c h O n T im e + 2 5 ° C - 1 8 5 5 0 0 - 1 8 5 - n s
F u ll - 1 0 0 0 - - 1 0 0 0 - n s
'O F F - S w i t c h O ff T im e + 2 5 ° C - 2 2 0 5 0 0 - 2 2 0 - n s
F u ll - 1 0 0 0 - - 1 0 0 0 - n s
“ O ff I s o l a t i o n " ( N o te 4 ) + 2 5 ° C - 8 0 - - 8 0 - d B
C s ( O F F ) - I n p u t S w i t c h C a p a c i t a n c e ♦ 2 5 ° C - 5 .5 - - 5 .5 - P F
O D ( O F F ) ' 1 O u t p u t S w i t c h C a p a c i t a n c e + 2 5 ° C - 5 .5 - - 5 5 - p F
C D (O N ) . J ♦ 2 5 ° C - 11 - - 11 - P F
C a - D ig i ta l I n p u t C a p a c i t a n c e + 2 5 ° C - 5 - - 5 - P F
C D S ( O F F ) . D r a i n - T o - S o u r c e C a p a c i t a n c e + 2 5 ° C - 0 5 - - 0 5 - P F
P O W E R R E Q U I R E M E N T S ( N o te 5 )
P q , P o w e r D i s s ip a t io n + 2 5 ° C - 1 5 - - 1 5 - m W
FuH - - 6 0 - - 6 0 m W
l+ , C u r r e n t ( P in 1 3 ) + 2 5 ° C - 0 5 - - 0 . 5 - m A
FuH - - 2 .0 - - 2 .0 m A
I- . C u r r e n t (P in 4 ) + 2 5 ° C - 0 . 5 - - 0 . 5 - m A
F u ll - - 2 . 0 - - 2 .0 m A
N O TES:
1. V q u j = ± 1 0 V . Iq u T ■ 1 m A 4 VA ■ 5 V . “ ' k f l . C l ■ 1 0 p F , V g " 3 v R M S - 1 “ 1 0 0 k H z .
2 . D ig ita l I n p u t s a r e M O S g a t e s — T y p ic a l L e a k a g e i s L e s s T h a n In A . S . V * - 4 -3V o r Va ■ OV fo r All S w i t c h e s .
3 . Va h “ 4 .0 V . & R e f e r t o L e a k a g e C u r r e n t M e a s u r e m e n t D ia g r a m o n P a g e 3 - 8 .
" N O T E : H I - 2 0 1 - 4 H a s S a m e S p e c i f c a l o n s a s H I - 2 0 1 - 5 O v e r t h e T e m p e r a tu r e R a n g e - 2 5 ° C to + 8 5 ° C
MOTOROLA
Specif icat ions and Appl ica t ions In forma t ion
MONOLITHIC JFET INPUT OPERATIONAL AMPLIFIERS
T h e s e i n t e r n a l l y c o m p e n s a t e d o p e r a t i o n a l a m p l i f i e r s i n c o r p o r a t e
h ig h ly m a t c h e d J F E T d e v ic e s o n t h e s a m e c h i p w i t h s t a n d a r d
b i p o la r t r a n s i s t o r s . T h e J F E T d e v ic e s e n h a n c e t h e i n p u t c h a r a c
t e r i s t i c s o f t h e s e o p e r a t i o n a l a m p l i f i e r s b y m o r e t h a n a n o r d e r
o f m a g n i t u d e o v e r c o n v e n t i o n a l a m p l i f i e r s
T h is s e r i e s o f o p a m p s c o m b i n e s t h e l o w c u r r e n t c h a r a c t e r i s t i c s
t y p i c a l o f F E T a m p l i f i e r s w i t h t h e l o w i n i t i a l o f f s e t v o l t a g e a n d
o f f s e t v o l t a g e s t a b i l i t y o f b i p o l a r a m p l i f i e r s . A ls o , n u l l i n g t h e o f f s e t
v o l ta g e d o e s n o t d e g r a d e t h e d r i f t o r c o m m o n m o d e r e j e c t i o n .
• L o w I n p u t B ia s C u r r e n t — 3 0 p A
• L o w I n p u t O f f s e t C u r r e n t — 3 . 0 p A
• L o w I n p u t O f f s e t V o l t a g e — 1 .0 m V
• T e m p e r a t u r e C o m p e n s a t i o n o f I n p u t O f f s e t V o l t a g e -
3 . 0 n V / ° C
• L o w I n p u t N o i s e C u r r e n t - 0 .0 1 pA/\/iTz• H ig h I n p u t I m p e d a n c e — 1 0 ^ 1 2
• H ig h C o m m o n M o d e R e j e c t i o n R a t i o - 1 0 0 d B
• H ig h D C V o l t a g e G a m - 1 0 6 d B
SERIES FEATURES
• L F 3 5 5 /3 5 5 B — L o w P o w e r S u p p l y C u r r e n t
• L F 3 5 6 /3 5 6 B — W i d e B a n d w i d t h
e L F 3 5 7 /3 5 7 B — W i d e r B a n d w i d t h D e c o m p e n s a t e d ( A y m i n " 5 )
L F 3 5 S 3 5 5 B L F 3 5 6 3 5 6 B L F 3 5 7 /3 5 7 B F a s t S e t t l i n g T i m e t o 0 . 0 1 % 4 . 0 / i s 1 .5 # is 1 5 # isF a s t S l e w R a t e 5 . 0 V / p s 1 2 V > s 5 0 V ' / i sW i d e G a i n B a n d w i d t h 2 .5 M H z _ 5 . 0 M H r _ 2 0 M H z
L o w I n p u t N o i s e V o l t a g e 2 0 n V / v 'H z 1 2 n W V H z 1 2 n V / V H z
O R D E R IN G IN FO R M A T IO N
D e v ic e T e m p e r a tu r e fU n g e P e c t e g e
LF355B H .H 0 to ♦ T O T M et ei C a nL F 3 S 5 B J J 0 to ♦ 7(TC C e ra m ic DIP
LF356BH .H O to ♦ 7<rc M eta l C anL F 3 5 6 B J J o t o » t o t : C e ra m ic DIP
LF357B H .H o to ♦ 7<rc M el e l C a nL F 3 5 7 B J J o t o * T trc C e ra m ic DIP
LF355, LF356, LF357*LF355B,
LF356B, LF357B*
MONOLITHIC JFET OPERATIONAL AMPLIFIERS
S I L I C O N M O N O L I T H IC I N T E G R A T E D C I R C U I T S
H SU FFIX M ETA L PA CK A G E
C A SE 6 0 1 -0 4
] O f lw r N u
Invt In p u t
N o n in v t In p u t
B 1o r t te t Null
V EE(T o p V iew )
J S U FFIXC E R A M IC PA CK A G E
C A SE 6 9 3 -0 2
O n s e t Null Inv l In p u t
N o n in v t In p u t
V EE
NC
vccO u tp u t O ffse t Null
A P P L I C A T I O N S
The LF senes is suggested for ell general purpose FET input amplifier requirem ents where precision and frequency response flexibility are of prim e im portance.
Specific applications include:
• Sample and Hold Circuits• High Impedance Buffers• Fast O/A and A/D Converters• Precision High Speed Integrators• W ideband. Low Noise. Low Drift Amplifiers
•NOTE: The LF357 357B are designed for wider bendwidth epplicetione They ere decompensated (Aymin • &)
MOTOROLA LINEAR/INTERFACE DEVICES
LF355, LF356, LF357, LF355B, LF356B, LF357B
D C E L E C T R IC A L C H A R A C T E R I S T I C S IV C c - 1 5 t o 2 0 V. V EE - - 1 5 t o 2 0 V l o r L F 3 5 5 B 3 5 6 B 3 5 7 B ; V c c - 1 5 V , V E E -- 1 5 V f o r L F 3 5 5 3 5 6 3 5 7 ; T * - O ’C t o ♦ 7 0 ‘C u n l e s s o t h e r w i s e n o t e d )
C h a r a c t e r i s t i c S y m b o l
U T S S B. * 8 / 7 8 L F 3 5 S 6 /7
U n itM in T y p M a x M in T y p M a x
I n p u t O f f s e t V o l ta g e (R g ■ 5 0 11. Vc m ■ VlO m V|T A - 2 5 'C ) 3 0 5 0 3 0 10(O v e r T e m p e r a tu r e ) — — 6 5 — — 13
A v e r a g e T e m p e r a tu r e C o e f f ic ie n t o f I n p u t O f f s e t •W j o -IT — 5 0 — — 5 .0 — nVrcV o lta g e( f ig = 5 0 0 )
C h a n g e in A v e r a g e TC w i th V j q A d ju s t A T C A V io — 0 5 — — 0 5 — tivrc(R g = 5 0 111 (N o te 2) p e r m V
I n p u t O f f s e t C u r r e n t (Vc m = 0) (N o te 3) ■lO( T j - 2 5 'C ) — 3 0 2 0 — 3 .0 5 0 PA( T j « 70°C ) — — 1.0 — — 2 .0 nA
I n p u t B ia s C u r r e n t (V q m ■ 0) (N o te 3) ' IB( T j = 2 5 ’CI — 3 0 1 0 0 — 3 0 2 0 0 pA( T j * 7CTC) — — 5 0 — — 8 .0 nA
I n p u t R e s i s t a n c e ( T j - 25°C ) n — 1 0 '2 — — 1 0 1 2 — nL a rg e S ig n a l V o l ta g e G a in a v o l V /m V
(V0 - * 10 V. RL - 2 .0 k. V c c - 15 V.VEE - - 1 5 V)(TA - 25*C) 5 0 2 0 0 — 2 5 2 0 0 —
(0°C < TA < + 7 0 * 0 2 5 — — 15 — —O u tp u t V o l ta g e S w in g Vo V
( V c c = 15 V. V EE = - 1 5 V, R l = 10 k fl) = 12 = 13 — = 12 = 13 —(VC C - 15 V. V EE = - 15 V, RL = 2 k i l l 2 10 = 12 — = 10 = 12 —
In p u t C o m m o n - M o d e V o l ta g e R a n g e VlCR = 11 + 15.1 — = 10 * 1 5 .1 — V(VC c = 15 V. VEE - - 1 5 V) - 12 0 - 12 .0
C o m m o n - M o d e R e je c t io n R a tio C M R R 8 5 100 — 8 0 1 00 — dB
S u p p ly V o l ta g e R e je c t io n R a t io (N o te 4) RSRR 8 5 1 00 — 8 0 100 — dB
S u p p ly C u r r e n t (TA - 25*C. V c c " 1 5 V. •dVEE = - 1 5 V)L F355B 3 5 5 — 2 0 4 .0 — 2 0 4 0L F 3 5 6 B /3 5 7 B — 5 .0 7 .0 — — —L F 3 5 6 .3 5 7 — — — — 5 0 10
A C E L E C T R IC A L C H A R A C T E R I S T I C S (VC C = 1 5 V. VEE - - I S V. TA - 25"C )
U T S S B 3 S 5 L F 3 5 6 B .3 5 6 L F 3 5 7 B 3 5 7
C h a r a c t e r i s t i c S y m b o l M in T y p M a x M in T y p M a x M in T y p M a x U n it
S le w R a te ( N o te 5) S R V/jaS(Av = 1) L F 3 5 5 /3 5 6 — 5 0 — 7 .5 12 — — — —
(A y = 5 ) L F357 3 0 5 0 —
G a in -B a n d w id th P r o d u c t G B W — 2 5 — — 5 .0 — — 2 0 — M Hz
S e t t l in g T im e to 0 .0 1 % (N o te 6) • • - 4 0 — — 1.5 — — 1.6 —
E q u iv a le n t In p u t N o is e V o l ta g e • n nV /vTTz(R g = 1 0 0 11. f - 10 0 Hz) — 2 5 — — 15 — — 15 —(R g = 1 00 n . f = 1 0 0 0 Hz) — 2 0 — — 12 — — 12 —
E q u iv a le n t In p u t N o is e C u r r e n t in p A /V H l(f - 1 00 Hz) 0 0 1 0 0 1 0.01(f = 1 0 0 0 Hz) — 0.0 1 — — 0 .01 — — 0.01 —
I n p u t C a p a c i t a n c e Ci - 3 .0 — - 3 .0 - - 3 .0 - p F
NOTTS(1) U n le s s o th e r w is e s p e c if ie d , th e e b s o lu te m a x im u m n e g a t iv e in p u t
v o l ta g e is e q u a l to t h e n e g a t iv e p o w e r s u p p ly121 T h e t e m p e r a tu r e c o e f f ic ie n t o f t h e a d ju s t e d in p u t o f f s e t v o l ta g e
c h a n g e s o n ly a s m a ll a m o u n t 10.6 *iV/*C ty p ic e lty l fo r e a c h m V o f a d ju s tm e n t f ro m i ts o r ig in a l u n a d ju s t e d v a lu e C o m m o n - m o d e r e je c t io n a n d o p e n lo o p v o l ta g e g a in a r e a l s o u n a f f e c te d b y o f fs e t a d ju s tm e n t .
131 T h e in p u t b ia s c u r r e n t s a p p r o x im a te ly d o u b le fo r e v e r y 1 0 T r i s e in ju n c t io n t e m p e r a tu r e . T j . D u e to l im ite d t e s t t im e , t h e in p u t b ia s c u r r e n ts a r e c o r r e la te d to ju n c t io n t e m p e r a tu r e . U s e o f a h e a t s in k is r e c o m m e n d e d if in p u t b ia s c u r r e n t is t o b e k e p t to a m in im u m .
(4) S u p p ly v o l ta g e r e je c t io n r a t io is m e a s u r e d fo r b o th s u p p ly m a g n i
tu d e s in c r e a s in g o r d e c r e a s in g s im u l ta n e o u s ly , in a c c o r d a n c e w ith c o m m o n p ra c t ic e
151 T h e M in . s le w r a te l im its a p p ly fo r t h e LF366B a n d th e LF357B . b u t d o n o t a p p ly fo r t h e LF3S6 o r LF367.
1*1 S e t t l in g l im e Is d e f in e d h e re , fo r a u n ity g a in I n v e r te r c o n n e c t io n u s in g 2 .0 k r e s i s to r s fo r th e I F 3 5 5 * It is t h e t im e r e q u i r e d fo r th e e r r o r v o l ta g e ( th e v o l ta g e e l t h e in v e r t in g in p u t p in o n th e a m p lif ie r ) t o s e t t l e t o w ith in 0 0 1 % o f its f in a l v a lu e f ro m th e t im e a 10 V s te p in p u t i s a p p l ie d to t h e In v e r te r F o r t h e LF357, A * - - 6 .0 . t h e f e e d b a c k r e s i s to r f ro m o u tp u t to In p u t is 2 .0 k a n d th e o u tp u t s t e p Is 10 V ( s e e s e t t l in g t u n e t e s t c ircu it) .
MOTOROLA LINEAR/INTERFACE DEVICES
147
Signetics 74221MultivibratorDual Monostable Multivibrator P ro d u c t S p ec if ica tio n
T Y P ET Y P IC A L P R O P A G A T IO N
D E L A YT Y P IC A L S U P P L Y C U R R E N T
(T O T A L )
7 4 2 2 1 4 2 n s 36mA
ORDERING CODE
P A C K A G E SC O M M E R C IA L R A N G E
V c c = 5 V 1 5 % ; T A = 0 ° C to + 7 0 ° C
P l a s t ic D IP N 7 4 2 2 1 N
P l a s t ic S O - 1 6 N 7 4 2 2 1 D
NOTE:Few information regarding devices processed to Military Speciticetione. see the Signetics Military Products Data Manual
Logic Products
FEATURESe Pulse width variance Is typically
less than ±0.5% for 98% of the units
• The '221 demonstrates electrical and switching characteristics that are virtually Identical to the '121 one-shots
e Pln-out Is Identical to the '123• Overriding Reset terminates
output pulse• B Input has hysteresis for
Improved noise Immunity• Maximum pulse width:
54221: 21 seconds 74221: 28 seconds
DESCRIPTIONThe '221 is a dual monostable multivibrator with performance characteristics virtually identical to those of the '121. Each multivibrator features an active LOW going edge input (A) and an active HIGH going edge input (B), either of which can be used as an Enable input.Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hys
teresis) for the B input allows jitter-free triggering from inputs with transition rates as slow as 1 volt/second, providing the circuit with excellent noise immunity of typically 1.2 volts. A high immunity to Vcc noise of typically 1.5 volts is also provided by internal latching circuitry.Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components. The output pulses can be terminated by the overriding active LOW Reset (Rd). Input pulses may be of any duration relative to the output pulse. Output pulse length may be varied from
35 nanoseconds to the maximums shown in the FEATURES by choosing appropriate timing components. With Rex, - 2kf2 and Cext - 0, an output pulse of typically 30 nanoseconds is achieved which may be used as a dc triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length.Pulse width stability is achieved through internal compensation and is virtually independent of Vcc and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components.
PIN CONFIGURATION
A, e HI VCC
•i Cl H) "*xVC*:l1"oi CC 3 c««tiOi E m o,o, (T 33 oi
ce*i2 CE 33 "02
"e*l,ce*l2 E 33 2
ONO E 3 *2
LOGIC SYMBOL
V cc - Pm 16 C w - p e n 14. 6 GND - Pm 8 C , * / ^ - Pm* 15. 7
LOGIC SYMBOL (IEEE/IEC)
2 & 1-TL13
IT
R
>
TX- cx—X—CX/AX
10 & 1 J~L S
l i dXT
R
l x - cx- x - cxwx
148
Signetics Logic Products Product Specification
Multivibrator 74221
J i t t e r - f r e e o p e r a t i o n is m a i n t a i n e d o v e r t h e
full t e m p e r a t u r e a n d V c c r a n g e s fo r m o r e t h a n s ix d e c a d e s o f t im in g c a p a c i t a n c e ( lO p F t o lO p F ) a n d m o r e t h a n o n e d e c a d e o f tim in g r e s i s t a n c e (2 k fZ to 3 0 k f i fo r t h e 5 4 2 2 1 a n d
2 k f i to 4 0 k f 2 fo r t h e 7 4 2 2 1 ) . T h r o u g h o u t
t h e s e r a n g e s , p u l s e w id th is d e f i n e d b y th e
fo llo w in g r e l a t i o n s h ip : ( s e e F ig u r e A)
t w ( o u t ) - C ex1R e r t l n 2 tw ( o u t) — 0 .7 C erTFtex1
In c i r c u i t s w h e r e p u l s e c u to f f i s n o t c r i t ic a l, t im in g c a p a c i t a n c e u p to lO O O p F a n d tim in g
r e s i s t a n c e a s lo w a s 1 .4 k f2 m a y b e u s e d
P m a s s i g n m e n t s fo r t h e s e d e v i c e s a r e id e n t i
c a l t o t h o s e o f t h e ‘ 1 2 3 s o t h a t t h e '2 2 1 c a n
b e s u b s t i t u t e d fo r t h o s e p r o d u c t s in s y s t e m s n o t u s in g t h e r e t r ig g e r b y m e r e ly c h a n g in g t h e
v a lu e o f R ex t a n d / o r C ex|.
FUNCTION TABLE ( E a c h m o n o s t a b l e )
I N P U T S O U T P U T S
R o A B 0 5
L X X L HX H X L HX X L L HH L T JT "LTH l H I fT L H _TL I f
In a d d i t i o n , s e e d e s c r i p t i o n a n ds w i tc h in g c h a r a c t e r i s t i c s .
H - HIGH voltage level L - LOW voltage level X - Don’t care
T - LOW-to-HIGH transition 1 - HIGH-to-LOW transition
_ T L - one HlGH-ievei pulse "LT - one LOW-level pulse
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
P IN S D E S C R IP T IO N 7 4
A I n p u t l u l
B , R d I n p u ts 2 u l
All O u t p u t s lO u l
NOTE:A 74 unit load (ul) is understood to be 40pA lIH and — 1.6ntA Iil-
* 1 0 0 » s
F i g u r e 1. O u t p u t P u l s e W id t h v s T i m i n g R e s i s t o r V a lu e
ABSOLUTE MAXIMUM RATINGS ( O v e r o p e r a t i n g f r e e - a i r t e m p e r a t u r e r a n g e u n l e s s o t h e r w i s e n o t e d )
P A R A M E T E R 7 4 U N IT
V c c S u p p ly v o l ta g e 7 .0 V
V,N I n p u t v o l ta g e - 0 . 5 t o + 5 . 5 V
•in I n p u t c u r r e n t - 3 0 to + 5 m A
VOUT V o l t a g e a p p l i e d to o u t p u t in H IG H o u tp u t s t a t e - 0 . 5 t o + V c c V
T a O p e r a t i n g f r e e - a i r t e m p e r a t u r e r a n g e 0 to 7 0 •c
RECOMMENDED OPERATING CONDITIONS
P A R A M E T E R7 4
U N ITM in N o m M a x
V c c S u p p ly v o l ta g e 4 .7 5 5 .0 5 .2 5 V
•iK I n p u t c la m p c u r r e n t - 1 2 m A
•OH H IG H -le v e l o u t p u t c u r r e n t - 8 0 0 p A
•OL L O W -le v e l o u t p u t c u r r e n t 1 6 m A
T a O p e r a t i n g f r e e a ir t e m p e r a t u r e 0 7 0 •c
149
TYP ES S N 5 4 A L S 1 1 2 A , S N 5 4 A S 1 1 2 , S N 7 4 A L S 1 1 2 A , S N 7 4 A S 1 1 2 DUAL J K NEGATIVE EDGE TRIGGERED FLIP FLOPS
WITH CLEAR AND PRESETD 2 6 6 1 . DECEMBER 1 9 8 2
• Fully Buffered to Offer Maximum Isolation from External Disturbance
• Package Options Include Both Plastic and Ceramic Carriers In Addition to Plastic and Ceramic DIPs.
• Dependable Texas Instruments Quality and Reliability
T Y PIC A L M A X IM U M
CLO CK FR EQ U EN C Y
•A L S 1 1 2 A 6 0 M H z
• A S 1 1 2 1 7 6 M H z
T Y PIC A L PO W E R
D IS S IP A T IO N
PER FLIP FL O P
6 m W
9 6 m W
8 N 6 4 A L S 1 1 2 A . S N S 4 A S 1 1 2 . . . J PA C K A G E
S N 7 4 A L S 1 1 2 A . S N 7 4 A S 1 1 2 . . . N PA C K A G E
(T O P VIEW )
descriptionT h e s e d e v i c e s c o n t a i n t w o i n d e p e n d e n t J - K n e g a t i v e - e d g e -
t r i g g e r e d f l i p - f l o p s . A l o w l e v e l a t t h e P r e s e t o r C l e a r i n p u t s s e t s
o r r e s e t s t h e o u t p u t s r e g a r d l e s s o f t h e l e v e l s o f t h e o t h e r i n p u t s .
W h e n P r e s e t a n d C l e a r a r e i n a c t i v e ( h ig h ) , d a t a a t t h e J a n d K i n p u t s m e e t i n g t h e s e t u p t i m e r e q u i r e m e n t s a r e t r a n s f e r r e d t o t h e
o u t p u t s o n t h e n e g a t i v e g o i n g e d g e o f t h e c l o c k p u l s e . C l o c k
t r i g g e r i n g o c c u r s a t a v o l t a g e l e v e l a n d i s n o t d i r e c t l y r e l a t e d t o
t h e r i s e t i m e o f t h e c lo c k p u l s e . F o l lo w in g t h e h o l d t i m e i n t e r v a l ,
d a t a a t t h e J a n d K i n p u t s m a y b e c h a n g e d w i t h o u t a f f e c t i n g t h e
l e v e l s a t t h e o u t p u t s . T h e s e v e r s a t i l e f l i p - f l o p s c a n p e r f o r m a s t o g g l e f l i p - f l o p s b y t y i n g J a n d K h i g h .
T h e S N 5 4 A L S 1 1 2 A a n d S N 5 4 A S 1 1 2 a r e c h a r a c t e r i z e d f o r
o p e r a t i o n o v e r t h e fu ll m i l i t a r y t e m p e r a t u r e r a n g e o f - 5 5 ° C t o
1 2 5 ° C . T h e S N 7 4 A L S 1 1 2 A a n d S N 7 4 A S 1 1 2 a r e c h a r a c t e r i z e d
f o r o p e r a t i o n f r o m 0 ° C t o 7 0 ° C .
S N 6 4 A L S 1 1 2 A . S N 5 4 A S 1 1 2 . . . FH PA CK A G E
S N 7 4 A L S 1 1 2 A . S N 7 4 A S 1 1 2 . . . FN PA CK A G E
(T O P VIEW )
% up* O O u b
3 2 1 2 0 19
IB [ 2 C L R
17 [ 2 C L K
16 [ N C
1 6 [ 2 K
14 [ 2 J
FU N C T IO N TA BLE
IN PU T S O U T P U T S
PRE CLR CLK J K 0 9L H X X X H LH L X X X L H
L L X X X H * H *
H H l L L 0 0 SoH H 1 H L H LH H 1 L H L H
H ' H 1 H H TO G G LE
H H H X X 0 0 Qo
•T he ou tpu t levels in this conhgureuon ere not g u eren teed to m ee t th e nw w rxxn levels (or Vq h It the low s st P rese t end Cleer ere neer VIL m esim um F urtherm ore, ttws configuretlon Is nonststX e. the t is. It wSI not persist w hen either P rese t or O e s r re turns to Its Ineclive Ihighl level
NC — N o m te m e l c o n n e c t io n
logic symbol
1CLK^ - I S L i o
2CLK
Pm num bers show n ere (or J end N peckeges
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)
S u p p l y v o l t a g e . V c c ............................................................................................................................................................................................................................ 7 v
I n p u t v o l t a g e ................................................................................................................................................................................................................................................. 7 V
O p e r a t i n g f r e e - a i r t e m p e r a t u r e r a n g e S N 5 4 A L S 1 1 2 A . S N 5 4 A S 1 1 2 ................................................................... - 6 5 " C t o 1 2 5 ° C
S N 7 4 A L S 1 1 2 A . S N 7 4 A S 1 1 2 ............................................................................. 0 ° C t o 7 0 ° C
S t o r a g e t e m p e r a t u r e r a n g e ........................................................................................................................................................................ - 6 5 ° C t o 1 5 0 ° C
150
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