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Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) Shivam Choudhary(sc3973)

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Page 1: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Switch ONAyush Jain (aj2672)

Donovan Chan(dc3095)Shivam Choudhary(sc3973)

Page 2: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

An extremely efficient Hardware Switch!!

““

Page 3: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Architecture ➔ Userspace generates

packets.

➔ Input module sorts and places in RAM(s).

➔ Scheduler avoids collisions between packets.

➔ Buffer stores data in output RAM(s).

Page 4: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Hardware Communication Protocol

Header Format

Page 5: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Hardware Scheduler - Single Input Queue

➔ Source & Destination modelled as 4 RAM(s) each.

➔ Individual scheduling to prevent collision.➔ Greedy,no optimization for head of line

blocking.

Page 6: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

➔ Modeled as 16 RAMs at the input. (Parallel Packet Switch)

➔ Destination still modelled as 4 RAMs➔ Prevents HOL, hence improves

throughput.➔ Requires additional hardware

complexity and storage.

Hardware Scheduler - PPS

Page 7: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

PPS vs Single Input Queue

Page 8: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

PPS vs Single Input Queue (contd.)

Worst-case Performance Average Performance Best-case Performance

➔ Better average case performance for PPS.

➔ Higher variance.

➔ Same for PPS and Single Input Queue.

➔ Such a case is theoretically less probable to occur.

Page 9: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Input Signals - wren, wraddress, data, rden, rdaddress.

Output Signals - q (Data occurs after one clock cycle)

Timing Diagrams - RAM(altsync)

Page 10: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Case: Signals for different output ports.

Timing Diagrams - Scheduler

Page 11: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Case: Signals for same output ports.

Timing Diagrams - Scheduler

Page 12: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Timing Diagrams - Full Suite

Page 13: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Validator

Page 14: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

DEMO

Page 15: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Results

Page 16: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Performance Constraints● RAMs take up three clock cycles to change from one read location to

another.● Transfers are restricted to 32 bits at a time because of ioctl calls.● Can also increase performance if we increase the number of parts at

the cost of hardware complexity.

Page 17: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Lessons Learned➔ It is named hard-ware for a

reason.

➔ Timing diagrams save time.

➔ Simulations may be far from

reality.

➔ You will often reduce to hard

problems in polynomial time.

➔ Documentations need a lot of

work.

Page 18: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Future Work➔ Analyze and compare the performance for a maximum bipartite

matching solution.➔ Implement DMA.➔ Produce test results for greater amount of data and different

scenarios.➔ Interface with Ethernet ports and test with real network.

Page 19: Switch ON - Columbia University · Switch ON Ayush Jain (aj2672) Donovan Chan(dc3095) ... Worst-case Performance Average Performance Best-case Performance Better average case performance

Thank You!!

Code available on Github: https://github.com/shivamchoudhary/SwitchON https://github.com/shivamchoudhary/SwitchONHW