Superscalar ProcessorsSuperscalar Processors

(Pictured above is the DEC Alpha 21064)

Presented by Jeffery AguiarPresented by Jeffery Aguiar

Purpose

Theory

Design

Implementation

Evaluation

Conclusion

Presentation Outline

Improve chip productivity

Reward the market with increased processor scalability

Develop without replacing current code & compilers

Optimize logic architecture

Purpose

Motivation: Complete multiple instructions per clock cycle to decrease ALU “idle” time

Employ multiple ALU’s & FPU’s to execute instructions

Reason why RISC over took CISC in the mid-1990s

Quick facts:

First implementation: Seymour Cray’s CDC 6600All CPU’s since 1998 are considered superscalar

History

“Parallelism” - multiple pipelines

Fundamental Processor Units (FPU)

Improves upon current techology

Dependency

Example code segments: Dependent: Independent: A + B = C x + y = z C + A = D n + k = p

Theory

●Fetch multiple instructions

●Decode/Evaluate dependencies

●Reorder code segment

●Execute

●Schematic:

Design

Apple Macintosh G5 (IBM 970FX chipset)

Vector Processing Unit (VPU) block diagram

Example: PowerPC

Weaknesses:

Dependencies (video games)

“Branch prediction is tricky business”

Strengths:

Independent variables

Strong basis in logic (video rendering)

Evaluation

Multiple instructions executed per cycle

Logic approach with hardware backing

One variable of the performance metric

Complicated when dealing with dependency

Conclusions

Smith, James. “The Microarchitecture of Superscalar Processors”

L. Gwennap, ‘‘PPC 604 Powers Past Pentium,’’ Microprocessor Report, pp. 5-8, Apr. 18, 1994.

J. K. F. Lee and A. J. Smith, ‘‘Branch Prediction Strategies and Branch Target Buffer Design,’’ IEEE Computer, vol. 17, pp. 6-22, January 1984.

References

Questions ?