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Optimizing Area, Delay, Power parameters for mixed CMOS design

Soumya Ranjan Mund

108cs062

This report is submitted as partial fulfillment of the requirements for the Bachelor of technology

degree of National Institute of Technology, Rourkela.

……………………………..

Signature of the supervisor

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Abstract

The main research area is of Low power VLSI circuits. As we know how much important the

power is in present day world. Many researches are going on how to reduce the power

dissipation,area, & delay. In the present day Deep Sub Micron Technology as number of

transistors is increasing day by day, power dissipation,area, & delay plays a major role in the

efficiency of the circuit. So designers have turned towards design of mixed CMOS circuits.

We can design a mixed CMOS circuit after separating the unate part & binate part of the inputs,

& then mapping the unate (non inverting) part using domino logic, & binate part using static

logic. Then we can optimize the static, & dynamic part to achieve better area,power, & delay.

Introduction

There are many approaches to design a CMOS like pure static or pure domino. The mixed

CMOS design we try to divide the circuit into a static part and a dynamic part and the combine

them both. Based on optimized values of area, power, & delay we choose the static part, &

dynamic part of the circuit. Generally, the mixed design is faster than pure static approach.

Key Terms Involved

CMOS

static CMOS

dynamic CMOS

mixed CMOS

domino logic

SIS tool

Graphviz

on the fly mapping

netlist

area, power, & delay

optimization

Description of the problem tackled

The whole problems can be divided into 7 sub-problems 1) Determining static & dynamic part

of the input file in .pla format using maxset unate decomposition algorithm. 2) Using SIS tool to

get the netlist for the static part of the input file by mapping it using a library (e.g. 22-1.genlib ).

3) Using netlist to construct a graph and demonstrate it using graphviz. 4) Using graph to

calculate the static area, power, & delay. 5) Doing on the fly mapping of the dynamic part using

domino logic & constructing a graph. 6) Using the graph to calculate the area, power, & delay of

dynamic part. 7) Optimizing the area, power, & delay.

Existing Approaches for above problems

There is a tool called SIS Tool. SIS is a logic synthesis package developed at the University of

California at Berkeley which allows interactive optimization of sequential digital circuits. The

SIS tool has many libraries for mapping circuits using pure static approach. The libraries such as

22-1.genlib, 44-1.genlib etc use NAND,NOT, & NOR gate to realize a circuit & can calculate

area, estimate power, & calculate delay. But, there is no such standard built in library till now

for mapping the circuits using domino logic which requires on the fly mapping.

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Challenges faced in solving the problem

Both unate & binate inputs can be realized using static logic but, only unate or non inverting

inputs can be realized using pure domino logic. So the first problem was to divide the inputs into

unate part, & binate part. Now,as there is no mapping library for domino logic implementation,

the next challenge is to make a mapping library for mapping unate functions using domino logic.

The mapping library should be able to map the optimized equation of the circuit( which can be

obtained from SIS tool) using on the fly technicque, & should be able to calculate area,estimate

power & delay.

Realization of circuits using static logic

The SIS tool can be used to find the netlist of a circuit. A netlist is a list which gives the

connectivity of the circuit. The netlist can be converted into a graph that is, the nodes of netlist

can be stored in graph data structure. In static logic the mapping is done using NAND, NOR, &

NOT gates.

This is how the nodes of the netlist are saved in graph data structure and can be converted into

graph.

Area, Power, & Delay Calculations:- The number of NAND, NOR, & NOT gates are

calculated from the graph and area, & power are calculated for the circuit using individual

values of these (which can be obtained from look up table).

For delay we find out the longest path from input to output node. In other words we calculate

the path with no slack.

NETLIST

[55] = v0' + v1'

[39] = v2' v4'

[76] = [39]'

[78] = v2' + v4'

[74] = [76]' + [78]'

[59] = [74]' + v3'

{v5.0} = [55]' [59]'

GRAPH

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Realization of circuits using domino logic

The mapping using domino logic is different from static logic implementation in terms of the

types of gates. In static logic the gates are NAND, NOR, & NOT. But, in domino the gates are

having different structure & can implement more functions in less area.

(NOT gate using static logic) (NOR gate using domino logic)

Features of Domino logic Implementation

1. They have smaller areas than conventional CMOS logic (as does all Dynamic Logic).

2. Parasitic capacitances are smaller so that higher operating speeds are possible.

3. Operation is free of glitches as each gate can make only one transition.

4. Only non-inverting structures are possible because of the presence of inverting buffer.

5. Charge distribution may be a problem.

The SIS tool can be used to find out the optimized equation of a circuit in SOP form. This

equation we can map using on the fly mapping technique. We present a sample mapping

technique taking gates up to 4*4(which can be varied).

Area, Power, & Delay Calculations:- The number of different gates(1*1, 2*1 etc) are

calculated from the graph and area, & power are calculated for the circuit using individual

values of these (which can be obtained from look up table).

For delay we find out the longest path from input to output node. In other words we calculate

the path with no slack.

EQUATION

{v5.0} = v0 v1

v2 v3 v4' + v0'

v1' v2' + v0'

v1' v3' + v0'

v1' v4 + v0' v2'

v4 + v1' v2' v4

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Look up Table Look up table gives the values of area power, & delay for different types of gates.

ckt name

step up delay

step down delay area total power dissipation total delay

(ps) (ps) (no. of

transistors) (uw)(average dissipation)

(ps)(average)

Inverter 21 11 2 1.083 16

nand2 28 24 4 2.02 26

nand3 44 32 6 2.46 38

nand4 54.3 45.3 8 3.053 49.8

nor2 47 13 4 1.855 30

nor3 70.1 15 6 2.358 42.55

nor4 78.6814 13.196 8 2.534 45.9387

d1x1 44.7 122.15 5 3.46 83.425

d1x2 51.8 36.68 6 18.04 44.24

d1x3 52.14 43.9025 7 26.17 48.02125

d1x4 57 88.85 8 4.846 72.925

d2x1 63.01 71.73 6 3.915 67.37

d2x2 67.72 86.83 8 4.534 77.275

d2x3 80.114 101.2258 10 5.387 90.6699

d2x4 84 115 12 6.222 99.5

d3x1 86.045 76.65424 7 4.292 81.34962

d3x2 96.7775 97.9748 10 5.384 97.37615

d3x3 103.725 118.64 13 6.523 111.1825

d3x4 110.02 143.54 16 7.764 126.78

d4x1 102.9 80.28 8 6.196 91.59

d4x2 118.96 108.4 12 4.629 113.68

d4x3 131 138.75 16 7.764 134.875 d4x4 147.5 165.94 20 9.35 156.72

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Implementation Details

Let us illustrate the solution using example 9sym.pla using library 22-1.genlib.

1) Run the code uda.c ,which is made from maxset unite decomposition algorithm, on input

file 9sym.pla & convert it into two files in .pla format to contain static and dynamic part of

the input onset.

Commands:

Type the following in terminal

cc uda.c

./a.out

Give input as 9sym.pla to this code.

cc convert.c

./a.out

Result: This gives two files in .pla format called 1) stat.pla which contains static part of the

input onset, & 2) dyna.pla which contain dynamic part of the input onset.

2) Use the SIS tool to find the netlist of the static part stat.pla, & copy the netlist to a file

called ‘netliststatic’.

Commands for running SIS tool:

Install sis from net as it is a free tool.

Then type the following commands in the terminal…

cd sis-1.3 (changes with the name of the folder)

cd bin

./sis

Then it will show

Sis>

Which means sis is completely installed in your system

Commands:

Type the following:

./sis

Sis>read_pla stat.pla

Sis>full_simplify

Sis>read_library 22-1.genlib

Sis>map –m 0 [this can be map –m 1 or map –n 1 depends on requirement]

Sis>print

To copy the code to a shell script and redirect the output to the file netliststatic.

Result: Gives a file netliststatic containing netlist of stat.pla

3) Take the 'netliststatic' file as input and create an appropriate graph taking into account all

the connectivities. Use these connectivities to make a picture of graph using graphviz.

Commands:

Type the following:

cc staticgraph.c

./a.out

Copy the output to a file called picturestat.

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Dot -Tpng picturestat>pict.png

The pict.png will contain the required static graph.

Result: The output to staticgraph.c will be a well connected graph which is input to

graphviz. The result is the picture of the graph.[The static graph for 9sym.pla is in

next page].

4) Calculate the area,power by counting the no. of different types of gates, & calculate the

delay by finding the longest path of the graph.

This code is incorporated in staticgraph.c.

Result:

total no of NOT gate in netlist 9

total no of NOR gate in netlist 29

total no of NAND gate in netlist 31

STATIC AREA IS 258.000000

STATIC POWER IS 126.162003

STATIC DELAY IS 340.000000

5) Using SIS tool get the value of the onset function, & save it to a file called equdynamic.

Run the code dynamicgraph.c, which takes the file equdynamic as input and maps it using

domino logic [ up to 4 * 4]. So result obtained is a graph with various dynamic gates.

Commands:

Type the following:

./sis

Sis>read_pla dyna.pla

Sis>full_simplify

Sis>read_library 22-1.genlib

Sis>print

To copy the code to a shell script and redirect the output to the file equdynamic.

6) Calculate the area,power ,& delay as calculated in case of static graph.

Commands:

cc dynamicgraph.c

./a.out

Result:

THE DYNAMIC DELAY IS 394.159973

THE DYNAMIC AREA IS 412.000000

THE DYNAMIC POWER IS 273.414001

7) Apply optimization technique such as genetic algorithm to get better solution[better area,

power, delay].Run the optimization code.

Commands:

cc gaopt.c

./a.out

Result: Various possible combinations of static, & dynamic inputs with corresponding

area,power, & delay. Select the appropriate option to design mixed CMOS.

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Static Graph for 9sym.pla

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DYNAMIC GRAPH FOR 9sym.pla

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Mixed Design for 9sym.pla

The overall area power and delay is calculated. The overall area is tha sum of the areas of static

and dynamic part. Power is also the sum of individual power of static and dynamic parts. The

overall delay is the bigger delay between static and dynamic part.

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Future Work

Some better way of on the fly mapping can be devised so as to get better area, power,

& delay in case of dynamic mapping. So, the mixed design can be more efficient in

comparison to pure static implementation.Also multiple objective optimization can be

done in order to obtain the refined result.

Conclusion

The mixed design has both advantage & disadvantage of both static and dynamic

implementations. In general we can get a faster circuit in mixed design compared to

that using static logic. In some cases we can get better area & power also after

optimization. It is observed that if we use bigger gates in domino logic mapping then the

result can be better.

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References

1. Unate Decomposition of Boolean functions, Alan Mishchenko and James Jacob, Proc.

International Workshop on Logic Synthesis, 2001. 2. Technology mapping for domino logic, Min Zhao and S. S. Sapatnekar, IEEE International

Conference on Computer-Aided Design, Digest of Technical Papers, Nov 1998 pp. 248- 251.

3. Domino logic synthesis using complex static gate, T. Thorp, Gin Yee and C. Sechen,

IEEE International Conference on Computer-Aided Design, Digest of Technical Papers, Nov 1998 pp. 242-247.

4. A Novel approach to Domino Circuit Synthesis, Dhiren M. Parmar, M. Sarma, D.

Samanta, Jan 2007, VLSID '07 : Proceedings of the 20th International Conference on VLSI Design.

5. Design issues in mixed static-domino circuit implementations, Ruchir Puri, IEEE

International Conference on Computer-aided design, proceedings, October 1998 pp.270-275.

6. High-speed compact circuits with CMOS, R.H. Krambeck, C.M. Lee and H. Law, IEEE Journal of Solid-State Circuits, June 1982, vol. SC-17 pp. 614-619.

7. R. K. Brayton et al. SIS: A System for Sequential Circuit Synthesis, Technical Report,

UCB/ERL M92/41, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, May, 1992.

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Project by

Soumya Ranjan Mund

Roll No: 108CS062

National Institute of Technology, Rourkela

Under the Guidance of

Prof. Debasis Samanta

School of Information Technology

Indian Institute of Technology, Kharagpur

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Signature of the Guide

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