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9- Chih-Cheng Hsieh Mixed-Signal IC Design for Image Sensor

Successive Approximation ADC

CHAPTER 9

1


Outline

2

1. Basic Operation Principle of SAR ADC

2. Block Introduction (S/H, DAC, Comparator, SAR)

3. DAC Switching Energy Calculation

4. DAC Switching Method

5. Comparator Requirement (Matching)

6. SAR Logic Implementation


Outline

3







9- Chih-Cheng Hsieh Mixed-Signal IC Design for Image Sensor 4

SAR ADC

• SAR ADC is composed of sample & hold, DAC, comparator and SAR control logic

• Conversion procedure

– Sampling phase S&H sample the input and reset DAC to initial value

– Conversion phase Comparator compare the input signal and DAC output, then control the SAR

logic to perform the binary search from MSB to LSB

Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator

Single Ended SAR ADC

8C 4C 2C 1C 1C

Vref

Vref

Vin

sample

sample

clk

sample

invert

Vref

Vin

VDAC

VDAC

VDAC=Vref

1 1 1Vin=b0( )Vref+b1( )Vref b2( )Vref

2 4 8

1 b3( )Vref+Nq

16


Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


Vref

Vin

VDAC

Vref-Vin

clk

sample

invert

8C 4C 2C 1C 1C

Vref

invert

Vref-Vin

VDAC=Vref-Vin


2 4 8

1 b3( )Vref+Nq

16


Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


Vref

½ VrefVin

VDAC

MSB1

8C 4C 2C 1C 1C

VrefVref-Vin+(½)Vref

Vref

clk

sample

invert

1VDAC=Vref-Vin+( )Vref

2


2 4 8

1 b3( )Vref+Nq

16


Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


Vref

¼ Vref

Vin

MSB1

MSB-10

8C 4C 2C 1C 1C

VrefVref-Vin+(½)Vref+(¼) Vref

Vref

clk

sample

invert

1 1VDAC=Vref-Vin+( )Vref+( )Vref

2 4


2 4 8

1 b3( )Vref+Nq

16


Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


clk

sample

invertVDAC

Vref

1/8Vref

Vin

MSB1

MSB-10

MSB-20

8C 4C 2C 1C 1C

VrefVref-Vin+(½)Vref+(1/8)Vref

Vref Vref


2 8


2 4 8

1 b3( )Vref+Nq

16



2 16

10

Sample & hold

N-bit DAC

SAR Control

Vin

Clk

Comparator


clk

sample

invertVDAC

Vref

1/16Vref

Vin

MSB1

MSB-10

MSB-20

LSB1

8C 4C 2C 1C 1C

VrefVref-Vin+(½)Vref+(1/16)Vref

Vref Vref


2 4 8

1 b3( )Vref+Nq

16

b0=1, b1=0, b2=0, b3=1


Outline

11







7. Low Power Design Case Study


Sample and Hold

VinCload

Vout

Clk

• Simple S/H concept using a NMOS and a capacitor

• When Clk is high, Vin is sampled on the sampling capacitor (Cload)

• Clk becomes low, Vin is held on Cload to perform conversion

Vin

S/H


Sample and Hold – On-Resistance

VinCload

Vout

Clk

• Because of threshold drop, NMOS only can pass the signal from 0 to VDD-Vth

• 𝑅𝑜𝑛 =𝐿

𝑊

1

𝜇𝑛𝐶𝑜𝑥(𝑉𝑔𝑠−𝑉𝑡ℎ)

• On resistance is signal-dependent, which leads to non-linearity error


Sample and Hold – Charge Injection

Vin

Cload

Vout

Clk

Charge injection

• When MOS turns off, stored charges are injected into Vin and Cload, results in voltage change across capacitor

Q = 𝐶𝑜𝑥 ∙ 𝑊 ∙ 𝐿 ∙ (𝑉𝑔𝑠 − 𝑉𝑡ℎ)

∆𝑉 =𝐶𝑜𝑥 ∙ 𝑊 ∙ 𝐿 ∙ (𝑉𝐷𝐷 − 𝑉𝑖𝑛 − 𝑉𝑡ℎ)

2𝐶𝑙𝑜𝑎𝑑

• Voltage change across Cload is signal-dependent, which leads to nonlinearity and harmonic distortion


Sample and Hold – Clock Feedthrough

• When Clk goes from high to low, the capacitance between the gate and source or drain will couple the voltage onto the loading capacitance

∆𝑉 =𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 ∙ 𝑉𝐷𝐷

𝐶𝑙𝑜𝑎𝑑 + 𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝

𝐶𝑜𝑣𝑒𝑟𝑙𝑎𝑝 = 𝐶𝑜𝑥 ∙ 𝑊 ∙ 𝐿𝐷

• 𝐿𝐷 is the length of the gate that overlap the drain/source

Vin

Cload

Vout

Clk

½ Cox ½ Cox


Sample and Hold – kT/C noise

𝑉𝑛2 =

𝑘𝑇

𝐶𝑙𝑜𝑎𝑑

• To achieve higher precision and lower noise, larger sampling capacitor is better

• Larger sampling capacitance needs more settling time

• Trade-off between speed and precision

Vin

Cload

Vout

Clk 𝑘𝑇/𝐶𝑙𝑜𝑎𝑑


Sample and Hold – Bootstrapped

• Under low voltage operation, the gate-source voltage of sampling switch is limited and increases the on-resistance

• The on-resistance results in sampled signal loss

• By the bootstrapped technique, the gate-source of sampling switch is boosted and signal independent

Clk

Clk

CDAC

VDAC=Vin

Vin

VDD

Vin+VDD

M1

M2

M3

M4 M5

M6 MSH


DACOutput

Amplifier

b0 b1 b2 bN-1

VREF

D VREF Vout=KD VREF

Digital-Analog Converter

• N-bits(b0,b1,b2…,bN-2,bN-1)

• Reference voltage VREF

• b0 is most significant bit(MSB)

• bN-1 is least significant bit(LSB)

• 𝐷 =𝑏0

21+

𝑏1

22+

𝑏2

23+⋯+

𝑏𝑁−1

2𝑁

• Vout = KVREF(𝑏0

21+

𝑏1

22+

𝑏2

23+⋯+

𝑏𝑁−1

2𝑁)


000 001 010 011 100 101 110 1110

0.125

0.250

0.375

0.500

0.625

0.750

0.875

1.000

1LSB

Input code

An

alo

g o

utp

ut

vo

lta

ge

Static Characteristic of DAC

• Ideal input-output of a 3-bit DAC

– LSB =𝑉𝑟𝑒𝑓

2𝑁

– Full scale(FS)= 𝑉𝑟𝑒𝑓 − 𝐿𝑆𝐵

= 𝑉𝑟𝑒𝑓 1 −1

2𝑁

– 𝐹𝑆𝑅 = lim𝑁→∞

𝐹𝑆 = 𝑉𝑟𝑒𝑓

– Dynamic range(DR)=𝐹𝑆𝑅

𝐿𝑆𝐵=

𝐹𝑆𝑅

(𝐹𝑆𝑅/2𝑁)= 2𝑁 = 6.02𝑁 𝑑𝐵


000 001 010 011 100 101 110 1110

0.125

0.250

0.375

0.500

0.625

0.750

0.875

1.000

1LSB

Input code

An

alo

g o

utp

ut

vo

lta

ge

000 001 010 011 100 101 110 111

+0.5LSB

-0.5LSB

Input code

Quantization Noise


• Quantization noise

– Analog output of infinite-bit DAC minus the output of finite-bit DAC

• Signal-to-noise ration(SNR) – Ratio of the full scale value to the rms

value of the quantization noise

– rms =1

𝑇 𝐿𝑆𝐵2(

𝑡

𝑇− 0.5)2𝑑𝑡

𝑇

0

=𝐿𝑆𝐵

12=

𝐹𝑆𝑅

2𝑁 12

– 𝑆𝑁𝑅 =𝐹𝑆𝑅/(2 2)

𝐹𝑆𝑅/(2𝑁 12)=

2𝑁 6

2

– 𝑆𝑁𝑅 𝑑𝐵 = 20 log2𝑁 6

2= 6.02𝑁 +

1.76

– 𝐸𝑁𝑂𝐵 =𝑆𝑁𝑅−1.76

6.02



000 001 010 011 100 101 110 1110

0.125

0.250

0.375

0.500

0.625

0.750

0.875

1.000

Input code

An

alo

g o

utp

ut

vo

lta

ge

Offset error

Actual 3-bit characteristic

Ideal 3-bit characteristic

000 001 010 011 100 101 110 1110

0.125

0.250

0.375

0.500

0.625

0.750

0.875

1.000

Input code

An

alo

g o

utp

ut

vo

lta

ge Gain error

K>1

K=1

• Integral nonlinearity(INL)

– ((Vi-Vi,Ideal)/Vs)LSB Vs is the ideal change of bit-to-bit

• Differential nonlinearity(DNL)

– (((Vi-Vi-1)/Vs)-1)LSB Vs is the ideal change of bit-to-bit


Charge Redistribution DAC

• Operate by binary dividing the total charge applied to a capacitor array

• By charge conservation

– 𝑉𝑟𝑒𝑓𝐶𝑒𝑞 = 𝑉𝑟𝑒𝑓 𝑏0𝐶 +𝑏1𝐶

21++⋯+

𝑏𝑁−1

2𝑁−1= 𝐶𝑡𝑜𝑡𝑉𝑜𝑢𝑡 = 2𝐶𝑉𝑜𝑢𝑡

– 𝑉𝑜𝑢𝑡 = 𝑉𝑟𝑒𝑓(𝑏0

21+

𝑏1

22+

𝑏2

23+⋯+

𝑏𝑁−1

2𝑁)

𝑺𝟎 𝑺𝟏 𝑺2 𝑺𝑵 − 𝟐 𝑺𝑵 − 𝟏

𝑽𝒓𝒆𝒇

𝑽𝒐𝒖𝒕 𝑪

𝑪

𝟐

𝑪

𝟒

𝑪

𝟐𝑵−𝟐

𝑪

𝟐𝑵−𝟏

𝑪

𝟐𝑵−𝟏


Comparator

• A comparator is defined as a circuit that has a binary output whose value is based on a comparison of two analog inputs

• Gain=Av= lim∆𝑉→0

𝑉𝑂𝐻−𝑉𝑂𝐿

∆𝑉

vp

vn

vo

VOH

VOL

VO

vp-vn


Comparator – Input Offset

24

VOH

VOL

VO

vp-vnVIH

VIL

VOS

• 𝑉𝑂𝑆 = ∆𝑉𝑇𝐻1,2 +𝑉𝑔𝑠−𝑉𝑇𝐻 1,2

2

∆𝑆1,2

𝑆1,2+

∆𝑅

𝑅

• ∆𝑆1,2 is the dimension mismatch between M1 and M2

• ∆𝑅 is the loading difference induced by M3-M6

• The input common-mode varies the input pair effective voltage which results the dynamic offset and degrades the performance


Outline

25








Switching Energy

26

• Assume that at time 0-, the input voltage has been sampled on the capacitor array and all switches are open. At time 0, the bottom plate of C2 is switched to VREF. The capacitor array is then charged to reach the final value. If the capacitor array settles in time TP, the total energy drawn from VREF is

An Energy-Efficient Charge Recycling Approach

for a SAR Converter With Capacitive DAC, ISCAS’05


Switching Energy

27

• The capacitor switched from ground to VREF consumes E0->1

• The remaining capacitor connected to VREF consumes ETOP

(1)

(2)


• The first step switches 4C to VREF and consumes

• The second step switches 1C from VREF to ground on non-inverting input, and 1C from ground to VREF on inverting input. That consumes

Example

28

(1) (1)

(1) (1)

Δ V=↑1/2

(2)

(2) (2)

(1)

Δ V=↑1/2

Δ V= ↓1/4

Δ V= ↑1/4


• Reset energy is defined as DAC energy consumed before the next sampling

• Some switching method consumes zero reset energy. Ex: Vcm-based and set-and-down switching method

• Some switching method consumes reset energy. Ex: CAS switching method

Reset Energy

29

Reset

SAR


Outline

30








Conventional Switching

3-bit Conventional DAC switching procedure

31


• Split the MSB capacitor into sub-array which is same as the remaining capacitor array

• “down” transition is power-efficient

Split Capacitor Switching

Fig. (a) 2-bit Split capacitor DAC (b) MSB capacitor C2 has been split into C2,1 and C2,2

32


Set-and-Down Switching

• Reset to reference high, VREF, then monotonically switch down

• Common mode voltage varies with every transition

Fig. 3-bit set-and-down DAC switching procedure

33


• Additional voltage source Vcm is needed

• Common mode voltage is fixed

Vcm-Based Switching

Fig. 3-bit Vcm-based DAC switching procedure

34


• Efficient switching energy but has reset energy

Capacitor Average Switching

Fig. 4-bit CAS DAC switching procedure

35


Switching Energy Comparison

10-bit DAC switching energy

36


Switching Energy Comparison

Conventional Split cap Set-and-down Vcm-based

CAS

Normalized Energy(%)

100 62.5 18.75 12.5 8.37

No. of switches 6n+6 12n-2 4n-2 6n-4 8n-8+2m

No. of binary caps

2n+2 4n 2n 2n 4n-4

No. of unit caps 2n 2n 2n-1 2n-1 2n-1

Table. Comparison of switching schemes for N-bit SAR ADC

† “m” depends on how many steps using CAS technique

37


Outline

38








Single-Pole Amplifier

• The comparator amplification gain is

• The relation between amplification gain U and time ta is

39

/( )[1 ]at RCoo

i

VU A e

V

o mA g R m

m

C

g

1ln( )

1

ao

m

o

tA

U

A


Positive-Feedback Regeneration

• The comparator amplification gain is

• The relation between amplification gain U and time ta is

40

1 12

2 11

0

0

O Om O

O Om O

dV VC g V

dt R

dV VC g V

dt R

O mA g R

m

m

C

g

1

ln1

1

a

m

O

tU

A

/

0

1 1 1/

a r

mr

O O

tO

O

ta

RC

A A

VU e

V

1 2

0O Om O

O O O

dV VC g V

dt R

V V V


Offset of a Source-Coupled Pair

• The equivalent input offset is

41

2 222 2 2 2

2

( ) 1( ) ( )

2 4t

OV OVOS t V

V VV V A A

W L

OX

WC

L

2

2 ( ) tV

t

AV

W L

22

2

( ) A

W L


Comparator Typical Architecture

• The equivalent input offset is

• The preamplifier provides:

– Input common-mode rejection

– Kick-back noise reduction

42

OSLOS OSA

VV V

A

22 2

2

( )( ) ( ) OSL

OS OSA

VV V

A


• When CLK=0, latch is disable and no power dissipation.

• When CLK=1

– The M1-M2 pair is activated

first

– The M3-M4 pair is then

activated

– The M5-M6 pair is last

activated.

Regenerative Latch

43


• After comparison, one of the comparator output would force to ground and the other to supply voltage

• The comparator inputs coupled with different voltage resulting a equivalent noise source.

Kickback-Noise

44

• The coupled value is corresponding to the ratio of parasitic capacitance of comparator input device and the loading capacitance of comparator input


Comparator Trade-Off

• For a MOS pair, mismatch and input-referred offset are modeled as

• For a comparator

K. Uyttenhove and M. Steyaert, “Speed-power-accuracy tradeoff in high- speed CMOS ADCs,” TCAS-II, 2002/4, pp. 280–286.

45

22 2 21( )

4t

OVOS V

VV A A

W L

2 /

(2 / 3)

m OV

OX

g I VSpeed

C WL C

22 2

2

2 2 2

( )1 4t

OVV

OS

DD DD

VA A

V

Accuracy V WL V

DDPower I V 2

22 2

1

4t

DD

OVOVOX V

VSpeed Accuracy

Power VVC A A


Variable-Offset Regenerative Latch

• Comparator offset is adjusted by varying C1 and C2, or I1 and I2.

46


Comparator offset Calibration

• During Calibration, Vi = Vi1-Vi2 = 0.

47


Outline

48








SAR ADC Architecture

• The SAR ADC is composed of a sample and hold (S/H), DAC, comparator and digital SAR control logic.

• N comparisons per conversion

• DAC voltage is converged to input voltage by SAR Control, which is determined by comparison results

49


Traditional SAR Logic

• The function of SAR is determined

by the value of each bit in a

sequential manner, based on the

output of comparator.

• Minimized the amount of DFF.

50

00

01

10

11

D Q

Clk

Q

MUX4

COMP

SHIFT

RESET

Q

CLK

ASAR Block

B


FSM of SAR Logic

Conversion step Input D/A word Comparator output

0 1 0 0 0 0 0 0 0 a7

1 a7 1 0 0 0 0 0 0 a6

2 a7 a6 1 0 0 0 0 0 a5

3 a7 a6 a5 1 0 0 0 0 a4

4 a7 a6 a5 a4 1 0 0 0 a3

5 a7 a6 a5 a4 a3 1 0 0 a2

6 a7 a6 a5 a4 a3 a2 1 0 a1

7 a7 a6 a5 a4 a3 a2 a1 1 a0

result a7 a6 a5 a4 a3 a2 a1 a0 -

Rossi, A., "Nonredundant successive approximation register for A/D converters," Electronics Letters , no.12, pp.1055,1057, 6 Jun 1996

51


B.P. Ginsburg, A.P. Chandrakasan, "Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver," JSSC , vol.42, no.2, pp.247,257, Feb. 2007.

Full Custom Register Logics

52

Switch drive register Resettable shift register


SAR ADC Flow Chart

• First, SAR ADC samples input signal on DAC by the S/H.

• Next, after the S/H is turn-off, the comparator directly performs the first comparison.

• According to the comparator output, the

digital output B1 is determined and the DAC

voltage is switched to converged.

• The ADC repeats the procedure until the

MSB to LSB is decided.

53


Asynchronous SAR Logic

• To avoid using a high-frequency clock generator, the asynchronous control circuit uses to internally generate necessary clock signals.

54

CLKs : sampling clock CLKc : control signal of comp. Valid : NAND of comp. outputs CLKi : CLK to store comp. output & control SAR

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