substrate coupling and interconnect noise in mixed-signaland …friedman/presentations/... ·...

Substrate Coupling and Interconnect Noisein Mixed-Signal and High Speed Digital ICs

Eby G. Friedman

Department of Electrical and Computer EngineeringUniversity of Rochester

IEEE CAS Workshop on Mixed-Signal Integrated Circuit Design

December 2, 1999

Presentation Outline

� Introduction to noise in high speed CMOS integrated circuits

� Substrate coupling in mixed-signal integrated circuits

� On-chip inductance

� Peak noise estimation of coupled lossy transmission lines

� On-chip simultaneous switching noise voltage in the powerdistribution network

� Repeater insertion for driving� ��

interconnect

� Conclusions

MSICD’99 Univer sity of Rochester


➱ Introduction to noise in high speed CMOS integrated circuits

� Substrate coupling in mixed-signal integrated circuits





interconnect

� Conclusions


Design Challeng e in VDSM CMOS ICs

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Noise Coupling – The General Case

� Noise

NOISESOURCE Transmission medium

NOISERECEIVER

– Generation

– Transmission

– Reception

� General applications– Digital Influencing Digital– Analog Influencing Analog

� Mixed-signal applications– Digital Influencing Analog– Analog Influencing Digital


Concept of Noise in Digital CMOS ICs

� Definition of noise

“The word noise in the context of digital circuits means un-wanted variation of voltages and currents at the logic nodes.”

— Jan Rabaey, UC Berkeley

“Noise in a digital CMOS VLSI chip is predominantly due tocoupling from other digital nodes, and not caused by intrinsicnoise generated by FETs or by any other active devices.”

— Masakazu Shoji, AT&T Bell Labs

� Aggressor and victim interconnects

RTSU S

V S

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V W

U S�WV S�W

Active signal Coupling noise

Aggressor Victim


Noise Margins in CMOS Digital Circuits

� Noise margin of a CMOS inverter

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Noise in Mixed-Signal Integrated Circuits

Digital Influences Analog

� Analog circuits and signals

InOut

Common chip substrate

Noise

Digital Analog

Vid

Vdd

Vout

Zload Z load

-Vee

– Sensitive analog circuits can be highly susceptible to noise� Digital circuits and signals

– More tolerant to noise– The noise threshold is the noise that induces a change

of logical state� Typical examples

– Digital to Analog Converters– Analog to Digital Converters


Noise in Mixed-Signal Integrated Circuits

Analog Influences Digital

� In smart-power circuits

– High substrate noise levels are present

– A noise threshold can be surpassed

Common chip substrate

Noise

Vdd

In

Power GND

Analog

InOut

Digital


On-Chip Noise Sources in Integrated Circuits

� Substrate coupling noise (substrate crosstalk)

� Interconnect related coupling noise

– On-chip inductance– degradation of signal quality

–� �

/� � �

transmission lines– reflections due to impedance mismatch

– Capacitively and inductively coupled interconnect

� On-chip and off-chip simultaneous switching noise

� Transient ¹ �drops in the power distribution network

� Device related noise– inherent to the FETs


Design for Noise (DFN)

� Overall objective:

– Incorporate substrate and interconnect noiseinto the design process

� Provide a capability for estimating noise at thesystem (or chip) level

� Develop design strategies to reduce substrateand on-chip interconnect noise


Integrate Noise Informationinto the IC Design Flow

Noise Information

Application Specification

Architecture Definition

Logic Design

Circuit Design

Physical Layout

Extraction,

Simulation and Verification


Simulation, and Verification

Fabrication




� Introduction to noise in high speed CMOS integrated circuits

➱ Substrate coupling in mixed-signal integrated circuits





interconnect

� Conclusions


Noise Flow Within Substrate

Noisy drain

P- Bulk

P+ N+ P+

0 50 100 150 200 250 300 350 400 450

10

0

50

40

30

20

Dis

tanc

e

N+ P+

P- Epi Layer

P+ Bulk

Substrate contact

P+

Substrate contact

0

50

40

30

20

Dis

tanc

e

10

Sensitive transistor

Substrate current flow in a lightly doped substrate

Substrate current flow in a highly doped substrate

(mic

rom

eter

s)(m

icro

met

ers)

Distance (micrometers)

* Wooley – IEEE JSSC’93


Classic Substrate Noise Waveforms

Volts

Time0 V

Vp-

p

0 V

(input signal)

Time

Noise generating signal transitions

Noise Voltage

Settling time

º Influence of

– Technology

– Process variables

– Physical layout

– Circuit design

* Wooley – IEEE JSSC’93Rubio – IEE PCDS’95Masui – IEEE IS VLSI’92Wooley – IEEE IEDM’96Fukuda – IEEE JSSC’96


Semiconductor Technologies

N+ N+

S G D G DS

P

P+ P+

D

P+

G

S G D

N+ N+P N-

P-DMOS

S G D

VMOSP

N+ N+

L

P P PN+ P

NN+

N

N+

N

N+

N

N+P+ P+P+

E B C C E C B

NPN Lateral PNP

P <100>

N+

N+

N

N+ N+P P

N

DSGS

P

N

N+ N+

S G D

P

S

P+

N

P+ P+

P+

Poly

P+

SiO2

P-N-well

N-

SiO2/Si3N4/SiO2

WordlineBitline

N+ N+ N+ N+

S G D G DS

P-

S G D G DS

P+

P

N+ N+

N

P+ P+

N

N+ N+

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P

P+ P+

S G D DS

P

N+ N+

N

P+ P+

G

P+ (N-)

P <111>

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NN+

N

N+

N

N+

N

N+P+ P+P+

E B C C E C B

NPN Lateral PNP

N-

DMOS CMOS

NMOS (PMOS) DRAM Technology

CMOS P-well, no-epi CMOS N-well, epi layer

CMOS double-well High-Voltage CMOS

Bipolar technologies DMOS, VMOS technologies

BCD - Bipolar, CMOS, DMOS technologies


Process Variab les

» Process variables

– Substrate doping[Wooley1, Rubio]

– Noise reduction techniques[Wooley1, Rubio, Masui, Allstot]

– Substrate (epitaxial layer) thickness[Rubio]

– Backplane substrate contact[Wooley1, Rubio, Masui, Wooley2, Allstot]

– Bonding wires and number of pads[Wooley1, Rubio, Masui, Allstot]

* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Masui – IEEE IS VLSI’92Wooley2 – IEEE IEDM’96Allstot – IEEE JSSC’94


Circuit and Physical Design

» Circuit design

– Switching speed and transition times[Wooley1, Rubio, Wooley2]

– Interaction among different types of transistors[Rubio]

– Size of the logic circuits[Wooley2]

» Physical layout

– Distance between the noise source and receiver[Wooley1, Rubio, Lewis, Troutman]

– Placement of the substrate contacts[Wooley2]

– Routing of power lines[Allstot1, Vulih]

– Relative placement of the logic and analog blocks[Rubio, Allstot2]

* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Wooley2 – IEEE IEDM’96Lewis – IEEE IEDM’86Troutman – IEEE IEDM’84Allstot1 – IEEE JSSC’94Vulih – IEEE CICC’87Allstot2 – IEEE CICC’94


Appl ying Classic Noise Reduction Techniques

» Specially optimized technologies with increasedisolation [Bierman, Korec, Lanca, Baliga]

D S SG CEB

D S B E C C CE B

D

G

G S

P-

P+

N-

N+

N+

N+ N+P P

P+

N+P

N-

N+

N+

N-

NPNDMOS

P-

N+ P N+ P+

N-

P+ N+

N+

N+N+P P+

N-N- N- N- N-

N+

P+ P+ P+ P+

DMOS NPN PNP

N+ P+ P N+

N- TUB

SiO2

P-

N+ N- P

P+

N+ N+ N+P

P+ P+

N

D G S S G D S G D

The self-isolation technique

High VoltageLateral DMOS

NMOS PMOS

RESURF junction isolation technique

Dielectric isolation technique

POLYSILICON

The thick epitaxial layer junction isolation technique

* Bierman – Electronics’85Korec – SSMAT’95Lanca – ISIE’97Baliga – IEEE TED’86


Appr oach for System on a Chip (SOC)

» Constituent blocks of an SOC– Digital circuit blocks– Analog circuit blocks– Smart-power circuit blocks

» Presently, special technologies are used to mitigate noisein mixed-signal applications

» Primary research objectives:

– Eliminate the need for specialized technologies

– Permit low cost monolithic SOC integration withhigh performance

– Develop– Circuit and physical design solutions to improve

circuit noise immunity

– Create– Low cost smart-power circuitry


Circuit Characteristics» NMOS implementation - Thermal Ink Jet (TIJ) printer

– An analog high-power noise source– A digital noise receptor

[Verdonckt-Vandebroek – IEEE CDM’97]

In

In

Digital Input

Heater

PowerVdd

inverter1 inverter2

Out

Vcc

NMOS power driver

Out

In

ck

ckbar

clear

Q

Vdd

NMOS static slave latch

In

Vdd

Out

In

ckbar

ck

Q1 (small)

Q2 (large)

Vdd

NMOS dynamic latch

13 volt predriver

NMOS Inverter


Test cir cuits

¼ 50 NMOS test circuits have been fabricated in a 3.5 ½ m technologyto analyze the influence of

– Digital influencing analog issues [Wooley1, RubioWooley2, Allstot1, Lewis, Troutman, Vulih, Allstot2]

¾ Distance¾ Noise reduction techniques¾ Placement of substrate contacts¾ Switching speed and transition times¾ Interaction among different transistors¾ Routing of the power lines¾ Logic blocks placement and orientation

– Smart-power specific issues¾ Power driver supply voltage and current¾ Size of the noise source¾ Clock and signal conditioning¾ Power drivers “on-off” timing with respect to registerclocking¾ Duration of noise pulse¾ Chip temperature

* Wooley1 – IEEE JSSC’93Rubio – IEE PCDS’95Wooley2 – IEEE IEDM’96Allstot1 – IEEE JSSC’94Lewis – IEEE IEDM’86Troutman – IEEE IEDM’84Vulih – IEEE CICC’87Allstot2 – IEEE CICC’94


Physical Layout of Test Circuits

» Microphotograph of test circuit used to evaluateeffect of noise in digital registers from high-poweranalog drivers

» Floorplan

Pads

Sensitive registers

312927252321191715131197531

Drivers and heaters

Group 1 Group 2 Group 3 Group 8

8...321 8...32 8...321 8...3211

...

Predrivers

Select registers


Architectural Aspects

» Noise source

– High voltage and high current power drivers

» Noise medium

– Common substrate region

» Noise receptor

– Static and dynamic latches

Pads

Sensitive registers

312927252321191715131197531

Drivers and heaters

Group 1 Group 2 Group 3 Group 8

8...321 8...32 8...321 8...3211

...

Predrivers

Select registers


Physical Layout of Test Circuits

» Test circuit used to evaluate noise waveformswithin the substrate


Physical Layout Detail

» Microphotograph of the latch-predriver-driverinterface


Noise Distrib utions for Epi andNon-Epi Technologies

» Distributions for Epi technologies

» Distributions for Non-Epi technologies


Issues Specific to Noise Coupling

¼ Technology

– Substrate doping

– Substrate (epitaxial layer) thickness

– Backplane substrate contact

¼ Physical Design

– Distance between the noise sour ce and receiver

– Noise reduction techniques¾ Rings¾ Substrate contacts

– Placement of the substrate contacts

– Routing of the high current power lines

– Relative placement of the logic and analog bloc ks

¼ Circuit Design

– Switching speed and transition times

– Interaction among different types of transistors

– Size of the logic circuits

– Static vs. dynamic register s


Dependence of Noise on the Input Data

» A parasitic transition is induced at the registeroutput

– For static master-slave registers

¿ Only if input data is logic high

– For dynamic registers

¿ For both input logic high and logic low

¿ Input low is more sensitive than input high

Out

In

ck

ckbar

clear

Q

Vdd

Out

In

ckbar

ck

Q1 (small)

Q2 (large)

Vdd

NMOS Static Slave Latch NMOS Dynamic Latch


Dependence of Noise on Register Clocking

» Static registers– 4, 3, 2, 1 where 4 = best, 1 = worst

» Dynamic registers– 1, 2, 3, 4 where 1 = best, 4 = worst

Driver pulse

on

off

Input clock

1

2

3

4

5 (same as 4)

(same as 1)6

7 (same as 4)

t1 t2 t3 t4 t5 t6

8

t1t2

t7 t8


Dependence of Noise on Register Clocking(Cont.)

100

90

80

70

60

50

40

30

20

10 s-4

s-3

s-2

s-1

d-1

d-2

d-3

d-4

Noise level (%)

¼ Relative dependency shown in number of affectedregisters

¼ The number of affected dynamic registers (d-4) is 1.3X largerthan the number of affected static registers (s-1)

¼ Noise tolerance further improved with

– Substrate contact placement

– Ground routing

– Register orientation¾ Depletion transistors placed closer to the noise source


Dependence of Noise on Distance

100

77

91

Noise level (%)

static500

static350dynamic350

dynamic500

» Relative dependency shown in number of affectedregisters

» The number of affected dynamic registers (dynamic350) is1.15X larger than the number of affected static registers(static350)

» Two distances evaluated– 350 À m– 500 À m


Noise Spreading Effects

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

34

30

26

22

18

14

10

6

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 3134

30

26

22

18

14

10

6

Clocking regime No. 2. Static registers.

Power driver power supply (Volts)

Register number

Clocking regime No. 3. Static registers.

Power driver power supply (Volts)

Register number

» Specific registers are affected depending on– Clocking regime– Ground bias– Active power driver group


Influence of Analog Power Suppl y

» More registers are affected as

– The driver power supply increases

– The clocking regime changes

– The noise pulse duration increases

0

5

10

15

20

25

30

35

0 5 10 15 20 25 30 35 40

No.

of a

ffect

ed r

egis

ters

Á

Drivers applied voltage (V)

"static1""static2""static3""static4"

» Slight dependency with chip temperature is noted

– Less than 5% for a 25 Â to 55 Â C temperature sweep range


Influence of the Size of the Noise Source

100

90

80

70

60

50

40

30

20

10

76

5

4

3

7

6

Noise level (%) clocking situation 1 clocking situation 4

» Relative dependency shown in number of affectedregisters

» The number of registers is 30X smaller forclocking regime 4 (seven active drivers) thanfor clocking regime 1 (seven active drivers)

» The noise tolerance improves for on-chip connecteddigital and analog ground lines


Related Publicationson Substrate Coupling

Ã R. M. Secareanu, S. Warner, S. Seabridge, C. Burke, T. E. Watrobski, C. Mor-ton, W. Staub, T. Tellier, and E. G. Friedman, “Substrate Noise Distribution andPlacement of Substrate Contacts to Alleviate Substrate Noise in Epi and Non-Epi Technologies,” Proceedings of the 23rd Annual IEEE EDS/CAS Activities inWestern New York Conference, pp. 10-11, November 1999.

Ã R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub,T. Tellier, and E. G. Friedman, “The Behavior of Digital Circuits under SubstrateNoise in a Mixed-Signal Smart Power Environment,” Proceedings of the IEEEInternational Symposium on Power Semiconductor Devices and ICs, pp. 253-256, May 1999.

Ã R. M. Secareanu, I. S. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub,T. Tellier, and E. G. Friedman, “Noise Immunity of Digital Circuits in Mixed-SignalSmart Power Systems,” Proceedings of the IEEE Great Lakes Symposium onVLSI, pp. 314-317, February 1999.



» Introduction to noise in high speed CMOS integrated circuits

» Substrate coupling in mixed-signal integrated circuits

➱ On-chip inductance

» Peak noise estimation of coupled lossy transmission lines

» On-chip simultaneous switching noise voltage in the powerdistribution network

» Repeater insertion for driving Ä ÅÇÆ interconnect

» Conclusions


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