stt simulations (horst wahl, 25 february 2000)

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STT simulations (Horst Wahl, 25 February 2000) trigger simulation (Silvia Tentindo-Repond, Sailesh Chopra, John Hobbs with help from Brian Connolly, Harrison Prosper, + Dave Toback) queueing studies (Stephan Linn) VHDL code for STC and circuit simulation (Bill Earle, Sailesh Chopra, Roberto Brown, Reginald Perry,…) Outline:

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STT simulations (Horst Wahl, 25 February 2000). trigger simulation (Silvia Tentindo-Repond, Sailesh Chopra, John Hobbs with help from Brian Connolly, Harrison Prosper, + Dave Toback) queueing studies (Stephan Linn) VHDL code for STC and circuit simulation - PowerPoint PPT Presentation

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Page 1: STT simulations (Horst Wahl, 25 February 2000)

STT simulations

(Horst Wahl, 25 February 2000)

trigger simulation (Silvia Tentindo-Repond, Sailesh Chopra, John Hobbs with help from Brian

Connolly, Harrison Prosper, + Dave Toback)

queueing studies (Stephan Linn)

VHDL code for STC and circuit simulation (Bill Earle, Sailesh Chopra, Roberto Brown, Reginald Perry,…)

Outline:

Page 2: STT simulations (Horst Wahl, 25 February 2000)

Trigger simulation(Silvia Tentindo-Repond, Sailesh Chopra,..)

Recent modifications/improvements: most of the code committed to CVS t70 L2STT Simulator code split into three

packages: tsim_l2stt (main package) l2stt_fitting l2stt_util

CTT roads:now integrated into main package;temporarily, use function for translation from

CFT to SMT coordinates (translation map for downloading into FPGA being developed)

l2stt_util:changes to accommodate roads and tracking

new functionality: can create a text file that contains SMT hits in

cable-format, to be used as an input for debugging and testing of VHDL code for clustering. (RCP switch)

clusters provided with their own ntuples tests of roads and clusters with t tbar and Z to

bbar + 2 MB events show results compatible

Page 3: STT simulations (Horst Wahl, 25 February 2000)

Trigger simulation, cont’d

tracking (with John Hobbs, Wendy Taylor):

l2stt_fitting contains all possible tracking algorithms (for testing);

main package will only have final choice of algorithm

still being debugged

Chunks: FT_L1 input chunk and SMT_FE input chunk

exist ,used as new UnpDataChunks. STT_L2 output chunk has been created and

encoded in CVS t64; temporarily contains information about Clusters, CFT tracks plus Ps and (fake) STT tracks.

Need STTChannel class; code that creates the STTChannel written, being debugged; need support from expert

Page 4: STT simulations (Horst Wahl, 25 February 2000)

Clusters from one t tbar event

Page 5: STT simulations (Horst Wahl, 25 February 2000)

Clusters from 100 t tbar events

Page 6: STT simulations (Horst Wahl, 25 February 2000)

Clusters from t tbar events

only from barrels

Page 7: STT simulations (Horst Wahl, 25 February 2000)

SMT clusters in CTT roads

Page 8: STT simulations (Horst Wahl, 25 February 2000)

Road centers in SMT

Page 9: STT simulations (Horst Wahl, 25 February 2000)

Clusters in roads for 100 t tbar events

Page 10: STT simulations (Horst Wahl, 25 February 2000)

CTT roads (100 t tbar events)

Clusters in roads

nb. Of CTT tracks

Page 11: STT simulations (Horst Wahl, 25 February 2000)

Queueing Studies(Stephan Linn)

Questions to be answered by queueing studies: how much processing (e.g. track fitting) time can

we afford before deadtime becomes unacceptably high?

where are the potential bottlenecks in the data flow through the trigger?

additional buffering needed?

Queueing simulation software previously, used RESQ (IBM product)

not supported anymore, only runs on IBM platforms look for alternative

Ptolemy: simulation package developed by EE and

comp.science dept. at UC-Berkeley can simulate complex systems at different levels of

detail and with different time scales elements of system represented by “queue and

serve galaxies” specified by service time and queue depth event defined by starting time and data value

(event number)

Page 12: STT simulations (Horst Wahl, 25 February 2000)

STT Model in Ptolemy

use latest specifications (note by U.Heintz at

http://physics.bu.edu/~heintz/STT_q.pdf) parameterize (from MC data)

Nt = number of tracks

Nh = number of hits H = clusters per hit T = clusters per track

transmission speeds data sizes

model: STT modeled as 6 independent sectors random numbers Nt, (hyperexponential) Nh (double

gaussian), track fitting time (double exponential, from JH+WT studies)

correlations between module delay times (depend on Nt, Nh)

PCI bus “arbitration” (priority to road transfer over filtered clusters)

STC filter waits for roads from FRC (see draft of note by Stephan Linn at

http://www-d0.fnal.gov/~linn/d0_private/queue.ps)

Page 13: STT simulations (Horst Wahl, 25 February 2000)

STT Queuing model

Page 14: STT simulations (Horst Wahl, 25 February 2000)

PCI bus model

Page 15: STT simulations (Horst Wahl, 25 February 2000)

distributions used

hit multiplicity

trackmultiplicity

track fitting time

Page 16: STT simulations (Horst Wahl, 25 February 2000)

Queuing simulation results

latency for one STT sextant:

latency for one sextant reproduces track fit delay

full system latency: worst-of-N convolution with five other sextants

total deadtime: < 1% (for nominal values) (not counting deadtime due to min. time between L1 accept)

16 event buffer before track fitting takes care of 50s track fitting time -- never filled to capacity.

no additional buffer necessary

Page 17: STT simulations (Horst Wahl, 25 February 2000)

VHDL code for STC STC VHDL code:

input stage of STC:receive SMT data from VTM recognize data (chip ID, address, pulseheight,

header,....) pedestal/dead channel correctionscluster SMT hits expand SMT strip addresses determine and format cluster pulse height buffer hit clusters (and pulseheights) for hit

filteringbuffer hit clusters (and pulseheights) for L3buffer 90deg hits for ZVC and L3

hit-filtering:receive/format L1CTT roads associate clusters with roadsbuffer associated data for L3 send associated data to TFC

status: preliminary conceptual design by Bill Earle coding: tedious learning curve delay; very recently recruited expert expect faster

progress from now onbig part of code written, being tested and

debugged

Page 18: STT simulations (Horst Wahl, 25 February 2000)

Conclusion

STT trigger simulation tools close to being ready; tracking part operational before Christmas alternative clustering schemes to be

implemented in January investigate possibility of using VHDL to C

translators (help ensure that algorithms in trig.simulation correspond to firmware implemented in hardware)

queueing simulation package operational have STT queueing model which is quite realistic studies so far show no major bottleneck in

design can easily adapt to new specifications as design

progresses

VHDL code for STC addition of new expert (Reginald Perry) will help

a lot getting the job done first version of clustering code being tested

(using VHDL tool to funnel MC data into VHDL code)

Page 19: STT simulations (Horst Wahl, 25 February 2000)

SMT processor galaxy