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SPIN TRANSFER TORQUE-RAM

Roshan Sebastian VSUSN:1PI14LVS1412

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INTRODUCTION:

STT-RAM is a new digital-data-recording technology, which will lead to durable, high density memory chips impervious to

radiation and capable of virtually unlimited read/write cycles.

Called SPIN TRANSFER TORQUE RANDOM ACCESS MEMORY (STT-RAM) chips is cost competitive provide a “revolution in military and space electronics”.

SPIN TORQUE TRANSFER RAM

AIM:

To design a Memory chip that satisfies the following needs:

-Increase the Throughput of the system.

- Reliability and better Scalability.

- Must be resistive to radiation and Other hazards.

- Doubling of the number of transistors on a chip roughly every

two years- MOORE’S law.

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Existing System

RAM

VOLATILE Ex: SRAM, DRAM.

NON-VOLATILEEx: MRAM,

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PROBLEM STATEMENT

In conventional RAM’s we are facing following problems:

Scalability problem (MRAM).

“write disturbance” under some conditions, which affects

accuracy and retention.

More current is needed.

An external magnetic field is necessary(MRAM).

More Voltage is required for the functionality of the chip.

The speed of writing is slow.

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It has no capacity to preserve data under radiation and other

hazards.

The user needs to move data from one format to another,

because it does not have the ability to work with virtually all

systems equally well.

Power trade off problem- “decrease in area of the chip

increases the power consumption”.

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The Challenge

To design the universal memory chip that satisfies all the aims and overcomes all the problems specified.

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PROPOSED SOLUTION

Use SPIN TRANSFER TORQUE technique to design

the Non-Volatile RAM.

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STT-RAM is a new digital-data-recording technology, which will lead to durable, high density memory chips impervious to

radiation and capable of virtually unlimited read/write cycles.

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Tunnel Magnetoresistance (TMR)

NiFe (free layer)

CoFe (fixed layer)Ru

CoFe (pinned layer)

4nm1..2nm

3nm

3nm

Al2O3 (tunneling barrier)

If the orientation of one of the magnetic layers be changed then the device will act as a filter, or ‘spin valve’, letting through more electrons when the spin orientations in the two layers are the same and fewer when orientations are oppositely aligned

The electrical resistance of the device can therefore be changed dramatically.

The resistivity and magnetic field strength of MTJ during logic ‘0’ and logic ‘1’.

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Spin Transfer Torque:

“A spin-polarized current injected into a ferromagnetic layer can induce a torque on its magnetization, hence rotate the

magnetization”.

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M1 exerts torque on incoming electron, that become spin polarized in M1 direction. This spin polarized current in turn exerts a torque on M2, causing M2 precision and switching.

WORKING OF STT-RAM:

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Change in magnetization direction by the application of direct current

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MRAM STT_RAM

External magnetic field is required for switching but this is not required in case of STT-RAM.

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The STT-RAM ARCHITECTURE:

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Parallel magnetic effect in MTJ or logic “1” state

WRITING PROCESS:

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Antiparallel magnetic effect in MTJ or logic “1” stateSPIN TORQUE TRANSFER RAM

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N×N STT-RAM CHIP.

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First generation MRAM cell STT-RAM cell

FABRICATION:

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Failure mitigation techniques for 1T-1MTJ STT_RAM cell

Possible failures in 1T-1R STT-RAM cell

1.Write failure2.Decision (read)failure3.Disturb failure

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Four failure mitigation techniques

A. Word Line Voltage Boosting

Here gate voltage boosted to lower Tx resistance and allow more current to flow through MTJ

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B.Transistor Body biasing

Here bit cell current increased without increasing width of Tx by lowering threshold Vt

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C.Write Voltage Bossting

Here current increased by increasing bit line voltage beyong Vdd

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D. Applied external magnetic field

Here magnetic field is applied to assist free layer magnetization

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Optimization results

Word line voltage boosting achieved most reduction in access transistor width and write power consumptionHowever read failure limited minimum width that could be usedThe applied external field was most energy efficient

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Conclusion

It combines the speed of SRAM.

The non-volatility of flash memory.

Cost effective and low-power memory solution like DRAM.

No limit for write-read cycles (flash 100,000)

Radiation-resistant.

Greater Performance, reliability and Scalability.

All leads to STT-RAM being used as Universal memory

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References

1. X. Fong, S. H. Choday, and K. Roy, “Failure Mitigation Techniques for 1T-1MTJ Spin Transfer Torque MRAM Bit_cells”,VLSI Systems vol.22,NO. 2, Feb. 20142. X. Fong, S. H. Choday, and K. Roy, “Bit-cell level optimization for non-volatile memories using magnetic tunnel junction and spin-transfer torque switching,” I EEE Trans. Nanotechnol., vol. 11, no. 1, pp. 172–181, Jan. 2012

Q/A

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Questions and answer time

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THANK YOU

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