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  • 4.12.2014

    1

    Computer System Structures

    cz:Struktury potaovch systm

    Lecturer: Richard usta

    VUT-FEL in Prague, CR subject A0B35SPS

    Version: 1.0

    Microprocessors

    2

  • 4.12.2014

    2

    Definition: Microprocessor

    A Microprocessor is a Single VLSI Chip that has a CPU and may also have some Other Units (for example, caches, floating point processing arithmetic unit, pipelining, and super-scaling units)

    Source Microprocessor Family

    Motorola 68HCxxx

    Intel 80x86 & i860

    Sun SPARC

    IBM PowerPC

    Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 3

    Existovalo a dodnes existuje mnoho typ od rznch vrobc

    http://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpg

    http://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpghttp://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpghttp://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpghttp://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpghttp://research.microsoft.com/en-us/um/people/gbell/CyberMuseum_contents/Microprocessor_Evolution_Poster.jpg

  • 4.12.2014

    3

    From 8 bit to 32 bit CISC processors

    8 bit -processor 8008 8080 8085 Z80

    Year 1972 1974 1976 1976

    Instructions 66 111 113 158

    MIPS 0.06 0.29 0.37 0.58

    Minimum system (IO circuits) 20-40 7 3 3

    16 and 32 bit

    -processor 8086/88 80286 80386 80486 Pentium

    64bit example: Intel

    I5-2500K Quad core

    Year 1978/79 1982 1985-91 1989-94 1993-98 2011

    Instructions processor

    + numeric cooprocessor 133 ~175 ~195 ~200 ~225 ~500

    MIPS 0.33-0.75 0.9-2.6 2.5-11 16-70 100-300 ~80000

    Memory Physical / Virtual 1 MB 16 MB/1 GB 4 GB / 64TB 32 GB / 256 TB

    Definition: Microcontroller

    A microcontroller is a single-chip VLSI unit which, though having limited computational capabilities possesses enhanced input-output capabilities and a number of on-chip functional units

    Source Microcontroller Family

    Motorola 68HC11xx, HC12xx, HC16xx

    Intel 80x86, 8051, 80251

    Microchip PIC 16F84, 16F876, PIC18

    ARM ARM9, ARM7

    Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 6

  • 4.12.2014

    4

    Microcontroller

    Microcontroller

    (uC)

    Outp

    ut in

    terfaces

    Input in

    tefaces

    In device1

    In device2

    In device3

    Out device1

    Out device2

    Auxiliary

    units

    7

    Example: Original 8051 Microcontroller

    Oscillator

    and timing

    4096 Bytes

    Program

    Memory

    128 Bytes

    Data

    Memory

    Two 16 Bit

    Timer/Event

    Counters

    8051

    CPU

    64 K Byte Bus

    Expansion

    Control

    Programmable

    I/O

    Programmable

    Serial Port Full

    Duplex UART

    Synchronous Shifter

    Internal data bus

    External interrupts

    subsystem interrupts

    Control Parallel ports

    Address Data Bus

    I/O pins Serial Input

    Serial Output

    Source: Raj Kamal, Embedded Systems: Architecture, Programming and Design 8

  • 4.12.2014

    5

    SPS 9

    Hardcore/Softcore Processors

    Hard-core Processors

    A Fabricated Integrated Circuit that may or

    may not be Embedded into Additional Logic

    Soft-core Processors

    A Processor Described in a HDL that is

    implemented in Reconfigurable Logic (ie, in

    an FPGA), e.g NIOS, MicroBlaze, OpenRISC

    SPS 10

    Soft-core Processors Logic Elements

    192

    200

    204

    390

    510

    1170

    1324

    1800

    1928

    1984

    2536

    2600

    3500

    5000

    6000

    37000

    60000

    100 1000 10000 100000

    Xilinx PicoBlaze

    LatticeMico8

    PacoBlaze

    Nios II/e

    DSPuva16

    Nios II/s

    Xilinx MicroBlaze

    Nios II/f

    OpenFire

    LatticeMico32

    aeMB

    ARM Cortex-M1

    LEON3

    LEON2

    OpenRISC 1200

    S1 Core

    Ultra SPARC S1 Core/f

    Su

    n M

    icro

    syste

    ms

    Op

    en

    so

    urc

    e

  • 4.12.2014

    6

    Copyright 2005 Altera Corporation

    Nios II: RISC soft-core processor

    Copyright 2005 Altera Corporation

    Nios II Versions

    Nios II Processor Comes In Three ISA (Instruction Set Architecture) Compatible Versions

    Software Code is Binary Compatible

    No Changes Required When CPU is Changed

    FAST: Optimized for Speed

    STANDARD: Balanced for Speed and

    Size

    ECONOMY: Optimized for Size

    12

  • 4.12.2014

    7

    Copyright 2005 Altera Corporation

    Nios II: Hard Numbers

    Nios II/ f Nios II /s Nios II /e

    Stratix II 200 DMIPS @ 175MHz

    1180 LEs

    90 DMIPS @

    175MHz

    800 LEs

    28 DMIPS @

    190MHz

    400 LEs

    Cyclone 100 DMIPS @ 125MHz

    1800 LEs

    62 DMIPS @

    125MHz

    1200 LEs

    20 DMIPS @

    140MHz

    550 LEs

    DMIPS = Dhrystone benchmark MIPS (million instructions per second)

    Dhrystone is without float point operations

    (Note: Whetstone [cz brousek] has float points)

    Comparing with Pentium (1996) 224 DMIPS @ 200MHz

    cca 196 DMIPS@175MHz - cca 140 DMIPS@125 MHz

    13

    2010 Altera CorporationPublic

    ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

    and Altera marks in and outside the U.S.

    Processor Core Variations Nios II /f

    Fast Nios II /s Standard

    Nios II /e Economy

    Pipeline 6 Stage 5 Stage None

    H/W Multiplier &

    Barrel Shifter 1 Cycle 3 Cycle

    Emulated

    In Software

    Branch Prediction Dynamic Static None

    Instruction Cache Configurable Configurable None

    Data Cache Configurable None None

    Logic Requirements

    (Typical LEs)

    1800 w/o MMU

    3200 w/ MMU 1200 600

    Custom

    Instructions Up to 256

    (MMU - Memory Management Unit)

    14

  • 4.12.2014

    8

    SPS 15 15

    Mutlicycle CPU

    Instr.

    decode/reg.

    fetch/branch

    addr.

    ALU

    operation

    Read

    memory

    data

    Instr.

    fetch/

    adv. PC

    load

    store

    Reg Branch

    Jump

    Start

    State 0 1

    2 3

    4 5

    6

    7 8 9

    Compute

    memory

    addr.

    Write

    jump addr.

    to PC

    Write

    register

    Write

    memory

    data

    Write

    register

    Write PC

    on branch

    condition

    SPS 16

    Different Execution Time of Instructions

    instruction

    memory

    data

    memory registers registers ALU

    P C

    Compute Not used

    Not used

    Not used

    P C

    Jump Not used Not used Not used Not used

    P C

    Branch Not used

    P C

    Branch Not used Not used Not used

    P C

    Load

    Not

    P C

    Store Not used

    Fastest

    Slowest

  • 4.12.2014

    9

    SPS 17

    Single-cycle versus multicycle instruction execution.

    Clock

    Clock

    Instr 2 Instr 1 Instr 3 Instr 4

    3 cycles 3 cycles 4 cycles 5 cycles

    Time saved

    Instr 1 Instr 4 Instr 3 Instr 2

    Time needed

    Time needed

    Time allotted

    Time allotted

    SPS 18

    Internal Registers in CPUs

    Processor

    AC MAR

    ALU

    Control

    Unit

    MDR

    PC IR

    Memory Input/Output

    Data Bus

    Address Bus

    PC Program counter

    AC Accumulator

    Internal registers

    IR Instruction register

    MAR Memory address register

    MDR Memory data register

  • 4.12.2014

    10

    SPS 19

    Cycles of Instructions

    Fetch

    Instruction

    Decode

    Opcode

    Execute

    Operation

    Fetch

    Operands

    Store

    Result IR MAR MDR

    SPS 20

    Pipelining

    zen procesoru s pipelining (zetzenm)

    zpracovnm instrukc nen jednoduch.

    Autoi procesoru MIPS, podobnho NIOSu, uvdj

    ve sv knize (Paterson, D., Henessy, J.: Computer

    Organization and Design, Elsevier), e jimi

    navren jednotka pro pipelining spn otestovna

    nejmn 100 lidmi na 18 rznch pracovitch

    obsahovala chybu ztracenou v nkolika tiscch

    dkch HDL kdu, na kterou se pilo a delm

    pouvn. Vce bude v pedmtu A0B36APO

    Architektura pota

  • 4.12.2014

    11

    2010 Altera CorporationPublic

    ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off.

    and Altera marks in and outside the U.S.

    Minimum Nios II Processor

    Program Controller

    & Address

    Generation

    clock

    reset

    Status & Control

    Registers

    Instruction Master Port

    Data Master Port

    General Purpose Registers

    Nios II Processor Core

    = Configurable

    = Fixed

    Arithmetic Logic Unit

    21

    Outside NI