stratified sampling for fault coverage of vlsi systems

Sep. 26, 2001 Agrawal: Stratified Sampling 1

Stratified Sampling for Fault Coverage of VLSI

Systems

Stratified Sampling for Fault Coverage of VLSI

Systems

Vishwani D. AgrawalAgere Systems, Murray Hill, NJ 07974

[email protected]://cm.bell-labs.com/cm/cs/who/va

September 26, 2001

Collaborators: Pradip Thaker, Acorn Networks, and Mona Zaghloul, GWU

http://cm.bell-labs.com/cm/cs/who/va


VLSI System DesignRegister-transfer level (RTL)

design and verification

Logic synthesis

Test generation

Design and test datafor manufacturing

90-100%stuck-atfault coveragerequired

Timing and physical design


Problem

Accurately estimate the gate-level fault coverage for a VLSI system at the RT-level

Advantages:

• Improve test

• Improve design

• Avoid expensive design changes Previous approaches do not accurately

represent gate-level fault coverage (function errors, mutation, statement faults, branch faults, etc.)


Solution

Model faults as representative sample of the targeted (gate-level stuck-at) faults.

Treat the coverage in an RTL module as a statistical sampling estimate.

For a multi-module VLSI system, combine module coverages according to the stratified sampling technique.


Outline of Talk

Introduction to fault sampling. RTL fault model and application to modules. Coverage in a multi-module system:

• Need for stratified sampling

• Stratum weights

• Experimental results Conclusion References


Fault Sampling

A randomly selected subset (sample) of faults is simulated.

Measured coverage in the sample is used to estimate fault coverage in the entire circuit.

Advantage: Saving in computing resources (CPU time and memory.)

Disadvantage: Limited data on undetected faults.


Random Sampling Model

All faults witha fixed butunknowncoverage

Detectedfault

Undetectedfault

Random

picking

Np = total number of faults

(population size)

C = fault coverage (unknown)

Ns = sample size

Ns << Npc = sample coverage (a random variable)


Probability Density of Sample Coverage, c

(x--C )2

-- ------------ 1 2 2

p (x ) = Prob(x < c < x +dx ) = -------------- e 2 1/2

p (

x )

C C +3C -3 1.0x

Sample coverage

C (1 - C)Variance2 = ------------ Ns

Mean = C

Samplingerror

x


Sampling Error Bounds C (1 - C ) | x - C | = 3 -------------- 1/2

NsSolving the quadratic equation for C, we get the 3-sigma(99.8% confidence) estimate (Agrawal-Kato, 1990):

4.5C 3 = x ------- [1 + 0.44 Ns x (1 - x )]1/2

Ns

Where Ns is sample size and x is the measured fault

coverage in the sample.Example: A circuit with 39,096 faults has an actualfault coverage of 87.1%. The measured coverage ina random sample of 1,000 faults is 88.7%. The aboveformula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.

Millot, 1923


An RTL Fault Model(ITC-2000)

Language operators are assumed to be fault-free Variables (map onto signal lines) contain faults

stuck-at-0stuck-at-1

Only one fault is applied at a time (single fault assumption)


RTL Fault Injection

Not affected by faults:

• Synthetic operators + - * >= <= == !=

• Boolean operators & | ^ ~

• Logical operators && || !

• Sequential elements (flip-flops & latches) Faults introduced in signal variables (stems and

fan-outs) Separate faults for bits of data words


Fault Modeling for Boolean Operators

m odule m ux(c, a , b , s );

assign d = a & s;assign e = s1 & b;assign s1 = !s;assign c = d | e;

endm odule

RT L D escrip tion Sym bolic D escrip tion

as

b

d

e

c

s1


Stem and Fan-out Fault Modeling

RTL fan-out faults: if(X) then Z=Y; else Z=!Y; Unique RTL fault is placed on each fan-out of each bit of a variable Unique RTL fault on each stem

(a )

m odule

(b)

m odule


More RTL Faultsb [1 ]b [0 ]

a [ 1 ]

d [1 ]

c [ 0 ]c [ 1 ]

a [ 0 ]

d [0 ]

+

-

*

f [2 :0 ]

e [ 3 : 0 ]

g [2 :0 ]

<

f [2 :0 ]

>

e [3 :0 ]

e [3 :0 ]

g [ 2 :0 ]

f [2 :0 ]

=

h

j

i

MUX

c lkr e s e t _

v

w

k

o u t_ si g 1

o u t_ s ig 2

g [2 :0 ]


Observations and Assumption: RTL Faults

RTL faults may have detection probability distribution similar to that of collapsed gate-level faults

Statistically, an RTL fault-list approximates a random sample from the gate-level fault-list

Number of RTL faults vs. gate-level faults depends on

• Level of RTL description

• Synthesis procedure used to convert RTL to gate level


RTL Fault Simulation

Analogous to gate-level approach Faults injected in RTL code of the design

description by a C++ parser; a simulatable logic buffer element inserted at fault site

Fault report contains statistics on detected and undetected RTL faults

Cadence’s Verifault-XL used as RTL fault simulator


Estimation Error for Module Fault Coverage RTL fault coverage assumed to be an estimate of the

collapsed gate-fault coverage within statistical bound [Agrawal and Kato, D&T, 1990]:

22

1 4 1 2kN

Nc c k( ) /

a = 3.00 for confidence probability of 99.8%

c = ratio of detected to total number of RTL faults

M = number of gate faults

N = number of RTL faults, k = 1 - N/M


DSP Interface Module(3,168 Gates)

0

10

20

30

40

50

60

70

80

90

100

0 500 1000 1500Test Vectors

RT

L &

Gat

e F

ault

Cov

(%)

RTL CovGate Cov


RTL Faults and VLSI System Coverage

Experimental results demonstrate RTL fault coverage of a module to be a good statistical estimate of the gate-level fault coverage

A VLSI system consists of many interconnected modules

Overall RTL fault-list of a VLSI system does not constitute a representative sample of the gate-level fault-list


Error at System Level

RTL Coverage = (0.91 x 100 + 0.39 x 100) / 200 = 65%Gate Coverage = (0.90 x 150 + 0.40 x 400) / 550 = 54%

A correct estimation of gate-level fault coverage from RTL coverage:

91 x (150 / 550) + 39 x (400 / 550) = 53%

M2100 faults39% cov.




RTL Gate-level


Application of Stratified Sampling

Fault population of a VLSI system divided into strata according to RTL module boundaries

RTL faults in each module are considered a sample of corresponding gate-level faults

The stratified RTL coverage is an estimate of the gate-level coverage:

Wm = stratum weight of mth module = Gm/G

cm = RTL fault coverage of mth module

Gm = number of gate-level faults in mth module

G = number of all gate-level faults in the system

M = number of RTL modules in the system

M

C =Wmcm m=1


Application of Stratified Sampling

Range of coverage,

where,

rm = number of RTL faults in mth module

t = value from tables of normal distribution

The technique requires knowledge of stratum weights and

not absolute values of Gm and G

cm(1 cm)

Wm

rm 1m=1

M

C + t


Stratum Weight Extraction Techniques

Logic synthesis based weight extraction Wm = Gm/G

Floor-planning based weight extraction Wm = Am/A

Entropy-measure based weight extraction


Experimental Procedure

Technology-dependent weight extraction• Several unique gate-level netlists obtained by logic

synthesis from the same RTL code• Each synthesis run performed using a different set of

constraints, e.g., area optimization (netlist 1), speed optimization (netlist 2), or combined area and speed optimizations (netlists 3 and 4)

• Strata weights calculated using gate-level fault lists of various synthesized netlists

Technology-independent weight extraction• Stratum weights calculated using area distribution among

modules Each set of stratum weights used to calculate RTL fault

coverage and error bounds Impact of estimation error investigated


Experimental Data: Weight Distributions

0

0.05

0.1

0.15

0.2

0.25

0.3

1 2 3 4 5 6 7 8 9 10 11 12

Modules

Str

atu

m W

eig

hts

Netlist1

Netlist2

Netlist3

Area

Netlist4


Experimental Data: RTL Fault Coverage

0

10

20

30

40

50

60

70

80

1 2 3 4 5 6 7Test Vector Set

Fau

lt C

ove

rag

e (%

)

RTL Cov.(Wm from Netlist1)RTL Cov.(Wm from Netlist2)RTL Cov.(Wm from Netlist3)RTL Cov. (Wm from Area)RTL Cov. (Wm from Netlist4)Gate Cov.


Experimental Data: Error Bounds

0

1

2

3

4

5

6

7

8

9

10

1 2 3 4 5 6 7

Test Vectors

Err

or

Bo

un

ds

(|E

|)

|E|(Wm from Netlis t1)



|E|(Wm from Area)



Timing Controller ASIC (17,126 Gates)

0

10

20

30

40

50

60

70

0 200 400 600Test Vectors

RT

L &

Gat

e F

ault

Cov

(%)

RTL Cov

Gate Cov


A DSP ASIC(104,881 Gates)

01020304050607080

0 200 400 600 800 1000Test Vectors

RT

L &

Gat

e F

aul

t C

ov(

%)

RTL Cov

Gate Cov


Conclusion Main ideas of RTL fault modeling

• A small or high-level RTL module contributes few RTL faults, but large statistical tolerance gives a correct coverage estimate

• Stratified sampling accounts for varying module sizes and for different RTL details that may be used

• Stratum weights appear to be insensitive to specific details of synthesis

Advantages of the proposed RTL fault model

• High-level test generation and evaluation

• Early identification of hard-to-test RTL architectures

• Potential for significantly reducing run-time penalty of the gate-level fault simulation


References V. D. Agrawal, “Sampling Techniques for Determining Fault Coverage in

LSI Circuits,” J. Digital Systems, vol. V, no. 3, pp. 189-202, 1981. V. D. Agrawal and H. Kato, “Fault Sampling Revisited,” IEEE Design &

Test of Computers, vol. 7, no. 4, pp. 32-35, Aug. 1990. P. A. Thaker, M. E. Zaghloul, and M. B. Amin, “Study of Correlation of

Testability Aspects of RTL Description and Resulting Structural Implementation,” Proc. 12th Int. Conf. VLSI Design, Jan. 1999, pp. 256-259.

P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test,” Proc. 17th IEEE VLSI Test Symp., Apr. 1999, pp. 182-188.

P. A. Thaker, Register-Transfer Level Fault Modeling and Evaluation Techniques, PhD Thesis, George Washington University, Washington, D.C., May 2000.

P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “Register-Transfer Level Fault Modeling and Test Evaluation Techniques for VLSI Circuits,” Proc. Int. Test Conf., Oct. 2000, pp. 940-949.

This presentation is available from the website http://cm.bell-labs.com/cm/cs/who/va


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