1. Storage Systems ktw@csie.ntu.edu.tw (Embedded Systems and Wireless Networking Laboratory) Reading: Kam-yiu Lam and Tei-Wei Kuo, Real-Time Database Systems: Architecture and Techniques, Kluwer Academic Publishers, 2000 Krishna and Kang, Real-TimeSystems, McGRAW-HILL, 1997.Storage SystemsReal-Time Disk Scheduling Flash-Memory Storage Systems

2. Real-Time Disk Scheduling Motivation: Disparity between CPU and disk speed.access time = queuing time + seek time + latency delay + transfer time Strategies to improve the performance of diskservice:First-come-first-served (FCFS) algorithm*:Poor because of no consideration in deadlines and arm movements.Earliest-deadline-first (EDF) algorithm:Not optimum in minimizing the number of transaction deadlines missed.1 4 380 390 Requests Deadlines Track Track1 20 3902 40 13 60 3804 804 1/25/2006 Embedded Systems and Wireless Networking Lab. 3 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Real-Time Disk Scheduling Scan (or elevator) algorithm*:Start at one end of the disk, and moves toward the other end, servicingrequests as it reaches each track, until it gets to the other end of the disk.At the other end, the direction of head movement is reversed andservicing continues.Bad for service requests at either end of a disk.5 30 70 150225 295399Trackqueue=295, 30, 150queue=5, 70, 225 C-Scan (Circle Scan) algorithm*:Goal: Provide a more uniform wait time. As does Scan scheduling, servicing requests as it goes. However, whenthe head reaches one end, it immediately returns to the beginning of thedisk.1/25/2006 Embedded Systems and Wireless Networking Lab. 4 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 3. Real-Time Disk Scheduling Shortest-seek-time-first (SSTF)algorithm*: A greedy algorithm which always selects the request with the minimum seek time from the current request queue. Starvation of some requests...5 30 70150225 305 399Trackqueue=305, 30, 5, 225queue=305, 150 A variation of SCAN: Classify requests into classes. Service requests in the same class in terms of SCAN. Service classes in order of their priorities. Q: How many priority levels are enough, and how to partition them?* means no consideration of deadlines.1/25/2006 Embedded Systems and Wireless Networking Lab. 5 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Real-Time Disk Scheduling A weighted scheduling algorithm: Sort requests in the waiting queue in the increasing order of their deadlines. Each request is assigned a weight wi depending on their order in the queue. Let i be the distance the arm has to move from its current position to serve the request. Consider q requests at a time to reduce the algorithm complexity. Service the request with the highest priority pi = 1/ (wi i) Q: How to assign processes weights wi? A variation of the weighted scheduling algorithm: Motivation: Consider deadline instead of deadline order! Service the request with the highest priority pi = f(di , i) = i + (1-) di . is a design factor, and choosing in the range 0.7 to 0.8 looks good. Reading: A. Silberschatz and P.B. Galvin, Operating System Concepts, 4th Ed., Addison-Wesley Publishing Company, 1994. C.M. Krishna and K.G. Shin, Real-TimeSystems, McGRAW-HILL, 1997.S. Chen, J.A. Stankovic, J.F. Kurose, and D.F. Towsley, Performance Evaluation of Two New disk scheduling Algorithms for Real-Time Systems, J. of Real-Time Systems, 3(3):307-336, 1991. 1/25/2006 Embedded Systems and Wireless Networking Lab. 6 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 4. Real-Time Disk Scheduling Another paper for discussion: A.L. N. Reddy and J.C. Wyllie, I/O Issues in Multimedia System, IEEE Transactions on Computers, March 1994.1/25/2006 Embedded Systems and Wireless Networking Lab.7 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Flash-Memory Storage Systems ktw@csie.ntu.edu.tw (Embedded Systems and Wireless Networking Laboratory) 5. Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 1/25/2006 Embedded Systems and Wireless Networking Lab.9 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Introduction Why Flash Memory Diversified Application Domains Portable Storage Devices Critical System Components Consumer Electronics Industrial Applications1/25/2006 Embedded Systems and Wireless Networking Lab.10 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 6. Introduction The Reality Tremendous Driving Forces from Application Sides Excellent Performance Huge Capacity High Energy Efficiency Reliability Low Cost Good Operability in Critical Conditions 1/25/2006 Embedded Systems and Wireless Networking Lab.11 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Introduction The Characteristicsof Storage MediaAccess time MediaReadWriteEraseDRAM60ns (2B) 60ns (2B) -2.56us (512B) 2.56us (512B)NOR FLASH150ns (1B)211us (1B)1.2s (16KB)14.4us (512B)3.52ms (512B) NAND10.2us (1B) 201us (1B)2ms (16KB) FLASH35.9us (512B) 226us (512B) DISK 12.4ms (512B) 12.4 ms(512B)- (average) (average) [Reference] DRAM:2-2-2 PC100 SDRAM. NOR FLASH: Intel 28F128J3A-150.NAND FLASH: Samsung K9F5608U0M. Disk: Segate Barracuda ATA II.1 1. J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A space-efficient flash translation layer for compact-flash systems. IEEE Transactions on Consumer Electronics, 48(2):366375, May 2002.1/25/2006 Embedded Systems and Wireless Networking Lab.12 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 7. Introduction Challenges Requirements in Good Performance Limited Cost per Unit Strong Demands in Reliability Increasing in Access Frequencies Tight Coupling with Other Components Low Compatibility among Vendors 1/25/2006 Embedded Systems and Wireless Networking Lab.13 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 1/25/2006 Embedded Systems and Wireless Networking Lab.14 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 8. Management Issues SystemArchitectures AP AP APAPFile-System Layer Block Device Layer (FTL emulation)MTD driversFlash Memory1/25/2006 Embedded Systems and Wireless Networking Lab.15 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Flash-MemoryCharacteristicsWrite one 1 Page = 512Bpage 1 Block = 32 pages(16KB)Block 0 Block 1 Block 2 Block 3Eraseone block1/25/2006 Embedded Systems and Wireless Networking Lab.16 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 9. Management Issues Flash-MemoryCharacteristicsWrite-OnceNo writing on the same page unless its residingblock is erased!Pages are classified into valid, invalid, and freepages.Bulk-ErasingPages are erased in a block unit to recycle used butinvalid pages.Wear-LevelingEach block has a limited lifetime in erasing counts.1/25/2006 Embedded Systems and Wireless Networking Lab.17 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Flash-MemoryCharacteristics Example 1: Out-place UpdateABCDLive pages Free pages Suppose that we want to update data A and B 1/25/2006 Embedded Systems and Wireless Networking Lab.18 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 10. Management Issues Flash-MemoryCharacteristics Example 1: Out-place UpdateABCD AB Dead pages1/25/2006 Embedded Systems and Wireless Networking Lab.19 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Flash-MemoryCharacteristics Example 2: Garbage Collection L D D L D D L DThis block is to berecycled. L L D L L L F D(3 live pages and 5dead pages) L F L L L L D FF L L F L L F D A live page A dead page A free page 1/25/2006 Embedded Systems and Wireless Networking Lab.20 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 11. Management Issues Flash-MemoryCharacteristics Example 2: Garbage CollectionD D D D D D D D Live data are copiedto somewhere else. L L D L L L L DL F L L L L D L A live page L L L F L L F D A dead page A free page 1/25/2006 Embedded Systems and Wireless Networking Lab.21 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Flash-MemoryCharacteristics Example 2: Garbage Collection F F F F F F F FThe block is then erased.L L D L L L L DOverheads:live data copying L F L L L L D Lblock erasing.L L L F L L F D A live page A dead page A free page 1/25/2006 Embedded Systems and Wireless Networking Lab.22 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 12. Management Issues Flash-MemoryCharacteristics Example 3: Wear-Leveling Wear-leveling might 100 L D D L D D L DAinterfere with the 10 decisions of the block- L L D L L L F DBrecycling policy. 20L F L L L L D FC A live page 15A dead page F L L F L L F DDA free pageErase cycle counts1/25/2006 Embedded Systems and Wireless Networking Lab. 23 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Policies: FTL FTL adopts a page-level address translation mechanism. The main problem of FTL is on large memory space requirements for storing the address translation information.1/25/2006 Embedded Systems and Wireless Networking Lab. 24 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 13. Management Issues Policies: NFTLA logical address under NFTL is divided into a virtualblock address and a block offset.e.g., LBA=1011 => virtual block address (VBA) = 1011 / 8 =126 and block offset = 1011 % 8 = 3 NFTLA Primary Block A Replacement BlockAddress Translation Table Address = 9 Address = 23 (in main-memory)Write data to Free UsedLBA=1011Free Used . .Free Used .UsedFree (9,23) FreeFree .If the page has been .Block Free to the used FreeWrite .Offset=3first free page VBA=126FreeFree1/25/2006FreeEmbedded Systems and Wireless Networking Lab. Free 25 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Policies: NFTLNFTL is proposed for the large-scale NAND flash storage systems because NFTL adopts a block-level address translation.However, the address translation performance of read and write requests might deteriorate, due to linear searches of address translation information in primary and replacement blocks. 1/25/2006 Embedded Systems and Wireless Networking Lab.26 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 14. Management Issues Policies FTL NFTLMemory Space RequirementsLarge Small Address Translation TimeShort LongGarbage Collection OverheadLessMore Space Utilization HighLow The Memory Space Requirements for one 256MB NAND (512B/Page, 4B/Table Entry, 32 Pages/Block) FTL: 2,048KB (= 4*(256*1024*1024)/512) NFTL: 64KB (= 4*(256*1024*1024)/(512*32)) 1/25/2006 Embedded Systems and Wireless Networking Lab.27 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Management Issues Flash-Memory Characteristics *FTL: Flash Translation Layer, MTD: Memory Technology Device 1/25/2006 Embedded Systems and Wireless Networking Lab.28 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 15. Management Issues Observations The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access numbers seriously exaggerates the Read/Program Disturb Problems!1/25/2006 Embedded Systems and Wireless Networking Lab.29 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 1/25/2006 Embedded Systems and Wireless Networking Lab.30 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 16. System Architecture fwrite(file,data) processprocess processApplications File system (FAT, ext2......) File Systems Block write (LBA,size) GarbageAddress FTL Layer Collection Translation Flash I/O Requests Flash-Memory Storage SystemDevice DriverControlsignals Physical Devices(Flash Memory Banks) 1/25/2006Embedded Systems and Wireless Networking Lab.31 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Flash ManagementObjectives Performance Space Utilization Memory OverheadsGarbage Collection CostPhysical Block Address .(block,page).Access LBA = 3 .. ..11 1,310 1,2 9 (1,3) 1,1 8 (1,2) 1,0 7 (2,1) 0,7 6 (1,0) 0,6 5 (4,7) 0,5 4 (0,4) 0,4 Spare data 3 (0,6) 0,3 2 0,2 1 (0,1) 0,1LBA=3; 0 (0,3) 0,0 ECC=. . .;Status=. . .;Logical Block Physical BlockAddressUserSpareAddress(block,page) data data (array index) Address TranslationTable (in main-memory) Flash memory1/25/2006Embedded Systems and Wireless Networking Lab.32 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 17. Flash Management Stripping Designs Efficient Hot-Data Identification Reliability Address Translation Efficiency Large-Scale Flash 1/25/2006 Embedded Systems and Wireless Networking Lab.33 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Stripping Designs Why? Could we boost the system performance and enlarge the system capacity by simply having multiple flash banks working together? Issues Space Utilization vs Wear-Leveling Stripping Levels vs Performance Performance vs Management Granularity 1/25/2006 Embedded Systems and Wireless Networking Lab.34 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 18. Stripping Designs Parallelism An Example Parallelism in Write OperationsMeasured performance:commandcommand + data = 313 sec busy = 606 secdata c busydata c busy data c busy data c busy1/25/2006 Embedded Systems and Wireless Networking Lab.35 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Stripping DesignsDecoder LatchLatchLatchLatchBank #0Bank #1 Bank #2 Bank #3 Each bank can operate (read/write/erase) independently. One Common Technical Issue: How to smartly distribute write requests among banks?1/25/2006 Embedded Systems and Wireless Networking Lab.36 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 19. Stripping DesignsPotential IssuesStatic or Dynamic Stripping Performance Boosting Bound?Access Locality Hot versus Cold Data1/25/2006 Embedded Systems and Wireless Networking Lab.37 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Stripping Designs A Static Striping Policy A typical static striping policy would evenly scatter write requests over banks to improve the parallelism. A RAID-0-Based Approach: Bank address = (LBA) % (# of the total number of banks)1/25/2006 Embedded Systems and Wireless Networking Lab.38 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 20. Stripping Designs A Static StripingPolicy 0 1 2 3 4 5 6 701 2 3 45 6 7True fair usages of banks could be hardlyachieved by static striping!1/25/2006 Embedded Systems and Wireless Networking Lab.39 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Stripping Designs A Snapshot ofa Realistic Workload1/25/2006 Embedded Systems and Wireless Networking Lab.40 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 21. Stripping Designs Hot data Hot data usually come from meta-data of file-systems, andSmall. A piece of hot data is usually 2 sectors. structured (or indexed) user files, etc. Storing of hot data on a statically assigned bank might consume free space quickly, start garbage collection frequently, or wear their residing banks quickly.1/25/2006 Embedded Systems and Wireless Networking Lab.41 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Stripping Designs Cold Data Cold data usually come from read-only (or WORM) files. E.g., bulk and sequential files that often have a number of sectors. Storing of cold data on a statically assigned bank might increase the capacity utilization, and deteriorate the efficiency of garbage collection severely.1/25/2006 Embedded Systems and Wireless Networking Lab.42 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 22. Stripping Designs A Dynamic Striping Policy Main Strategies:Distribute hot/cold data properly amongbanks.Hot data banks have low erase cycle counts.Cold data banks have low capacityutilizations. Remark: The hotness of written data should be efficiently identified!!!1/25/2006 Embedded Systems and Wireless Networking Lab.43 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Stripping Designs Dynamic Striping 0 15 16 0 5 6 7 8 9 100 16 7 81569 1005 100200250 300 Erase cycle countHot dataCold data 1/25/2006 Embedded Systems and Wireless Networking Lab.44 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 23. Stripping Designs A Hot-Cold Identification Mechanism Hot listElement is demoted Element is promoted to the to the candidate list if hot list if the LBA alreadythe hot list is full.exists in the candidate list.Candidate list Element is discarded ifNew element with LBA is added ifthe candidate list is full.the LBA does not exist in any list. 1/25/2006 Embedded Systems and Wireless Networking Lab.45 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Stripping Designs Address TranslationA ccess.LBA = 3 ..... p h y s ic a l a d d re s s110 ,1 ,3(b a n k ,b lo c k ,p a g e )100 ,1 ,2 92 ,1 ,3 0 ,1 ,1 80 ,1 ,2 0 ,1 ,0 71 ,2 ,1 0 ,0 ,7 60 ,1 ,0 0 ,0 ,6 50 ,4 ,7 0 ,0 ,5 40 ,0 ,4 0 ,0 ,4s p a re 30 ,0 ,6 0 ,0 ,3 20 ,0 ,1 0 ,0 ,2 10 ,0 ,1 LBA= 3; 00 ,0 ,3 0 ,0 ,0E C C = ...;S ta tu s = ...; U serS p a reLBAP h y s ic a l a d d re s s(a rra y in d e x ) (b a n k ,b lo c k ,p a g e ) A re aA re a A d d re s s T ra n s la tio n F la s h m e m o ry T a b le (In R A M )1/25/2006 Embedded Systems and Wireless Networking Lab.46 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 24. Stripping Designs PerformanceEvaluation 40,000Write Request Response Time 35,000 30,000When the 25,000Flash20,000(us)Capacity 15,0004 BanksIs Fixed 10,0002 Banks5,0001 Bank 01600 2400 3200 4000 4800 5600 6400 7200 8000 8800 Write Requests Processed So FarB aa n k00B nkB aa n k11 B nk B aa n k22 B nkB aa n k33B nk E ra s e c yc le c o u n tsE ra s e c yc le c o u n ts33 5 0 50 33 5 252 33 4 8 48 33 5 050 (D yn a m ic )(D yn a m ic ) E ra s e c yc le c o u n tsE ra s e c yc le c o u n ts33 0 7 07 44 7 575 33 7 3 73 33 3 434 (S ta tic )(S ta tic ) C a p a c ity U tiliza tio nC a p a c ity U tiliza tio n 00 .7 6 .7 600 .7 6 .7 600 .7 6 .7 6 00 .7 6.7 6 (D yn a m ic )(D yn a m ic ) C a p a c ity U tiliza tio nC a p a c ity U tiliza tio n 00 .7 2 .7 200 .8 1 .8 100 .7 7 .7 7 00 .7 4.7 4 (S ta tic )(S ta tic )1/25/2006Embedded Systems and Wireless Networking Lab.47 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Flash Management Stripping Designs Efficient Hot-Data Identification Reliability Address Translation Efficiency Large-Scale Flash 1/25/2006Embedded Systems and Wireless Networking Lab.48 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 25. Efficient Hot-Data Identification A Snapshot of a Realistic Workload1/25/2006 Embedded Systems and Wireless Networking Lab.49 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Efficient Hot-Data Identification Why Important?Wear-LevelingPages that contain hot data could turn into dead pagesvery quickly.Blocks with dead pages are usually chosen for erasing. Hot data should be written to blocks with smallererase counts.Erase Efficiency (i.e., effective free pagesreclaimed from garbage collection.) Mixture of hot data and non-hot data in blocksmight deteriorate the efficiency of erase operations.1/25/2006 Embedded Systems and Wireless Networking Lab.50 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 26. Efficient Hot-Data Identification Related WorkMaintain data update times for all LBAs (Logical BlockAddresses)1Introduce significant memory-space overheadsHave a data structure to order LBAs in terms of their updatetimes2Require considerable computing overheads Our ApproachA Multi-Hash-Function FrameworkIdentify hot data in a constant timeReduce the required memory space 1. M. L. Chiang, Paul C. H. Lee, and R. C. Chang, Managing Flash Memory in Personal Communication Devices, ISCE 97, December 1997, pp. 177-1822. L. P. Chang and T. W. Kuo, An Adaptive Striping Architecture for Flash Memory Storage Systems of Embedded Systems, 8th IEEE RTAS, September 2002, pp. 187-1961/25/2006 Embedded Systems and Wireless Networking Lab.51 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Efficient Hot-Data Identification A Multi-Hash-Function Framework012 Hash functionsK independent hashf1(y)functions M-entry hash tablef2(y) C-bit counters Checkupfk(y)Status Update DecayC-bit counterM11/25/2006 Hash table Systems and Wireless Networking Lab.Embedded 52 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 27. Efficient Hot-Data Identification A Multi-Hash-Function Framework Hotness Checkup 1 0 1 1 1. An LBA is to be verified as a location0 1 1 1 for hot data. f1(y)(z)2. The corresponding LBA y is hashedsimultaneously by K given hash0 0 1 1Logical Block functions.Address f2(y)(z)3. Check if the H most significant bits y1 0 0 0of every counter of the K hashedvalues contain a non-zero bit value.f3(y)(z)z1 0 1 01 1 1 1f4(y)(z) 1 1 0 1 H most significant Bits1/25/2006 Embedded Systems and Wireless Networking Lab.53 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Efficient Hot-Data Identification A Multi-Hash-Function Framework Status Update1 0 1 11 0 0 1. A write is issued to the FTL. 2. The corresponding LBA y is hashedsimultaneously by K given hashf1(y)functions.0 0 1 11 0 0Logical Block3. Each counter corresponding to the KAddress f2(y) hashed values (in the hash table) isincremented by one to reflect the yfact that the LBA is written again,f3(y) 1 0 1 01 f4(y) 1 1 0 11 0 H most significant Bits1/25/2006 Embedded Systems and Wireless Networking Lab.54 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 28. Efficient Hot-Data Identification A Multi-Hash-Function Framework 0 Decay0 11 00 1 1 0For every given number of sectors have 0 0been written, called the decay period of 0the write numbers, the values of all 0counters are divided by 2 in terms of a 00 1 10 0right shifting of their bits. 0 0 0 0 0 0 0 11 0 10 1 0 0 0 0 0 11 0 11 0 0 0 H most significant Bits 0 1/25/2006Embedded Systems and Wireless Networking Lab.55 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Efficient Hot-Data Identification Implementation StrategiesA Column-Major Hash Table1/25/2006Embedded Systems and Wireless Networking Lab.56 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 29. Efficient Hot-Data Identification Analytic Study The probability of false identification of an LBA as a location for hot data:(1 (1 1/M)2NRK)K RSystem Model ParametersNotation Number of Counters/Entries in a Hash TableM Number of Write References N Ratio of Hot Data in All Data (< 50%)R Number of Hash Functions K1/25/2006 Embedded Systems and Wireless Networking Lab.57 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Efficient Hot-Data Identification Impacts of Hash-Table Sizes Ratio of Hot Data to All Data (%)The locality of data access(decay period: 5117 writes) Ratio of False Hot-Data Identification (%) Ratio of false hot- data identification for various hash- table sizes1/25/2006 Embedded Systems and Wireless Networking Lab.58 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 30. Efficient Hot-Data Identification Impacts of Decay Period Multi-Hash-Function Ratio of Hot Data to All Data Direct Address 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 21.75 1.5 1.251 Decay Period 0.75 (unit: 5117 writes) 400.5 3035 20 25 0.25101505The Number of Write Requests So Far (unit: 1279 writes)1/25/2006 Embedded Systems and Wireless Networking Lab. 59 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Efficient Hot-Data Identification Runtime Overheads Multi-Hash-Function Two-Level LRU List*Framework (2KB)(512/1024) Standard Standard Average Average DeviationDeviation Checkup2431.358 97.98981 4126.353 2328.367Status Update 1537.848 45.09809 12301.75 11453.72Decay 356590.7671 N/AN/AUnit: CPU cycles * L. P. Chang and T. W. Kuo, An Adaptive Striping Architecture for Flash Memory StorageSystems of Embedded Systems, 8th IEEE RTAS, September 2002, pp. 187-1961/25/2006 Embedded Systems and Wireless Networking Lab. 60 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 31. Agenda Introduction Management Issues Performance vs Overheads Other Challenging Issues Conclusion 1/25/2006 Embedded Systems and Wireless Networking Lab. 61 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Challenging Issues ReliabilityEach Word Line is connected tocontrol gates.Each Bit Line is connected to thedrain. Control GateDrainSource Cell IDS Selected cell 1/25/2006 Embedded Systems and Wireless Networking Lab. 62 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 32. Challenging Issues ReliabilityRead OperationProgram OperationWhen the floating gate is Electrons are moved intonot charged with electrons, the floating gate, and thethere is current ID (100uA) threshold voltage is thusif a reading voltage is raised.applied. (1 state)5V 1V1/25/2006 Embedded Systems and Wireless Networking Lab.63 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Challenging Issues Reliability Over-Erasing Problems Fast Erasing Bits All of the cells connected to the same bit line of a depleted cell would be read as 1, regardless of their values. Read/Program Disturb Problems DC erasing of a programmed cell, DC Programming of a non-programmed cell, drain disturb, etc. Flash memory that has thin gate oxide makes disturb problems more serious! Data Retention Problems Electrons stored in a floating gate might be lost such that the lost of electrons will sooner or later affects the charging status of the gate!1/25/2006 Embedded Systems and Wireless Networking Lab.64 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 33. Challenging Issues Observations The write throughput drops significantly after garbage collection starts! The capacity of flash-memory storage systems increases very quickly such that memory space requirements grows quickly. Reliability becomes more and more critical when the manufacturing capacity increases! The significant increment of flash-memory access numbers seriously exaggerates the Read/Program Disturb Problems! Wear-leveling technology is even more critical when flash memory is adopted in many system components or might survive in products for a long life time!1/25/2006 Embedded Systems and Wireless Networking Lab.65 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University.Conclusion Summary Striping Issues Hot-Data Identification Challenging Issues Scalability Scalability Technology Reliability Technology Customization Technology1/25/2006 Embedded Systems and Wireless Networking Lab.66 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. 34. Contact InformationProfessor Tei-Wei Kuoktw@csie.ntu.edu.twURL: http://csie.ntu.edu.tw/~ktwFlash Research:http://newslab.csie.ntu.edu.tw/~flash/Office: +886-2-23625336-257Fax: +886-2-23628167Address: Dept. of Computer Science & Information Engr. National Taiwan University, Taipei, Taiwan 1061/25/2006 Embedded Systems and Wireless Networking Lab.67 Copyright: All rights reserved, Prof. Tei-Wei Kuo, Embedded System and Wireless Networking Lab, National Taiwan University. Q&A