stm32_training_12w06_1v0 (1)

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STM32VL- Training

Tunis – Jan 2012 V1.0

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CONTENTS

PART I : CORTEX-M3

PART II : STM32F100 device

PART III : STM32 Value line Discovery Kit

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PART - I

CORTEX M3

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CONTENTS Objectives Introduction

Cortex-M3 Processor

Cortex M3 interrupt handling

Cortex-M3 Memory Map

Power Management

System Timer (SysTick)

Debug Capabilities

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OBJECTIVES

Familiarize with Cortex M3

At the end of the part you will be able to List the main features of the Cortex M3

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CONTENTS Objectives

Introduction

Cortex-M3 Processor



Power Management


Debug Capabilities

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What is ARM(Advanced Risc Machines)?

ARM is an UK company that designs

innovative 32-bit microprocessors

ARM leads the world of RISC microprocessor cores

ARM develops directly and through partnership the tools, systems and services to support its architecture.

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Why use an ARM-based processor? Sa

les

in b

illion

s of

dol

lars

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Why Cortex M3?

Cortex-A Series, applications processors for complex OS and user applications. Cortex-R Series, real-time systems profile. Cortex-M Series, microcontroller profile optimized for cost-sensitive applications.. The number at the end of the Cortex name refers to the relative performance level, with 1 the lowest and 8 the highest.

More Than 28 company ST, NXP, Atmel, Samsung…

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ARM Cortex processor family

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CONTENTS Objectives

Introduction

Cortex-M3 Processor



Power Management


Debug Capabilities

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Cortex-M3 Processor Hierarchical processor integrating core and advanced system peripherals

Cortex-M3 Processor

CM3 Core: Harvard (Separate Busses) 32 Bits Register & ALUs.

Interrupt controller: -1 to 240 interrupts. - 256 Priority levels - Hard Fault -SysTick

(Porting !!!)

WIC

Wakup Int. controller: Wakeup from Sleep

modes throuht interrupts & exceptions

Debug Access port

4 Watch points

Multi layer Bus Matrix (Parallel transfers

between core, memory, & peripherals

8 Hardware Breakpoints

Integrated Trace module: Low cost (2 wires)

Embedded Trace MacroCell

Optional Memory Protection Unit (8 regions)

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Cortex-M3 Processor Main Features ARM v7M Architecture

Thumb-2 Instruction Set Architecture Mix of 16 and 32 bit instructions for very high code density

Harvard architecture Separate I & D buses allow parallel instruction fetching & data storage

Integrated Nested Vectored Interrupt Controller (NVIC) Vector Table is addresses.

Integrated Bus Matrix

Data memory management

3 Stage Pipeline

Integrated System Timer (SysTick) for Real Time OS

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Data Memory management (1/7)

Cortex-M3 includes two technologies to reduce Data memory requirements: 1. Unaligned Data Support 2. Atomic Bit Banding

These technologies can dramatically improve data

(SRAM) memory utilization, potentially enabling silicon designers and users to reduce the amount of SRAM required and dramatically impacting silicon usage.

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Data Memory management(2/7)

Long (32) Long (32)

short (16) short (16) Char Char Char Char

Unused (wasted) space

Data aligned on word boundaries

Char

Long (32)

short (16) Char Char Char

short (16) Long (32)

Free space Can be used

Other Core does not support unaligned data

ARM Cortex-M3 supports unaligned data that can improve SRAM utilization

• Unaligned Data Support:

Reduces SRAM Memory Requirements By Over 50%

Less Memory - LowER Cost devices

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Unused (wasted) space

Data aligned

Free space for the rest of the application

32bit machine which does not support

unaligned data

long (32)

int (16)

char (8)

long (32)

int (16)c

int (16)

long (32)

char (8) char (8) char (8)

char (8)

long (32)

… long

int (16)

char (8)

… long int (16)c

int (16)

… long (32)

char (8) char (8) char (8)

char (8)

long (32)

long (32) …

long (32) …

long …

Structure management

example

Reduces SRAM Memory Requirements By Over 25%

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♦ Bit Banding done by bus matrix. ♦ Single instruction Read/Modify/Write (no more masking). ♦ No new instruction set Use standard data one (AND, OR, XOR…).

b0

b31

32bit

b0 b31 @Rbase+N

example: 20000000h to 200FFFFFh

VIRTUAL aliased bit banding image

REAL memory image

Speed and code size optimized Cortex-M3 implementation

Read byte (RAM, register)

1 1 0 1 0 0 1 0

Disable external events

Mask and modify bit element

X X 1 X X X X X

Write byte (RAM, register)

1 1 1 1 0 0 1 0

Enable external events

Traditional method

Optimized RAM, peripherals and IOs registers accesses Easy multi-task semaphore management

• Bit Banding:

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1MB Peripheral bit-band region

32MB alias region

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• Each bit of the bit band region (1MB) is mapped to one 32 bit address (32 MB Bit Band Alias = « Virtual zone »).

• Each bit in the Bit Band region can be accessed separately through the corresponding 32 bits register in the alias region.

Bit Banding

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Data Memory management(7/7) Bit Banding

where: bit_word_addr: is the address of the word in the alias memory region that maps to the targeted bit.

bit_band_base is the starting address of the alias region (0x22000000 or 0x42000000 )

byte_offset is the number of the byte in the bit-band region that contains the targeted bit

bit_number is the bit position of the targeted bit(0-7).

• Bit Banding formula (mapping the bit to the register) is: bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)

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Data Memory management: exercice Bit Banding

Solution:

We are accessing the peripheral bit band region beginning at 0x 0x40000000

and mapped to the bit band alias zone with bit_band_base = 0x42000000

Example -1: How to map bit 15 of the byte located at address 0x40000300 in the alias region.

Writing to address 0x4200609C has the same effect as a read-modify-write operation on bit 15 of the byte at address 0x40000300.

0x42000000 + ( 0x301*32) + (7 * 4) = 0x4200603C =bit_word_addr

Reading address 0x4200603C returns the value of bit 15 of the byte at address 0x40000300.

Byte_offset = 0x40000300 - 0x40000000 = 0x300

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Instruction Pipeline(1/3)

PC points to fetch stage:

FETCH

DECODE

EXECUTE

Instruction fetched from memory

Instruction decoded

Register(s) read from Register Bank

Shift and ALU operation or memory access

Write register(s) back to Register Bank

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Cycle 1 2 3 4 5 6 7 8 9 Operation ADD F D E SUB F D E ORR F D E AND F D E ORR F D E EOR F D E

F- Fetch D - Decode E - Execute All operations here are registers (single cycle execution) In this example it takes 6 cycles to execute 6 instructions Clock cycles per Instructions (CPI) = 1

Optimal Pipelining:

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A flush of the pipeline can occur because of A Branch An exception A breakpoint

F- Fetch D - Decode E - Execute

0x8FF0 EOR 0x8FEE ORR 0x8FEC AND 0x8004 ORR 0x8002 SUB 0x8000 B 0x8FEC Address Operation Cycle 9 8 7

E D F E D F

E D F F D F E D F

6 5 4 3 2 1 Branch Pipeline Example:

Flushing :

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Register Set(1/2) Registers R0-R12 are simple registers

that can be used to hold program variables.

Registers R13-R15 have special functions within the Cortex CPU. R13: Register R13 is used as the stack pointer

R14: called the link register. used to store the return address when a call is made to a procedure

R15: is the program counter

xPSR:The Program Status Register contains status fields for instruction execution

R8

R9

R10

R11

R12

R13(SP)

R14(LR)

R15 (PC)

xPSR

R0

R1

R2

R3

R4

R5

R6

R7

Register Set

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Cortex-M3 Processor




Debug Capabilities

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Interrupt Handling

The Cortex-M3 processor integrates an advanced Nested Vectored Interrupt Controller (NVIC)

The NVIC supports up to 240 dynamically reprioritizes

interrupts each with up to 256 levels of priority

Supports advanced features for next generation real-time applications: Tail-chaining of pending interrupts Interrupt Pre-emption Late Arrival

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PUSH POP ISR 1 PUSH POP ISR 2

PUSH ISR 1 POP ISR 2

26 16 26 16

12

IRQ1

IRQ2

ARM7 Interrupt handling in

assembler code

Cortex-M3 Interrupt handling in HW

6 12

42 CYCLES

6 CYCLES

Interrupt Response- Tail Chaining(1/3)

Highest

Tail-chaining

ARM7 • 26 cycles from IRQ1 to ISR1 entered

•Up to 42 cycles •42 cycles from ISR1 exit to ISR2 entry •16 cycles to return from ISR2

Cortex-M3 • 12 cycles from IRQ1 to ISR1 entered

• 12 cycles •6 cycles from ISR1 exit to ISR2 entry •12 cycles to return from ISR2

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Interrupt Response – Preemption(2/3)

POP ISR 1 PUSH 2 POP ISR 2

ISR 1 POP ISR 2

16 26 16

1- 11

IRQ1

IRQ2

ARM7

Cortex-M3

6

42 CYCLES

7-18 CYCLES

Highest

POP

12

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ISR 2

Interrupt Response – Late Arriving(3/3)

IRQ1

IRQ2

ISR 2

Tail-Chaining

ISR 1 PUSH PUSH POP POP

PUSH POP

ARM7

Cortex-M3

Highest

26 16 16 26

12 6

ISR 1

Less than 12 cycle

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Interrupt Response – Lab

Highest

IRQ1

IRQ2

ISR 2 Starts

NMI

IRQ3

Push for ISR1 begins Pre-empted by NMI

New instruction fetch in parallel minimises time to NMI

NMI ISR 1 ISR 2 ISR 3 POP PUSH PUSH

Cortex-M3 •Following NMI processor tail-chains into ISR1 •ISR2 Completed •Pop only occurs on return to “Main”

POP

More than12 cycle

Less than12 cycle

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NVIC Registers Each interrupt input has several registers to control it

Enable/Disable Bit Enable or disable the interrupt

Can be set, cleared or read

Pending Bit If the pending bit is set, then the interrupt is pending

A pending interrupt can only be taken (become active) if it is enabled and it has sufficient priority to run

Pending bit can be set, cleared or read

Active Bit A bit is set if the interrupt is executing or “active-stacked”

“Active-stacked” means the interrupt was executing, but was pre-empted by another higher-priority interrupt

Active register is normally read only

Priority field

priority management for each interrupt

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Cortex-M3 Exception Types

No. Exception Type Priority Type of Priority Descriptions

1 Reset -3 (Highest) fixed Reset

2 NMI -2 fixed Non-Maskable Interrupt

3 Hard Fault -1 fixed Default fault if other hander not implemented

4 MemManage Fault 0 settable MPU violation or access to illegal locations

5 Bus Fault 1 settable Fault if AHB interface receives error

6 Usage Fault 2 settable Exceptions due to program errors

7-10 Reserved N.A. N.A.

11 SVCall 3 settable System Service call

12 Debug Monitor 4 settable Break points, watch points, external debug

13 Reserved N.A. N.A.

14 PendSV 5 settable Pendable request for System Device

15 SYSTICK 6 settable System Tick Timer

16 Interrupt #0 7 settable External Interrupt #0

…… ………………….. ……………… settable …………………..

256 Interrupt#240 247 settable External Interrupt #240

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Cortex-M3 Processor



Power Management


Debug Capabilities

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Flexible system timer

24-bit self-reloading down counter with end of count interrupt generation

2 configurable Clock sources

Suitable for Real Time OS or other scheduled tasks

In STM32F10x the SysTick clock can be: CPU clock or CPU clock/8 (provided externally by the Reset Clock Control )

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What is ARM ? Why use an ARM-based processor?

Cortex-M3 Processor Cortex-M3 Processor Main Features Data Memory Instruction Pipeline

Write Buffer

Privilege, Modes, Stacks and Register Set Cortex M3 interrupt handling

Exception/Interrupt Handling, NVIC Registers Cortex-M3 Exception Types Vector Table

Cortex-M3 Memory Map Power Management System Timer (SysTick) Debug Capabilities

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Debug Capabilities

JTAG

SWD More pins available for the application

Three solutions are possible :

Serial Wire Debug for targeted low bandwidth data trace

Enhanced Thematic Mapper capability for better real time debugging ♦ Instruction trace only

Joint Test Action Group easy flashed application debugging ♦ 2 hardware breakpoints 8 hardware breakpoints

ETM

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PART - II

STM32F10x Device

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CONTENTS Objectives

STM32F10x Device Block Diagram

Memory mapping and boot modes

System Architecture

STM32F10x System Peripherals Main features

STM32F10x Minimum External Components

STM32F10x standard peripheral Library What is CMSIS?

Package organization

STM32F10xxx standard peripheral library architecture

Coding conventions

Using the Library

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OBJECTIVES

Familiarize with STM32F10x device

At the end of the training you will be able to List the main features of the STM32F10x system

peripherals Configure the standard library environment Develop your applications using the STM32F10x

standard library

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CONTENTS Objectives



System Architecture






Coding conventions

Using the Library

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More choice with STM32 series

The general purpose F-1 series addresses a wide range of applications, from the lowest price-sensitive design to the computing intensive, high memory Footprint

Get the highest performance with the F-2 series for computing intensive application and advanced connectivity. The F-2 series maintains the compatibility with the F-1 series.

Get the highest performance with the Design ultra-low-power applications with the L-1 series for those who are power conscious and seek the absolute lowest energy consumption. The L-1 series maintains the compatibility with the F-1 series.

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STM32 portfolio based on F1 series

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CORTEXTM-M3 CPU

24 MHz

4kB SRAM

ARM

® P

erip

hera

l Bus

2

(max

24M

Hz)

1 x I2C

1 x USART/LIN Smartcard / IrDa Modem Control

37/51 I/Os

Up to 16 Ext. ITs

Flas

h I/F

16kB - 32kB Flash Memory

JTAG/SW Debug

XTAL oscillators 32KHz + 4~25MHz

Power Supply Reg 1.8V

POR/PDR/PVD

DMA 7 Channels

Nested vect IT Ctrl

1 x USART/LIN Smartcard/IrDa Modem Control

1 x SPI

Bridge

Bridge

ARM

Lite

Hi-S

peed

Bus

M

atrix

/ Ar

bite

r (m

ax 2

4MH

z)

Int. RC oscillators

40KHz + 8MHz

PLL

Clock Control RTC / AWU

ARM® Peripheral Bus 1 (max 24MHz)

20B Backup Data

1 x 12-bit ADC

up to 16 channels

Temperature Sensor

2 x Watchdog (independent & window)

5 x 16-bit timer 1 x CEC

2-channel 12-bit DAC

1 x Systick Timer

1 x 16-bit PWM Synchronized AC Timer

Core and operating conditions ARM® Cortex™-M3 1.25

DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 °C

LQFP48, LQFP/BGA64

Advanced analog 12-bit1.2 µs conversion time ADC Dual channel 12-bit DAC

Enhanced control 16-bit motor control timer 5x 16-bit PWM timers

Rich connectivity 5 communications peripherals

STM32 Value line 16K-32KBytes block diagram

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CORTEXTM-M3 CPU

24 MHz

ARM

® P

erip

hera

l Bus

2 (m

ax 2

4MH

z)

2 x I2C

1 x SPI


37/51/80 I/Os

Up to 16 Ext. ITs

JTAG/SW Debug


POR/PDR/PVD

DMA 7 Channels

Nested vect IT Ctrl


1 x SPI

Bridge

Bridge

1 x Systick Timer

ARM

® L

ite H

i-Spe

ed B

us

Mat

rix /

Arbi

ter (

max

24M

Hz)

RTC / AWU

ARM® Peripheral Bus1 (max 24MHz)


Int. RC oscillators

40KHz + 8MHz

PLL

8kB SRAM

Flas

h I/F

64kB - 128kB Flash Memory

Clock Control

20B Backup Data

1 x 12-bit ADC up to16 channels

Temperature Sensor


6 x 16-bit Timer 1 x CEC


1 x 16-bit PWM Synchronized AC Timer



LQFP48, LQFP/BGA64, LQFP100

Advanced analog 12-bit1.2 µs conversion time ADC Dual channel 12-bit DAC

Enhanced control 16-bit motor control timer 6x 16-bit PWM timers



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LQFP64, LQFP100, LQFP144

FSMC SRAM, NOR, memories support. LCD Parallel interface 8/16-bit Intel 8080 and Motorola 68K

Enhanced control

16-bit motor control timer 10x 16-bit PWM timers


CORTEXTM-M3 CPU

24 MHz

AR

M®

Per

iphe

ral B

us 2

(m

ax 2

4MH

z)

2 x I2C


51/80/112 I/Os

Up to 16 Ext. ITs

FSMC SRAM/ NOR/ LCD parallel

interface

JTAG/SW Debug


POR/PDR/PVD

DMA up to 12 Channels

Nested vect IT Ctrl


1 x SPI

Bridge

Bridge

1 x Systick Timer

AR

M ®

Lite

Hi-S

peed

36u

s M

atrix

/ A

rbite

r (m

ax 2

4MH

z)

RTC / AWU

ARM® Peripheral Bus 1 (max 24MHz)


Int. RC oscillators 40KHz + 8MHz

PLL

24KB-32kB SRAM

Flas

h I/F

256KB-512kB Flash Memory

Clock Control

84B Backup Data


1 x 12-bit ADC up to 16 channels

Temperature Sensor


10 x 16-bit Timer

2 x SPI

1 x CEC 1 x 16-bit PWM

Synchronized AC Timer

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Memory Mapping and Boot Modes

BOOT Mode Selection Pins Boot Mode Aliasing

BOOT1 BOOT0

x 0 User Flash

User Flash is selected as boot space

0 1 SystemMemory SystemMemory is selected as boot space

1 1 Embedded SRAM

Embedded SRAM is selected as boot space

Boot modes: Depending on the Boot configuration - Embedded Flash Memory - System Memory - Embedded SRAM Memory is aliased at @0x00

Addressable memory space of 4 GBytes RAM : up to 32 kBytes FLASH : up to 512 kBytes

SystemMemory: contains the Bootloader used to re-program the FLASH through USART1.

CODE

SRAM

Peripherals

0x0000 0000

0x2000 0000

0x4000 0000

0xE010 0000

0xFFFF FFFF

Reserved

Reserved

Reserved

0x0800 0000

0x0801 FFFF

0x1FFF F000

0x1FFF F7FF

Flash

SystemMemory

Reserved

Reserved

Option Bytes 0x1FFF F800

0x1FFF F80F

Cortex-M3 internal

peripherals 0xE000 0000

0xE00F FFFF

Reserved

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STM32F10x :Boot Modes

•Boot mode = System Memory For applications where firmware update is performed frequently (example: Satellite receiver, Playsattion, etc…).

CPU System memory

(Boot Loader)

Flash

(Application Code)

Bus Matrix UART ata packets (code)

The CPU executes the boot loader:

1) Data packets containing code are Received through through serial peripheral (UART).

2) The Flash is reprogrammed with the new received code

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CONTENTS Objectives



System Architecture






Coding conventions

Using the Library

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STM32F101x Series Block Diagram

CORTEXTM-M3 CPU

24 MHz

AR

M®

Per

iphe

ral B

us

(max

24M

Hz)

2 x I2C


51/80/112 I/Os

Up to 16 Ext. ITs

FSMC SRAM/ NOR/ LCD parallel

interface

JTAG/SW Debug


POR/PDR/PVD

DMA up to 12 Channels

Nested vect IT Ctrl


1 x SPI

Bridge

Bridge

1 x Systick Timer

AR

M ®

Lite

Hi-S

peed

36u

s M

atrix

/ A

rbite

r (m

ax 2

4MH

z)

RTC / AWU

ARM® Peripheral Bus (max 24MHz)


Int. RC oscillators 40KHz + 8MHz

PLL

24KB-32kB SRAM

Flas

h I/F

256KB-512kB Flash Memory

Clock Control

84B Backup Data


1 x 12-bit ADC up to 16 channels

Temperature Sensor


10 x 16-bit Timer

2 x SPI

1 x CEC 1 x 16-bit PWM

Synchronized AC Timer

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Power Control (PWR) and Backup Domain (BKP)

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Power Supply

VSS

VDD

VBAT

VDDA

VSSA

VREF-

VREF+ A/D converter Temp. sensor Reset block PLL

VDDA domain

LSE crystal 32K osc BKP registers RCC BDCR register RTC

Backup domain

Core Memories Digital peripherals

V18 domain VDD domain

STANDBY circuitry (Wake-up logic, IWDG, RCC CSR reg)

Voltage Regulator

I/O Rings

Low Voltage Detector

• Power Supply Schemes

VDD = 2.0 to 3.6 V: External Power Supply for I/Os and the internal regulator.

VDDA = 2.0 to 3.6 V: External Analog Power supplies for ADC, Reset blocks, RCs and PLL.

ADC working only if VDDA ≥ 2.4 V

VBAT = 1.8 to 3.6 V: For Backup domain when VDD is not present.

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Power On Reset / Power Down Reset

• Integrated POR(Power On Reset )/ PDR(Power Down Reset ): circuitry guarantees proper product reset when voltage is not in the product guaranteed voltage range (2V to 3.6V) No need for external reset circuit

• POR and PDR have a typical hysteresis of 40mV

VDD

POR

PDR 40mv hysteresis

Reset

Vtrh

Vtrl

Tempo 2ms

Vtrl min 1.8V / Vtrh max 2V

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Programmable Voltage Detector (PVD)

• Programmable Voltage Detector(PVD) Enabled by software Monitor the VDD power supply

by comparing it to a threshold Threshold configurable from

2.2V to 2.9V by step of 100mV

VDD

100mv hysteresis

PVD Output

PVD Threshold

Threshold

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Low Power Modes STM32F10x Low Power modes: uses CortexM3 Sleep

modes SLEEP, STOP and STANDBY modes The reset circuitry, POR/PDR, is active in STANDBY and STOP modes

Feature STM32F10x typ (*)

Consumption in RUN mode w/ execute from Flash on internal RC and peripherals clock ON

4.9mA

Consumption in RUN mode w/ execute from Flash on PLL 24 MHz (HSE : external clock = 8MHz) and peripherals clock ON

36mA

Consumption in RUN mode w/ execute from Flash on PLL 24 MHz (HSE : external clock = 8MHz) and peripherals clock OFF

27mA

STOP w/ Voltage Regulator in low power Low speed and high-speed internal RC oscillators and high-speed oscillator OFF(no independent watchdog)

14µA

STANDBY w/ low-speed oscillator and RTC OFF Low-speed internal RC oscillator and independent watchdog OFF

2µA

RTC on VBAT 1.4 µA

(*) : Typical values are measured at TA = 25 °C, VDD/VBAT = 3.3 V.

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CONTENTS Objectives



System Architecture






Coding conventions

Using the Library

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What is CMSIS? • Definition: The Cortex-M3™ Microcontroller Software Interface Standard (CMSIS) is defined in close cooperation with various silicon and software vendors and provides a common approach to interface to peripherals, real-time operating systems and middleware components. For more details, please refer to www.onarm.com.

• CMSIS layer structure

http://www.onarm.com/�

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Cortex-M3 exceptions

- STM32 interrupt IRQ list/ Specific options for the Cortex-M3 core - STM32 peripheral memory mapping and physical register address definition - Configuration options …

Peripheral header file

Include NVIC and SysTick drivers

Low-level & API functions to Perform basic operations offered by the peripheral

User application

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Using the Library (1/4) 1) Before configuring a peripheral, you have to enable its clock by calling one of the

following functions: RCC_AHBPeriphClockCmd(RCC_AHBPeriph_PPPx , ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_PPPx , ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_PPPx , ENABLE);

2) PPP_DeInit(..) function can be used to set all PPP’s peripheral registers to their

reset values: PPP_DeInit(PPPx);

3) If after peripheral configuration, the user wants to modify one or more peripheral

settings he should proceed as following: PPP_InitStucture.memberX = valX; PPP_InitStructure.memberY = valY; PPP_Init(PPPx, &PPP_InitStructure);

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Using the Library (2/4) At this stage the PPP peripheral is initialized and can be enabled by

making a call to PPP_Cmd(..) function: PPP_Cmd(PPPx, ENABLE); Note: This function is used only for communication peripherals like UART,

SPI, …

To access the functionality of the PPP peripheral, the user can use a set of dedicated functions. These functions are specific to the peripheral and for more details refer to STM32F10x Firmware Library User Manual.

Example of GPIO Functions available

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Using the Library (3/4) UART1 configuration example : /* Enable USART1 Clock */ RCC_APB2PeriphClockCmd( USART1, ENABLE );

/* set all UART1’s peripheral registers to their reset values */ USART_DeInit( USART1 ) ;

/* USART1 configuration ------------------------------------------------------*/ /* USART1 configured as follow: - BaudRate = 19200 baud - Word Length = 8 Bits - One Stop Bit - Even parity - Hardware flow control disabled (RTS and CTS signals) - Receive and transmit enabled */ USART_InitStructure.USART_BaudRate = 9600; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_Parity = USART_Parity_Even; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; /* Configure USART1 */ USART_Init( USART1, &USART_InitStructure); /* Enable USART1 */ USART_Cmd( USART1, ENABLE );

USART 1 is ready now …

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Using the Library (4/4)

stm32f10x_It.h /* Exported functions ----------------------------------------------- */ void NMI_Handler(void); void HardFault_Handler(void); … stm32f10x_It.c #include "stm32f10x_it.h" … void EXTI1_IRQHandler(void) { GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); }

main.c #include "stm32f10x.h“ int main(void) { ... GPIO_WriteBit(GPIOD, GPIO_Pin_1, Bit_SET); … }

stm32f10x_conf.h /* Includes ------------------------------------------------------------------

*/ /* Uncomment the line below to enable peripheral header file

inclusion */ /* #include "stm32f10x_adc.h" */ /* #include "stm32f10x_bkp.h" */ /* #include "stm32f10x_can.h" */ … … stm32f10x.h /* Uncomment the line below according to the target STM32

device used in your application */ #if !defined (STM32F10X_LD) && !defined

(STM32F10X_MD) && !defined (STM32F10X_HD) /* #define STM32F10X_LD */ /*!< STM32 Low density

devices */… #endif … /* STM32F10x Interrupt Number Definition*/ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */

• Files to be modified by the user:

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PART - III

STM32 Value line Discovery Kit

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STM32 Value line Discovery Kit

Microcontroller Division of MMS Group June, 2010

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The cheapest and quickest way to discover the STM32

Everything included for a quick start with the STM32 Value Line Price: $9.90 (RRP) Order code: STM32VLDISCOVERY Available NOW from ST and Distributors

In circuit ST-LINK debugger / programmer included to debug

Discovery kit applications or other target board applications.

Ideal for quick evaluation, learning or prototyping

Dedicated web site www.st.com/stm32-discovery Examples ready to run Schematics Forums and more…

66

http://www.st.com/stm32-discovery�

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STM32 Value line Discovery Board A compact “all in one board”

The debugger “ST-link” is on

the board itself

Few leds and button for immediate usage

The extension connector will all STM32 pins enable building more complex applications by using an extension board

The board can be used as an independent ST-link for your own board if needed

67

42mm

84mm

ST-LINK

STM32F100RBT6B

User button

Led Green Led Blue

SWD connector

Extension connector On each side

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Tools and Software

68

Development Toolchain support Free Atollic TrueSTUDIO® lite version with unlimited code-size and usage-time. IAR EWARM KEIL MDK-ARM

Software examples available at www.st.com/stm32-discovery for a quick start to evaluate and develop with the STM32 Value line

http://www.st.com/stm32-discovery�

http://images.google.fr/imgres?imgurl=http://www.soccentral.com/SOCContent/Logos/Atollic.gif&imgrefurl=http://www.soccentral.com/results.asp?EntryID=29672&usg=__DOhxBHUpyQxmtVngGzgu6LDpPEg=&h=49&w=225&sz=7&hl=fr&start=8&tbnid=bX_CP9oUcnwGKM:&tbnh=24&tbnw=108&prev=/images?q=atollic&gbv=2&hl=fr&safe=off�

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Features and Benefits

69

Feature Benefit

STM32F100RBT6B microcontroller Discover STM32 with STM32 Value line, including 128-Kbyte Flash, 8-Kbyte RAM in a 64-

pin LQFP Self powered by USB cable between PC and

STM32 Value line Discovery Immediate plug-and-play demonstration

Can supply target application with 5 V and 3 V Adapts the demo to the future application environment

On-board ST-Link with USB interface for programming and debugging

Non-intrusive debug with the in-circuit debugger present on STM32 Value line Discovery.

Selection mode switch to use the kit as a standalone ST-Link (with SWD connector)

The kit can be used as an ST-link for your own board

Extension header for all QFP64 I/Os Ideal for prototyping and easy probing. Enable quick connection to a prototyping board

Development toolchains from partners Complete kit enabling full software development, no need for additional software.

Large number of free, downloadable ready-to-use software examples

Fast startup, accelerate your developments.

More than 37 Videos are available on YouTube web site. example: link : http://www.youtube.com/watch?v=5Si0tgqrAd0

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STM32F100xx Value Line necessary docs RM0041 (Reference Manual): Peripherals description…

PM0063 (Flash Programming Manual): Flash description…

Product Datasheet STM32F100x468B-B: Electrical parameters…

STM32F10x Standard Peripheral Library V3.3.0: STM32 value Line Firmware

library, examples…

AN3268 (STM32VLDISCOVERY firmware package): STM32 discovery Firmware library…

UM0919 (STM32VLDISCOVERY STM32 value line Discovery): STM32 discovery board description, schematics…

UM0985 (Developing your STM32VLDISCOVERY application using the IAR Embedded Workbench software): Tools description...

All docs are available from www.st.com/mcu

http://www.st.com/mcu�

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Contact us

1- Systèmes Embarqués Consulting: µC (STM32, PIC...), Embedded C, VHDL… a. Email: [email protected] b. Page faceBook :https://www.facebook.com/Systemes.Embarques.Consulting c. Marketing phone number: +216 52 02 16 71

2- Linux embarqué Consulting (Embedded Linux) a. Email: [email protected] b. Page faceBook : https://www.facebook.com/Linux.embarque c. Marketing phone number: +216 52 02 16 71 3- Formation RH: Interview, CV,… a. Email: [email protected] b. Page faceBook : https://www.facebook.com/FormationRH c. Marketing phone number: +216 21 33 33 91

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Now you are able to…

Develop your application around STM32F100 device

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Thank you

stm32_training_12w06_1v0 (1)

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