STIL FilePresented By:

ContentsPurpose of STILWhats in a STIL file?STIL KeywordsCapture ProceduresNamed Capture ProceduresComparing Generic Captures FlowsScan Compression Architecture EDT ArchitectureOCC Structure Definition

Purpose of STILSTIL is a test data description language approved by IEEE as Std 1450.0 in 1999. STIL is pronounced as the word style in English.

STIL is an approved IEEE standard used for simplifying the number of test vector formats that ATE vendors and computer-aided engineering (CAE) tool vendors must support.

Facilitates the transfer of digital test vector data from CAE to ATEenvironments.

Specifies pattern, format, and timing information to define theapplication of digital test vectors to a DUT.

Supports the volume of test vector data generated from structured tests.

Whats in a STIL file?

STIL KeywordsSTIL 1.0 { Design P2000.9;}The STIL keyword defines the version of STIL in the file. It is the first statement of any STIL file encompassing files opened from the Include statement.Header { Title "DFT Compiler 2004.06 STIL output"; Date "Wed July 7 12:59:09 2004"; History { }}

The Header block provides title and date creation information. The Header block is optional. If it is present, it must be the first statement after the STIL statement for a file.

STIL KeywordsSignals { "ASIC_TEST" In; "SE" In; "a[0]" In; "a[1]" In; "a[2]" In; "a[3]" In; "b[0]" In; "b[1]" In; "b[2]" In; "b[3]" In; "c[0]" In; "c[1]" In; "c[2]" In; "c[3]" In; "clk" In; "d[0]" Out; "d[1]" Out; "d[2]" Out; "d[3]" Out; "e[0]" Out; "e[1]" Out; "e[2]" Out; "e[3]" Out;}

The Signals section lists all of the inputs, outputs, and bi-directional signals for the design under test. The Signals block is required.

STIL KeywordsSignalGroupsTetraMAX has a number of predefined signal groups it recognizes. A SignalGroup is a method in STIL to describe a list of pins using a symbolic label. _in = input pins_out = output pins_io = bidirectional pins_pi = inputs + bidirectional pins_po = outputs + bidirectional pins_si = scan chain inputs_so = scan chain outputsSignalGroups { "all_inputs" '"ASIC_TEST" + "SE" + "a[0]" + "a[1]" + "a[2]" + "a[3]" + "b[0]" + "b[1]" + "b[2]" + "b[3]" + "c[0]" + "c[1]" + "c[2]" + "c[3]" + "clk"'; // #signals=15 "all_outputs" '"d[0]" + "d[1]" + "d[2]" + "d[3]" + "e[0]" + "e[1]" + "e[2]" + "e[3]"'; // #signals=8 "all_ports" '"all_inputs" + "all_outputs"'; // #signals=23 "_pi" '"all_inputs"'; // #signals=15 "_po" '"all_outputs"'; // #signals=8}Example:

STIL KeywordsScanStructuresScan chains are defined in the STIL ScanStructures block. The following example shows four scan chains.

ScanStructures { ScanChain "chain1" { ScanIn "edt_channels_in[0]"; ScanOut "edt_channels_out[0]"; } ScanChain "chain2" { ScanIn "edt_channels_in[1]"; ScanOut "edt_channels_out[1]"; } ScanChain "chain3" { ScanIn "edt_channels_in[2]"; ScanOut "edt_channels_out[2]"; }}

STIL KeywordsTiming { WaveformTable "_default_WFT_" { Period '100ns'; Waveforms { "clk" { 0 { '0ns' D; } } "clk" { P { '0ns' D; '45ns' U; '55ns' D; } } "clk" { 1 { '0ns' U; } } "clk" { Z { '0ns' Z; } } "dtp_clk" { 0 { '0ns' D; } } "dtp_clk" { P { '0ns' D; '45ns' U; '55ns' D; } } Timing BlockAll pulsed ports including clocks and asynchronous sets and resets are defined in the Timing block of the STIL file.

STIL Keywords_launch_WFT__capture_WFT__launch_capture_WFT_WaveformTable "_launch_WFT_" { Period 40ns; Waveforms { "CLK1" { 01Z { 0ns D/U/Z; } } "CLK1" { P { 0ns D; 5ns U; 10ns D; } } "_default_In_Timing_"{01ZN {0ns D/U/Z/N; } } "_default_Out_Timing_"{X {0ns X; } } "_default_Out_Timing_" { HLT { 0ns X; 4ns H/L/T; } } } } WaveformTable "_capture_WFT_" { Period 40ns; Waveforms { "CLK1" { 01Z { 0ns D/U/Z; } } "CLK1" { P { 0ns D; 30ns U; 35ns D; } } "_default_In_Timing_"{01ZN {0ns D/U/Z/N; } } "_default_Out_Timing_"{X {0ns X; } } "_default_Out_Timing_" { HLT { 0ns X; 4ns H/L/T; } } } } Transition Testing in STIL file

STIL KeywordsProcedures

The procedures section defines a set of test data to be used multiple times in a Pattern.Procedures { "load_unload" { V { CLOCK = 0; RESETB = 1; SCAN_ENABLE = 1; } Shift { V { _si=####; _so=####; CLOCK=P; } } }}

Capture Procedures"capture_CLOCK" {W "_default_WFT_";"forcePI": V { "_pi"= \r10 # ; }"measurePO": V { "_po"=######; }"pulse": V { "CLOCK"=P; }}

"capture_CLK" { W "_default_WFT_"; V { "_pi"=\r 10 # ; "_po"=\r 6 #; "CLK"=P; } }

Named Capture Procedures"capture_RSTB" { W "_default_WFT_"; "force_and_measure": V { "_pi"=\r 10 # ; "_po"=\r 6 #; } "pulse": V { "RSTB"=P; } } Defining PI Constraints in STIL "multiclock_capture" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1; "scan_pipeline_enable"=0; } V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }}"sequential_capture"W "_default_WFT_";F {"test_mode"= 1; }V {"_pi"= \r48 #; "_po"= \r12 X ; }V {"CLK1"= P; CLK2= #; }V {"CLK3"= P; }V {"_po"= \r12 #; }}

Comparing Generic Captures Flows Procedures {"multiclock_capture" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_capture" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_launch" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1; } V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_launch_capture" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }}}Procedures {"multiclock_capture" { W "_default_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_capture" { W "_capture_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_launch" { W "_launch_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1; } V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }} "allclock_launch_capture" { W "_launch_capture_WFT_"; F { "edt_bypass"=1; "scan_mode_i"=1;} V { "_pi"=\j \r280 #; "_po"=\j \r263 #; }}}SA FlowTF Flow

STIL KeywordsTest SetupThe "test_setup" macro is optional. It defines any initialization sequences that the design might need for test mode, or to ensure that the device is in a known state. Some of the tasks, which are frequently done in a test_setup procedure are:place device in ATPG test modeplace clocks at their off statesinitialize constrained portsinitialize bi-directional ports to Zinitialize JTAG

MacroDefs { "test_setup" { W "_default_WFT_"; V { "edt_bypass"=1; "scan_mode_i"=1; "scan_pipeline_enable"=0; "clk"=0; "dtp_clk"=0; "fpi_clk_i"=0; "ptd_clk"=0; "dtp_reset_n"=1; "fpi_reset_n_i[0]"=1; "fpi_reset_n_i[1]"=1; "mbist_nrst"=1; "ptd_reset_n"=1; "resn"=1; "mem_red_RESETB_i"=1; } }}Example

OCC Structure Definition