status of the r&d on maps in strasbourg and frankfurt outline: operation principle of maps (a...

Status of the R&D on MAPS in Strasbourg and Frankfurt

Outline:• Operation principle of MAPS (a reminder)• Fast readout• Radiation hardness• System integration and material budget• Summary and Conclusion

S. Amar, G. Bartone, J. Baudot, A. Besson, G. Claus, C. Colledani, M.Deveaux, A. Dorokhov, G. Dozière, W. Dulinski, C. Dritsa, X.Fang, J.C. Fontaine, I. Fröhlich, M. Goffe, D. Grandjean, S. Heini,

A. Himmi, C. Hu, M. Koziel, K. Jaaskelainen, F. Morel, C. Muentz, N. Pillet, C. Schrader, A. Shabetai, J. Stroth, M. Szelezniak, I. Valin, B. Wiedemann, M. Winter (Project coordinator MAPS)

The operation principle of MAPS

Particle trajectory

~20µm

Preamplifier (one per pixel)

Diffusing free electrons

A Minimum Ionising Particle creates ~80 e-/h-pairs per µm in Si

Collection with build in voltages and thermal diffusion

~ 30µm

Diode

P++

P++P-

N

P++ = Highly P-doped

The MIMOSA - Technology

Minimum Ionizing Particle MOS Active Pixel Sensor

Features of the MIMOSA – detectors:

• Single point resolution 1.5µm - 2.5µm

• Pixel – pitch 10-40 µm

• Thinning achieved 50 - 120µm

• S/N for MIPs 20 – 40

• Detection efficiency > 99%

• Radiation hardness: 1MRad ; 2 x 1012 neq/cm²

• Produced in various commercial CMOS-Processes

MIMOSA IV

Main R&D Directions

Fast readout and good time resolution

• Improvement of analog electronics• Integration of zero suppression

Radiation hardness

• Search for improved sensors (pixel design, production process…)

System integration and reliability

• Study complex sys-tems composed of numerous chips

Thinning and material budget

• Thinning of Chips• Feasibility studies on thin support structures

Column parallel readout is demonstrated but needs improvement. Data sparsification logic remains to be developed.Goal: A readout time of ~ 10µs for CBM

Pixel array ~1000 on - chip discriminators

Data sparsifi-cation logic

Output: Cluster information(zero suppressed)

Concept:

Sensor Blind area





MIMOSA-16 • Designed in AMS-0.35µm Opto • 32 columns of 128 pixels (25 µm pitch)• On-pixel CDS• On-chip discriminator• Improved version of the successful MIMOSA-8

Pixel array

~ On - chip discriminator


Beam test at CERN – SPS in early September

CAD – Layoutof MIMOSA-16

Some results are labelled „Private and preliminary“:

Data is roughly 2 weeks old, very preliminary analysis. Only the few results shown are stabilized (might still get better).



MIMOSA-16D

etec

tio n

eff

icie

n cy

[ %]

Good reference design (4.5 x 4.5 µm² diode)Collection diode too small (2.4 x 2.4 µm²)

Detection efficiency of referencedesign is > 99 %

For some pixels, the collection diodewas chosen to small (insufficient CCE)

Fake hit rate at typical discriminator threshold (> 4 mV) < O(10-4)

S/N (MIMOSA-8) = ~ 8-9S/N (MIMOSA-16) = ~ 16-17

10-8

10-2

Note:Spatial resolution: 5-6 µmDigital resolution: 7.2 µmClustering helps despite of digital output

A. Besson

A. Besson

MIMOSA-16 Fast readout and good time resolution


Mean number of firing pixels/hit varies between 2.5 and 6

A. Besson

Sig

nifi

cant

pix

els

/ hit



MIMOSA-16

Pixel multiplicity in clusters has a wide distribution.One can hardly accept only clusters with >1 significant pixel!

IPHC-StrasbourgCEA-Saclay

3.5 mV

7.8 mV

A. Besson (modified)

4.5 x 4.5µm² - diode

Pixel array



Next generation prototype MIMOSA-22 under preparation : • Coll. length = 640 pixel (needs different design of steering and readout busses)• Pixels smaller (18.4 x 18.4 µm²), needs smaller discriminators• Slow control with JTAG• 128 colls. digital, (+ 8 analogue for debugging/test purpose)

Submission planned for 27. October 2007Tests planned February 2008



MIMOSA-16 works very well . . .

but leaves room for improvement:• Too short col. lengths • Pixels still too big (25 x 25 µm²) => limited radiation hardness



Pixel array


Data spasifi-cation logic

First test of on-chip implementation

Close to hardware but inflexible

Only digital part, (not yet combined with sensor)

Not (yet) designed for beam tests

FPGA-based solution

Flexible for testing different strategies

Use existing chips as sensor

Compatible with HADES – DAQ

Test in HI-experiment is possible (MVD demonstrator)

See talk of C. Schrader

SUZE – 1 chip



The readout architecture of SUZE-1:

Integrated logic:-Step 1 (inside blocks of 64 colls) identify up to 6 series of up to four significant pixels / line

-Step 2 Read-out outcome of step-1 in all blocks, keep up to 9 series of four pixels

• Surface: ~ 3.6 x 3.6 mm²

• Still too slow for CBM but sufficient for STAR-HFT and EUDET (FP6)• Submitted for fabrication, back from foundry in October• Test completed by end of year

• Next generation chip is scheduled for 2008 (faster logic)

4 output memories ( 512 x 16 bits)



MIMOSA-22 sensor + discriminator:• 640 pixels per coll. x 1088 colls (more than Mi-22, surface ~1 x 2 cm²)• Pixel pitch 18.4 x 18.4 µm²• Integration time ~ 100 µs

+ SUZE-1 data sparsification logic

Pixel array


Data spasifi-cation logic

MIMOSA-22+ = MIMOSA-22 + SUZE-1

Final sensor for EUDET - Telescope

Submission planned October 2008

Radiation hardness• Study of pixel designs• Study of dedicated production processes• Cryogenic detector operation

Limitation of the non-ionizing radiation hardness:

Reduced charge carriers lifetime => Signal electrons recombine before being collected

Strategy to improve: A) Speed up charge collection time B) Use thicker sensor, produce more initial signal C) Recover lifetime of electrons

How to do it: A) Reduce pixel pitch, shorter way, faster collection

40 µm => ~1011 neq / cm², 20 µm => ~1012 neq / cm² (MIMOSA-9)Try to modify pixel structure for faster collection (MIMOSA-21)

B) Use sensors with thicker epitaxial layer (20µm instead 14µm)C) Try cryogenic detector operation

Main concern for CBM: Non-ionizing radiation hardness


Study of MIMOSA-18 Smaller pixels, thicker sensor

Status:

• First beam tests: June 2007 (DESY) – non irradiated chips• Irradiated samples now available• Systematic studies of irradiated chips: In Frankfurt by the end of the year

MIMOSA-18

Designed: 2006

• 512 x 512 pixels• 10µm pixel pitch (faster charge coll.)• Sensor thickness: 14µm and 20µm


Study of MIMOSA-18: Thicker sensor, beam test at Desy (June 2007)

Room for Mi18 Beamtest results

S/NElectrons

ENC

[electrons]

[ENC]

Results show no clear preference

C. Dritsa (preliminary)




Additional charge is observed in the periphery of the clusters only.Benefit of thick sensor is smaller than expected.Next step: Confirm with irradiated chips => Frankfurt


Study of MIMOSA-18: Thicker sensor, beam test at Desy (June 2007)


Study of the ST-BICMOS 0.25µm process (MIMOSA-21)

Features:• Lowly doped (50 Ω cm) substrate for sensors

Allows depleting a bigger part of the volume => Faster charge collection

• Deep N-Well implantation Faster charge collection Higher capacity (how much higher?) Higher dark current (how much higher?) Higher noise ? Ionising radiation hardness?

N-Well

Deep N-Well

Standard N-Well diode.Diffusing electron may miss it.

N-WellDeep

N-Well

Deep N-Well diode.Expect faster collection time.

Signal electron starting point

Possible trajectory

10 µm pitch


N-WellDeep

N-Well

N-WellDeep

N-Well

So far: Chips without epitaxial layer => Study diode properties Chips with epitaxial layer are under design

Preliminary results (at 20°C, tInt = 40 ms => unfavorable conditions):

Leakage current : 0.5 fA (OK)Noise : 19 ENC (still OK)(No shot noise) : 15 ENC (OK)CCE : Not Available

Leakage current : 0.5 fA (OK)Noise : 19 ENC (still OK)(No shot noise) : 15 ENC (OK)CCE : Not Available

Both pixels show satisfactory noise performances combined with extraordinary low leakage current. Next step: Address radiation hardness. Build chips with epi-layer

Lower layer is missing!

Study of the ST-BICMOS 0.25µm process (MIMOSA-21)

Lower layer is missing!

Recombination destroys the signal

Efficient approach for depleted N-doped detectors. BUT: MAPS are P-doped and undepleted.


Cryogenic detector operation:Passivate signal traps by cooling



MIMOSA-18 (?)

Support, LN2 cooled Support, “water” cooled@ room temperature

Mimosa – Readout board

PCB

Vias for thermalcontact

Challenges: Build a test system • Chip operation at very low temperature => Isolate with vacuum• Operate readout board at warmer temperatures (reduce problems)• Transfer signals out of vacuum

Prelim

inary co

ncept

Input is

welc

ome



A vacuum vessel is being build at Frankfurt.

Mission:

• Cryogenic MAPS operation

• Test of MVD components under vacuum conditions.

• Volume sufficient to test full detector stations

Status: • First vacuum tests are ongoing. • Experiments located in the device are still under design.

Thinning and material budget• Thinning of Chips• Feasibility studies on thin support structures

CVD – Diamond (50 – 100 µm)

Printed Circuits (Al, 3 µm)

MIMOTel (50 µm) MIMOTel (50 µm)Contact

Project goal: Build a super thin ladder of MAPS detectors with ~ 0.1 % X0

Project partners:• IPHC – Strasbourg (MAPS production and coordination)• Diamond Materials, Freiburg (CVD- diamond production)• IZM – Munich (Lithography, system integration and bonding)

Operation Diamond

Project is started but ambitious fundamental research. Risks are sizeable.Thickness of diamond aims to ILC, insufficient for our cooling requirements?

(More about material budget: See talk of C. Müntz)

Summary and Conclusion:

Fast column parallel architecture:- MIMOSA-16 beam tests demonstrated substantial improvements- First data sparsification chip is curently fabricated- Integrate sensors and data sparsification (MIMOSA-22+, in 2008)- FPGA board for studying interface MAPS to CBM-DAQ is under design

Radiation tolerance issues:- Interesting fab. processes are under study (20µm, deep N-Well)- Cryogenic chip operation is under preparation

Integration issues:- Design of MVD-Demonstrator is started at Frankfurt- Integration of CVD-Diamond + Silicon is under investigation by Strasbourg and partners.


Study of MIMOSA-18, MIMOSA-19Smaller pixels with modified structure

Standard pixel (Mimosa-18)

Hit and

diff. e-

Collectingdiode

Mimosa – 19 pixel

Status: MIMOSA-18 is running in Strasbourg and FrankfurtMIMOSA-19 produced, tests under preparationIrradiation is done

Better charge collection?

More charge/pixel?

Higher capacity/lower gain

Higher noise?

Higher dark current?

MIMOSA-18 (Standard – pixel, 10 µm pitch) MIMOSA-19 (Particular diode, 12 µm pitch)

General Status

Strasbourg:

• Tests of the chips produced in 2006 are ongoing (MIMOSA-16 to MIMOSA-21 + ADCs)• Chip design activities focus on fast readout• Specific prototypes are developed for radiation hardness issues• R&D on very thin support structures has started

Frankfurt:

• Equipment still being completed• Preparation for tests on cryogenic chip operation• First simple radiation hardness studies were performed; systematic studies under preparation (MIMOSA-18, MIMOSA-19)• Intense R&D on MVD demonstrator

status of the r&d on maps in strasbourg and frankfurt outline: operation principle of maps (a...

Documents

readout time

mdigital resolution

suppressionfast readout

cbmfast readout

spatial resolution

sn mimosa

pixel pitch

single point resolution