status of cbm-gas-xyter
TRANSCRIPT
SchaltungstechnikSimulationund
SchaltungstechnikSimulationund
Status of CBM-GAS-XYTER
15th CM @ GSI
April 2010
Latest Results of the Self-Triggered Digitizer Chip
13.04.10 15th CBM CM - Tim Armbruster 2LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
1. Introduction
13.04.10 15th CBM CM - Tim Armbruster 3LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Requirements/Motivation
• Application:
– Main task: gas chamber readout for CBM TRD
– Application in other FAIR detectors also conceivable
• We need a self-triggered readout chip that has:
– 32-64 mixed-signal channels
– Low noise & power charge amplification (order of 1000e ENC @ 30pF det.)
– Bandwidth limitation (2nd order shaper or higher, about 90ns shaping time)
– Digitization (7-10 bit @ 5-30 MHz)
– Time stamping (necessary time resolution depends on ADC sample speed)
– In-channel data processing (ion tail cancellation, baseline correction, ...)
– Inter-channel network (e.g. token ring network)
– Inter-chip network (pass the data to the next stage)
13.04.10 15th CBM CM - Tim Armbruster 4LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Conceptual Data Flow Diagram
tokenring
prev.chip
nextchip
ADC IIR
hitdetector
hits to and from neighbors
chargepulse
digitalanalog
output logic
+driver
13.04.10 15th CBM CM - Tim Armbruster 5LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Status of Development
tokenring
ADC IIR
hitdetector
hits to and from neighbors
chargepulse
Preamp, Shaper, ADC
• Several test-ASICs successfully realized
• First test-chip including an ADC (next to last chip) showed promising results as shown in Split
• Preliminary measurement results of current test-chip will be presented
Hit detector, data generator and token ring
• Design of data flow and control concept completed
• 1st iteration of Verilog description finished
• First simulation results will be presented
Infinite Impulse Response Filter (IIR)
• Theoretically well understood, abstract Mathematica calculations completed
• Simplified Verilog description has been written
• First simulation results will be presented
13.04.10 15th CBM CM - Tim Armbruster 6LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
2. Current Test-Chip Architecture
13.04.10 15th CBM CM - Tim Armbruster 7LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Block Diagram of Current ASIC
preamp 25 shaper 25
SR 0preamp 0 shaper 0
ADC 0
Analog Bias12 x 7 Bit current DAC
Shift RegisterControl
8
8
8
8
8
8
8
8
Output MUXand
Decoder16
9
Testand
CalibrationCircuits
ADC 7 SR 7
ESD Pad
ESD Pad
ESD Pad
ESD Pad
ESD Pad
ESD Pad
ESD Pad
ESD Pad
8 complete channels (ESD pad, CSA, ADC, output decoder)
13.04.10 15th CBM CM - Tim Armbruster 8LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Current Test-Chip: Layout
Bias circuitry (12 current DACs)26 preamp/shaper channelsDetector capacitors (5pF per block)8 pipelined ADCs
ADC control + bias 5.2 kBit shift register matrixControl + readout/decoder logic blocksTest circuits
13.04.10 15th CBM CM - Tim Armbruster 9LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Reminder: Preamplifier/Shaper Circuit
H s ≈ADC
1sRSCS2
RS RS
CS
CS
11x 1x
(also channels with less
instances for test purpose
on chip)
• O'Connor FB
• 2nd order shaper
• Shaping time: 82 ns
• Unified amplifier cell
• N-MOS input
• ≈ 3.6 mW/channel
New:
• Scaled lengths of input NMOS (180, 250, 320, 390, 460nm)
• Re-Layout of input NMOS: The (long) gate-fingers have been cut into smaller pieces to decrease gate resistance
06.10.09 14th CBM CM - Tim Armbruster 10LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Reminder: Algorithmic ADC Design
U to I
compa-rator
currentin/out
write
write & read
Vref digitalout
current mode
voltage node
digital domain
storage node
• 8 (scaled) pipeline stages, therefore 9 Bit design
• Algorithmic working principle (“1.5 redundant Bits” / conversion step)
• 25 MSamples/s, layout only 130x120 µm², power consumption 4.5 mW
• Core unit: Novel current storage cell:
13.04.10 15th CBM CM - Tim Armbruster 11LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
3. Measurement Results
13.04.10 15th CBM CM - Tim Armbruster 12LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Test Setup
13.04.10 15th CBM CM - Tim Armbruster 13LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Shaper Pulse
prelim
inary
Channel with ESD pad (oscillation)
“Normal” channel shaper output
13.04.10 15th CBM CM - Tim Armbruster 14LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Noise Results
Measurement
Simulation
750e ENC @ 30pF
prelim
inary
• New layout of input NMOS had no impact on noise results
• Large deviation between channel types can't be seen in simulation
• 320nm is the best choice
13.04.10 15th CBM CM - Tim Armbruster 15LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Characteristic ADC Curve
preliminary
1 ADC @ 12 MSamples/s1 value/step, 1000 steps
8 ADCs @ 12 MSamples/s20 values/step, 500 steps
13.04.10 15th CBM CM - Tim Armbruster 16LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Digitized Pulses
preliminary
@ 12 MSamples/sseveral digitized shaper pulses
13.04.10 15th CBM CM - Tim Armbruster 17LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
4. Digital Development
13.04.10 15th CBM CM - Tim Armbruster 18LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
IIR Filter (Ion Tail Cancellation) Diagram
<< +
FF
a0
FF
+
+
+
>>
a1
a2
b0
b1
b2
N11
N12
N00
N01x
N02
N10 N20
N21
N22
0,1,2 0,1,2
0,1,2 0,1,2
5,6,7
0
0
0,1,23 4
3
34
3
cycle ncycle n+1
N01
N21x
N00x N20x
D1
D0 D3
D2
● Direct form 2● 2nd order →
compensation of two exponents
● Need at least 5 multipliers (complicated)
● Need 4 adders (simple)
● Need to find out proper internal resolution
13.04.10 15th CBM CM - Tim Armbruster 19LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Mathematica: IIR Filter (Ion Tail Cancellation)
ADC Output(triple pulse with
different amplitudes)
ADCvalues
time
Theoretical optimum(no quantization)
Filter resultwith a quantization step after each multiplication
(undershoot)
Mathematica Simulation
13.04.10 15th CBM CM - Tim Armbruster 20LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Digital Simulation: IIR Filter (Ion Tail Cancellation)
Digital Simulation (Verilog)
● RED: IIR filter input pulse with very long ion tail● BLUE: IIR output after ion tail cancellation (preliminary results)
– strong overcompensation, but probably due to quantization (compare to Mathematica results)
– adjustment of filter factors should lead to better results
preliminary – very first results
13.04.10 15th CBM CM - Tim Armbruster 21LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Digital Hit Detector and Package Builder
input buffer(FIFO)
input buffer(FIFO)
hit synchronization
hit synchronization
hitdetector
hitdetector
meta data generator (logic only)
meta data generator (logic only)
main control(FSM)
main control(FSM)
start of frameFIFO
start of frameFIFO
IIR data (9)
threshold (9)
hit length (6)
max hit length (6)
neighbor hits (2)
internal hit (1)
hit
hit type (2),TS latched (12)
data selector
data selector
output buffer (FIFO)
output buffer (FIFO)
start of frameFIFO
start of frameFIFO
# values sent (6),control (9) write enable (2),
almost full (2)
global TS (12)
inte
r ch
annel
net
work
(to
ken r
ing)
meta data (9)mixed data (10)
select (1)
13.04.10 15th CBM CM - Tim Armbruster 22LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Example 1: Internal Hit
Token bus output package:
SOF: 16 data packages sentTS1: 000000 (part 1)TS2: 011011 (part 2)DATA: 12DATA: 42DATA: 47DATA: 40DATA: 30DATA: 26[...]DATA: 5DATA: 4DATA: 3EOF: internal hit
hitdetector
IIR
dataselector
+metadata
generatorADC
tokenring
connector
hit to and from neighbor global data (TS, ...) token in
token out
hitsync
toke
n r
ing d
ata
bus
13.04.10 15th CBM CM - Tim Armbruster 23LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Example 2: External Hit
Token bus output package:
SOF: 16 data packages sentTS1: 000000 (part 1)TS2: 111000 (part 2)DATA: 2DATA: 2DATA: 2DATA: 2DATA: 2[...]DATA: 2DATA: 2DATA: 2DATA: 2EOF: external hit
hitdetector
IIR
dataselector
+metadata
generatorADC
tokenring
connector
hit to and from neighbor global data (TS, ...) token in
token out
hitsync
toke
n r
ing d
ata
bus
13.04.10 15th CBM CM - Tim Armbruster 24LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Example 3: Internal Double Hit
Token bus output package:
SOF: 25 data packages sentTS1: 000010 (part 1)TS2: 010000 (part 2)DATA: 12DATA: 42[...]DATA: 16HTP: internal hitTS1: 000010 (part 1)TS2: 011001 (part 2)DATA: 23DATA: 51[...]DATA: 3EOF: internal hit
hitdetector
IIR
dataselector
+metadata
generatorADC
tokenring
connector
hit to and from neighbor global data (TS, ...) token in
token out
hitsync
toke
n r
ing d
ata
bus
“double hit marker”
13.04.10 15th CBM CM - Tim Armbruster 25LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
5. Excursion to UMC 90nm
13.04.10 15th CBM CM - Tim Armbruster 26LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
CSA Submission in UMC 90nmMotivation
• UMC 90nm technology available via Europractice
• Still a lot of free space on our first 90nm multi-design test-chip (VCO, SRAM, CMOS-counter, …)
• Large deviation between measured and simulated noise in 180nm
• General discussion in analog design: 180nm vs. 90nm
=> Submission of a simple CSA design (preamp, shaper, discriminator) on March 22, 2010
3 CSA channels in UMC 90nm + Bias
13.04.10 15th CBM CM - Tim Armbruster 27LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
90nm CSA Characteristics
Characteristics from simulation
• 3 channels with on-die detector capacitors (0pF, 12.6pF, 25.2pF)
• NMOS input, O'Connor feedback, 2nd order shaper
• Peaking-Time: 83ns, Rise-Time: 47ns
• Power consumption: 2.3mW (VDD 1.0V)
• Noise: 377e @ 20pF
• Note: no optimization, minimum on-chip bias circuitry, 5 days of work for the whole design
13.04.10 15th CBM CM - Tim Armbruster 28LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
90nm CSA Shaper Output Pulse
Shaper Output
Discriminator Output
Gain: 33.6mV/fC(curve: 4.2fC input charge,
20pF detector cap.)
CMOS output only due to pad limitation
13.04.10 15th CBM CM - Tim Armbruster 29LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
6. Future Plans and Summary
13.04.10 15th CBM CM - Tim Armbruster 30LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Floor Plan Proposal
Bias
Slow Control and Data I/O
Post
-Pro
cess
ing /
Rea
dout
Preamp/Shaper IIRInj. ADC
3 mm
2m
m
300µm
det
ecto
r ch
annel
pitch
Detector Pads Bias + Power Pads Digital I/O
Preamp/ShaperIIR Inj.ADC
● 3 x 2 mm² estimated die size● 32 channels, 40-80µm pitch, (mostly) symmetric layout, low(er) IR-drops● Detector connection-pads on two sides (chips will probably be attached to back of detector-
module, this relaxes routing/spacing)
13.04.10 15th CBM CM - Tim Armbruster 31LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Summary
Status of analog chip design:
• Measurement results so far promising
• Further tests still have to be done (find optimal settings, test ESD pads, connect CSAs to ADCs, ...)
Status of digital channel back-end design:
• First design proposal of digital back-end completed
• Good simulation results, ongoing development of larger verification environment
• Large construction site: IIR filter (good topic for a diploma thesis)
Next Steps:
• Complete chip measurement
• Connect chip to some gas-chamber (e.g. from Frankfurt)
• Start tests of digital channel back-end on some FPGA board
• Maybe submit a completely digital test-ASIC
• Do first steps towards the CBM-GAS-XYTER design (layout concept, ...)
• Find a better name for CBM-GAS-XYTER
13.04.10 15th CBM CM - Tim Armbruster 32LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Thank you!
13.04.10 15th CBM CM - Tim Armbruster 33LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Raw Data vs. Extracted Data: System Options le
vel o
f int
egra
tion
digitalfilterADC
analog front-end
hitdetector
Neighbor readout trigger
windowselection FPGA
raw data (samples + header)
CBM-GAS-XYTER ROC
Neighbor readout trigger
datasel.
FPGAmixed data (raw + extracted)
Combination ofneighbor-data
valid hit
dataextractionanalog
front-endADC digital
filterhit
detector
Combination ofneighbor-data
Neighbor readout trigger
FPGAextracted datadata
extractionanalog
front-endADC
digitalfilter
hitdetector
Combination ofneighbor-data
Neighbor data request
FPGAcombined extracted datadata
extractionanalog
front-endADC digital
filterhit
detector
Extractedneighbor-data
datacomb.
neighbor
transmission channel
max. chip rate ≈ 1.1 Gbpsavg. chip rate ≈ ???
max. chip rate ≈ 500Mbpsavg. chip rate ≈ ???
max. chip rate < 500Mbpsavg. chip rate ≈ ???
13.04.10 15th CBM CM - Tim Armbruster 34LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Chip: Preamp/Shaper Results
• Noise was measured with s-curve scans using the discriminator
• Injection capacitor calibrated via test circuit
• 4 different preamplifier types: old, normal, no triwell, long
• Results:
– Noise values of normal (triwell NMOS input, minimal length) and no triwell (NMOS without triwell, minimal length) channel show no significant difference compared to the old channel => values still much worse than simulated
– Noise slope of long (triwell NMOS input, 320 nm length) channel about two-times smaller => about 800 e ENC @ 30 pF achievable, still worse than in simulation
13.04.10 15th CBM CM - Tim Armbruster 35LS Schaltungstechnik & Simulation
SchaltungstechnikSimulationund
Chip: ADC Results
ADC characteristic curve• Measured @ 24 MSamples/s• Logic runs with 196 MHz CLK• Readout via dynamic SR buffer• Output decoded on chip• 7-8 Bit effective