statistical approach to detection of hardware virtualization based rootkits
DESCRIPTION
There exist many methods of detection of this malware type, and as many ways to prevent them. In this paper, I chose a detection method based on the time-stamp counter (TSC) and ways to prevent this detection, such as modification of the TSC and Blue Chicken technology. To develop the ways to detect hypervisor I did mining and modeling of CPU behavior. I designed the models (two directed multigraphs) of CPU behaviour in cases when hypervisor is present or not. With the help of models of CPU behavior, I discovered hidden relationships between variability of time duration of certain instructions in various CPU states. I suggested that we could use certain statistical values such as variance, fourth moments and others to detect a hypervisor or several nested ones. Experimental verification of the models built with the help of the Kolmogorov Criterion showed that a 5% significance level the model data are consistent with experimental data. The statistical values grow when we install a hypervisor. The hypervisor can modify only the mean values, but it cannot change these variation values. I took into consideration lack of repeatability and reproducibility of experimental results. This method was implemented in the as a program and driver for Windows. This tool was successfully tested and implemented on various workstations, laptops and hypervisors.TRANSCRIPT
Statistical Approach to Detection of Hardware Virtualization Based Rootkits
Igor KorkinAdviser: Prof. T.V. Petrova
February 2012
o There are no legitimate tools to detect a hypervisor and nested ones either.o A hypervisor is likely to be run illegally and include malware payload.o A hypervisor can prevent its detection with the help of TSC
cheating and Blue Chicken technology.
History of the problem
2
How PC works in cases of no hypervisor and after it has been installed:
Nowadays there are many computer systems that use CPU with hardware virtualization support and on the other hand there is no tool to detect hypervisor with certainty.
Operation system 2
Virtual machine 2
Hardware
Operation system
Hardware
PC without hypervisor
PC is controlled by two nested hypervisors
Operation system 1
Virtual machine 1
hypervisorinstallation
Trusted hypervisor
Hypervisor rootkit
Research aims
3
o Analysis of statistical characteristics of trace execution latencies in cases when hypervisors are present or not;
o Creation of a criterion of hypervisorsβ presence under the condition that the hypervisors can prevent their detection;
Hypervisor is able to cheat TSC and as a result we can see that mean trace execution latencies in cases when hypervisors are present are similar to their values in case when there is no hypervisor. Therefore, a new statistical approach has to be found.
The main tasksβ Comparative analysis and classification of existing methods and tools of hypervisors detection.β Research into processorβs instructions execution latencies in cases when hypervisors are present or not. β Design and analysis of execution trace models in cases when hypervisors are present or not. β Creation of criteria for hypervisorsβ presence under the condition that the hypervisors can prevent their detection.β Research into statistical characteristics of trace execution latencies in cases when hypervisors are present or not; and testing of the criteria.β Development of hypervisor detection tool.
4
Hypervisor detection methods
Timing Behavioural
Signature based
Based on TLB
Based on RSB
Based on instructions trapped by hypervisor
Based on TLB
Based on memory walk
Based on bugs in hypervisors and
CPUs
Proactive
Hypersight Rootkit Detector McAfee's DeepSAFE
DeepWatch (JTAG port) Co-Pilot (PCI card)
Based on a trusted hypervisor
Based on hardware
Based on software
The suggested classification of hypervisor detection methods
5
My method is based on the difference in trace execution latencies in cases when hypervisors are present or not
Comparative analysis of existing hypervisors detection tools
Name of the tool
Ability to detect Convenience in usage and distribution
Detection of nested
hypervisorsnon stealthy hypervisor
stealthy hyperviso
rHypersight
Rootkit Detector+ β + β
Symantec Endpoint
Protection+ β + β
McAfee Deep Defender
+ β + βDeepWatch + + β β
Co-Pilot + + β β
6
Experimental software samples
+ β + β
Virtual machine
Hypervisor
OperationsystemTRACE
DT
HardwareTSC
Analysis of timing detection method which is based on instructions trapped by hypervisor
Trace β a set of CPUID instructions.
7
No cheating TSC
Cheating TSC
No hypervisor 2*103 2*103
Hypervisor is present 2*105 2*103
Mean trace execution latencies in ticks:
Hypervisor cheats TSC
How to get statistical data:β’ read TSC value;β’ execute 10 CPUID instructions;β’ read TSC value again;β’ calculate the trace execution latency.
*DT β detection tool
Switching between CPU modes in cases when hypervisor is present or not
8
In case of no hypervisor
Hypervisor is present
Protected mode(R-mode)
System Management
Mode(S-mode)
SMM entry
SMM exit
VM exit
VM entryVMX non root mode (R-mode)
VMX root mode (V-mode)
System Management Mode
(S-mode)
System Management Mode
(S-mode)
SMM entry
SMMexit
SMM entry
SMMexit
Execution trace model in case of no hypervisor (NH)
9
Trace execution latency with n0 CPUID instructions:
(p,ns)
(q,0) (q,0). .
. .
(p,ns)
π1 π2 ππ0 π‘ππ» = αΊπ0 + πππ»βππα»βπ π is one instruction execution latency in ticks π0 is the number of CPUID instructions in the trace ππ are instructions in the trace, π = 1,..,π0 ππ is the number of instructions in the SMM dispatcher π is the probability of the fact, that the switch between R- and S- mode occurred (along a lower arc) π is the probability of the fact, that the switch between R- and S- mode did not occur (along a higher arc, π = 1β π) πππ» is the random variable, which means how many numbers of switches between R- and S- mode occur. Its values are binomially distributed, parameters π0 and π.
Execution trace model in case when hypervisor is present (HP) under the condition that it can prevent its detection
10
Trace execution latency with π0 CPUID instructions: π‘π»π = αΊπ0 + π0 βππ+ ππ»π βππ+ π0 βπΏα»βπ
Hypervisor dispatcher
(p,ns)
(q,0)
(p,ns)
(q,0) (q,0)
(p,ns)
(q,0)
(p,ns)
(q,0)
(p,ns)
(q,0). .
. .
. .(p,ns)
π is one instruction execution latency in ticks π0 is the number of instructions in the trace; ππ β instructions in the trace, π = 1,..,π0 ππ is the number of instructions in the hypervisor dispatcher; ππ are instructions in the hypervisor dispatcher, π= 1,..,ππ ππ is the number of instructions in the SMM dispatcher π is the probability of the fact, that the switch to S- mode occurred (along a lower arc) π is the probability of the fact, that the switch to S- mode did not occur (along a higher arc, π = 1β π) πΏ is the value of TSC cheating ππ»π is the random variable, which means how many numbers of switches to S- mode occur. Its values are binomially distributed, parameters (π0 + π0 βππ) and π
0 10 20 30 40 50 60 70 80 90 1002915
2920
2925
2930
2935
2940
ΠΠΎΠΌΠ΅ΡΠ° ΠΈΠ·ΠΌΠ΅ΡΠ΅Π½ΠΈΠΉ
ΠΡΠ΅
ΠΌΡ Ρ
ΡΠ°ΡΡ
Ρ Π²
ΡΠ°ΠΊ
ΡΠ°Ρ ,
tGraphs of theoretical distribution of trace execution latencies
in cases when hypervisor is present or not and under the condition that it prevents its detection
11
Hypervisor is present
Hypervisoris not present
Parameters values:k=2920 p=0.004 d=-20n0=10 ns=200 nv=200
Number of repeated measurements
Trac
e ex
ecut
ion
late
ncie
s, ti
cks
π0,ππ,ππ,πΏ,π ββ€; πββ are some fixed values. πππ» is range of values, received from π‘ππ», ππ»π is range of values, received from π‘π»π. π: π= πππ»βππ»π. π₯Τ¦π = (π₯1,..,π₯π) is a sample from π. Hypervisor presence criterion based on the variance. Critical set (hypervisor is present): π= {π₯Τ¦π:πΰ·οΏ½οΏ½2αΊπ₯Τ¦πα»β₯ π},
where πΰ·οΏ½οΏ½2 is sample variance, πββ€ is experimentally defined. Making a decision: if π₯Τ¦π βπ, it means a hypervisor is present; if π₯Τ¦π βπ, it means there is no hypervisor.
Hypervisor presence criterion based on the fourth central moments. Critical set (hypervisor is present): π= {π₯Τ¦π:πΰ·οΏ½οΏ½2αΊπ₯Τ¦πα»β₯ π},
where πΰ·οΏ½οΏ½2 is sample fourth central moment, πββ€ is experimentally defined. Making a de-cision: if π₯Τ¦π βπ, it means a hypervisor is present; if π₯Τ¦π βπ, it means there is no hyper-visor.
Hypervisor presence criterion based on the length of variation series. Critical set (hypervisor is present): π= {π₯Τ¦π:πααΊπ₯Τ¦πα»β₯ π},
where πα is length of variation series, πββ€ is experimentally defined. Making a decision: if π₯Τ¦π βπ, it means a hypervisor is present; if π₯Τ¦π βπ, it means there is no hypervisor.
12
Hypervisors presence criterions
Theorem. For sampling from tNH and tHP prove the existence of the hypervisor presence criterion.
Experimental check of hypervisors presence criteria
β The experiments were carried out as single-factor experiments:
β The variable factor is the PC state in cases when a hypervisor is present or not.
β Statistics of trace execution latencies were analyzed.
β The results were 1000Ρ 10 matrix, including measurements data of trace execution latencies in cases when a hypervisor is present or not. (Π’HP and Π’NH)
β According to ISO 5725 experiments were carried out in series of 5 repeated cases during 10 days until the data stabilized.
13
0 10 20 30 40 50 60 70 80 90 1002915
2920
2925
2930
2935
2940
ΠΠΎΠΌΠ΅ΡΠ° ΠΈΠ·ΠΌΠ΅ΡΠ΅Π½ΠΈΠΉ
ΠΡΠ΅
ΠΌΡ Ρ
ΡΠ°ΡΡ
Ρ Π²
ΡΠ°ΠΊ
ΡΠ°Ρ ,
t
14
Experimental results. Graphs of distribution of trace execution latencies in cases when hypervisor is present or
not and under the condition that it prevents its detection
Hypervisor is present
Hypervisor is not present
Experimental results fromIntel Core 2 Duo E8200 Windows 7
Number of repeated measurements
Trac
e ex
ecut
ion
late
ncie
s, ti
cks
PC Statistics Filtration level π
Threshold values Probability of errors Hypervisor is
not present Hypervisor is present Type I, Ξ± Type II, Ξ²
1 πΏΰ΄€π 0 β€ 7 β₯ 8 0.04 0 π·ΰ΄₯π 0 β€ 14 β₯ 18 0.02 0 πΰ΄₯π 0.1 β€ 679 β₯ 947 0.02 0
2 πΏΰ΄€π 0 β€ 11 β₯ 12 0.1 0.06 π·ΰ΄₯π 0.2 β€ 100 β₯ 101 0.08 0.1 πΰ΄₯π 0.2 β€ 168 β₯ 13030 0.14 0.02
3 πΏΰ΄€π 0 β€ 34 β₯ 241 0 0 π·ΰ΄₯π 0 β€ 216 β₯ 5478 0 0 πΰ΄₯π 0.02 β€ 54 β₯ 956 0 0
πΏΰ΄€π is the mean length of variation series, π·ΰ΄₯π is the mean variance, πΰ΄₯π is the mean fourth central moments.
Threshold values of statistics
15
#1 β Intel Core 2 Duo E8200, Windows 7, #2 β Intel Core 2 Duo E6300, Windows 7,#3 β AMD Phenom X4 945, Windows Live CD XP (DDD)
My hypervisor was used in PCs #1 and #2. Special BIOS hypervisor was used in PC #3.
16
Algorithm of getting threshold values of trace execution statistical characteristics
Input data: noneOutput data: statistics, their filtration levels and threshold values
Choose threshold values SN H,[f] and SHP,[f] whereby error I
and error II are minimal
End
From matrixes TN H and THP get filtered arrays TN H,f and THP,f for
the following filtration levels f={0; 0,02; 0,05; 0,1; 0,15; 0,2}
Calculate the statistical characteristics SN H,f and SHP,f for the arrays TN H,f and THP,fGet matrixes TN H and THP of trace
execution latencies with (and without) a hypervisor
Entry
17
Hypervisor detection algorithmInput data: statistics, their filtration levels and threshold values.Output data: a solution about hypervisorsβ presence
Get the matrix of trace execution latency TΠ’ΠSΠ’
Entry
Calculate statistical characteristics SΠ’ΠSΠ’,[f]
SΠ’ΠSΠ’,[f] β€ SN H,[f]T
F
End
SΠ’ΠSΠ’,[f] β₯ SHP,[f]
Hypervisor is present
Hypervisor is not present
F
T
Get the array TΠ’ΠSΠ’,[f] after filtering of matrix TΠ’ΠSΠ’
Input characteristics: SN H,[f] , SHP,[f] and [f]
Phase Description Pr
epar
ator
y 1. Upgrade BIOS software with trusted BIOS-image with the help of a programmer.
2. Install OS. 3. Get threshold values for hypervisor detection with the
help of the corresponding algorithm.
Ope
ratio
nal 4. Repeatedly check the system to see if a hypervisor
is present. 5. Install additional software (MS Office etc). 6. Monitor messages about a hypervisor detection. 7. To adapt the detection tool to the legitimate hypervisor
do step 3 again.
Approach to hypervisor detection
18
OSBIOS image
Additional software
Software updates
?
19
Hypervisor detection tool architecture
Hypervisor detection subsystem
Threshold values creation subsystem
Threshold values
Intruderβs activity imitation subsystem
Hypervisorβs start and stop
Ope
rati
onal
ph
ase
Pre
para
tory
ph
ase
Ability to detect stealthy hypervisors
Convenience in usage and distribution
Detection of nested hypervisors
+ + +
o Execution trace models were designed for the cases when hypervisors are present or not
o Hypervisors presence criteria were created. They are based on the variance, fourth moments, and length of variation series of trace execution latencies
o Algorithms of hypervisor detection were developedo Hypervisors detection software tool was developed.
It has the following advantages:
20
The main results