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5.2.2 STATIC Memories:

Memories that consist of circuits capable of retaining their state as long as

power is applied are known asstatic memories.

Two inverters are cross-connected to form a latch. The latch is connected

to two bit lines by transistors T1and T2. These transistors act as switches that

can be opened or closed under control of the word line. When the word line is atground level, the transistors are turned off and the latch retains its state.

Read Operation:

In order to read the state of the SRAM cell, the word line is activated to close

switches T1and T2. It the cell is in state 1, the signal on bit line b is high and

the signal on bit line b'is low. The opposite is true if the cell is in state O.

Thus, b and b'are complements of each other. Sense / Write circuits at the end

of the bit lines monitor the state ofb and b'and set the output accordingly.

Write Operation:The state of the cell is set by placing the appropriate value on bit line b and its

complement on b', and then activating the word line. This forces the cell into the

corresponding state.

The required signals on the bit lines are generated by the Sense / Write circuit.

DMA: To transfer large blocks of data at high speed, an alternative approach is

used. A special control unit may be provided to allow transfer of a block of data

directly between an external device and the main memory, without continuous

intervention by the processor. This approach is called direct memory access, orDMA.

Although a DMA controller can transfer data without intervention by the

processor, its operation must be under the control of a program executed by the

processor.

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A DMA controller connects a high-speed network to the computer bus. To start

a DMA transfer of a block of data from the main memory to one of the disks, a

program writes the address and word count information into the registers of the

corresponding channel of the disk controller. It also provides the disk controller

with information to identify the data for future retrieval. The DMA controller

proceeds independently to implement the specified operation. When the DMA

transfer is completed, this fact is recorded in the status and control register of

the DMA channel by setting the Done bit. At the same time, if the IE bit is set,the controller sends an interrupt request to the processor and sets the IRQ bit.

The status register can also be used to record other information, such as whether

the transfer took place correctly or errors occurred.

7.3 Multiple bus organization (3 bus organization):

A three-bus structure used to connect the registers and the ALU of a processor.All general-purpose registers are combined into a single block called the

register file. In VLSI technology, the most efficient way to implement a number

of registers is in the form of an array of memory cells similar to those used in

the implementation of random-access memories (RAMs) described in Chapter

5. The register file in Figure 7.8 is said to have three ports. There are two

outputs, allowing the contents of two different registers to be accessed

simultaneously and have their contents placed on buses A and B. The third port

allows the data on bus C to be loaded into a third register during the same clock

cycle.Buses A and B are used to transfer the source operands to the A and B inputs of

the ALU, where an arithmetic or logic operation may be performed. The result

is transferred to the destination over bus C. If needed, the ALU may simply pass

one of its two input operands unmodified to bus C. We will call the ALU

control signals for such an operation R=A or R=B. The three-bus arrangement

obviates the need for registers Y and Z in Figure 7.1.

A second feature in Figure 7.8 is the introduction of the Incrementer unit,

which is used to increment the PC by 4. Using the Incrementer eliminates the

need to add 4 to the PC using the main ALU, as was done in Figures 1.6 and7.7. The source for the constant 4 at the ALU input multiplexer is still useful. It

can be used to increment other addresses, such as the memory addresses in Load

Multiple and Store Multiple instructions.