stanford university © giovanni de micheli abstract models...
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MODELING LANGUAGESAND
ABSTRACT MODELS
© Giovanni De MicheliStanford University
Chapter 3 in book,please read it.
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OutlineOutline• Hardware modeling issues:• Representations and models.• Issues in hardware languages.• Abstract hardware models:
– Data flow and sequencing graphs.
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Circuit modelingCircuit modeling
• Formal methods:– Models in hardware languages.– Flow and state diagrams.– Schematics.
• Informal methods:– Principles of operations.– Natural-language descriptions.
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Hardware Description Languages
• Specialized languages with hardwaredesign support.
• Multi-level abstraction:– Behavior, RTL, structural.
• Support for simulation.• Try to model hardware as designer
likes to think of it.
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Software programming languages
• Software programming languages (C) can modelfunctional behavior.–– Example:Example: processor models.
• Software language models support marginally designand synthesis.– Unless extensions and overloading is used.– Example: SystemC.
• Different paradigms for hardware and software.• Strong trend in bridging the gap between software
programming languages and HDLs.
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Hardware versus software models• Hardware:
– Parallel execution.– I/O ports, building blocks.– Exact event timing is very important.
• Software:– Sequential execution (usually).– Structural information less important.– Exact event timing is not important.
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Language analysis• Syntax:
– External look of a language.– Specified - by a grammar.
• Semantics:– Meaning of a language.– Different ways of specifying it.
• Pragmatics:– Other aspects of the language.– Implementation issues.
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Language analysis
• Procedural languages:– Specify the action by a sequence of steps.– Examples: C, Pascal, VHDL, Verilog.
• Declarative languages:– Specify the problem by a set of
declarations.– Example:Example: Prolog.
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Language analysis• Imperative semantics:
– Dependence between the assignments and thevalues that variables can take.
–– Examples:Examples: C, Pascal.• Applicative semantics:
– Based on function invocation.–– Examples:Examples: Lisp, Silage.
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Hardware languages and views• Physical view:
– Physical layout languages.– Declarative or procedural.
• Structural view:– Structural languages.– Declarative (with some procedural features).
• Behavioral view:– Behavioral languages.– Mainly procedural.
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Summary
• Hardware synthesis requires specialized language support.• VHDL and Verilog HDL are mainly used today:
– Similar features.– Simulation-oriented.
• Synthesis from programming languagesSynthesis from programming languages is also possible.– Hardware and software models of computation are different.
– Appropriate hardware semantics need to be associatedwith programming languages.
• Abstract models:– Capture essential information.– Derivable from HDL models.– Useful to prove properties.
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Structural view
• Composition of blocks.• Encoding of a schematic.• Incidence structure.• Hierarchy and instantiation.• HDL examples:
– VHDL, Verilog HDL, ...
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Example(half adder)
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Verilog examplestructural
representationmodule HALF_ADDER (a , b ,
carry ,sum); input a , b; output carry, sum; and g1 (carry, a , b); xor g2 (sum, a , b);endmodule
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Behavioral viewprocedural languages
• Set of tasks with partial order.– Logic-level:
• Tasks: logic functions.
– Architectural-level:• Tasks: generic operations.
• Independent of implementation choices.• HDL examplesHDL examples:
– VHDL, Verilog HDL, ...
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Verilog exampleBehavior of combinational logic circuit
module HALF_ADDER (a , b , carry , sum); input a , b; output carry, sum; assign carry = a & b ; assign sum = a ^ b ;endmodule
Stands for exoroperator
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Verilog examplebehavior of sequential logic circuit
module DIFFEQ (x, y, u , dx, a, clock, start);input [7:0] a, dx;inout [7:0] x, y, u;input clock, start;reg [7:0] xl, ul, yl;always begin begin wait ( start); while ( x < a ) begin xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + (u * dx); @(posedge clock); x = xl; u = ul ; y = yl; endendmodule
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Behavioral view declarative languages
• Combinational circuits:– Set of untimed assignments.– Each assignment represents a virtual logic gate.– Very similar to procedural models.
• Sequential circuits:– Use timing annotation for delayed signals.– Set of assignments over (delayed) variables.
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Silage example
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Silage example
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Issues in hardware languages
• Mixing behavior and structure.– Controlling some implementation details.
• Primitive elements and variablesemantics.– Multiple-assignment problem.
• Timing semantics.– Synthesis policies.
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Behavior versus structure
• Express partitions in design.• Pure behavior is hard to specify.
– I/O ports imply a structure.– Hierarchy may imply structure.
• Hybrid representations.
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Example
• Pipelined processor design• Pipeline is an implementation issue.• A behavioral representation should not
specify the pipeline.• Most processor instruction sets are conceived
with an implementation in mind.• The behavior is defined to fit an
implementation model.
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Hardware primitives
• Hardware basic units:– Logic gates.– Registers.– Black-boxes (e.g. complex units, RAMs).
• Connections.• Ports.
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Semantics of variables
• Variables are implemented in hardware by:– Registers.– Wires.
• The hardware can store information or not.• Cases:
– Combinational circuits.– Sequential circuits.
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Semantics of variables
• Combinational circuits.• Multiple-assignment to a variable.• Conflict resolution.
– Oring (YLL).– Last assignment.
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Semantics of variables
• Sequential circuits.• Multiple-assignment to a variable.• Variable retains its value until reassigned.• Problem:
– Variable propagation and observability.
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Example
• Multiple reassignments:– x= 0 ; x = 1 ; x = 0 ;
• Interpretations:– Each assignment takes a cycle. --> pulse.– x assumes value 0.– x assumes value 0 after a short glitch.
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Timing semantics
• Most procedural HDLs specify a partial orderamong operations.
• What is the timing of an operation?– A posteriori model:
• Delay annotation.
– A priori model:• Timing constraints.• Synthesis policies.
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Timing semantics(event-driven semantics)
• Digital synchronous implementation.• An operation is triggered by some event:
– If the inputs to an operation change --> the operation is re-evaluated.
• Used by simulators for efficiency reasons.
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Synthesis policyfor VHDL and Verilog
• Operations are synchronized to a clock byusing a wait (or @) command.
• Wait and @ statements delimit clockboundaries.
• Clock is a parameter of the model:– model is updated at each clock cycle.
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Verilog examplebehavior of sequential logic circuit
module DIFFEQ (x, y, u , dx, a, clock, start);input [7:0] a, dx;inout [7:0] x, y, u;input clock, start;reg [7:0] xl, ul, yl;always begin begin wait ( start); while ( x < a ) begin xl = x + dx; ul = u - (3 * x * u * dx) - (3 * y * dx); yl = y + (u * dx); @(posedge clock); x = xl; u = ul ; y = yl; endendmodule
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Abstract models
• Models based on graphs.• Useful for:
– Machine-level processing.– Reasoning about properties.
• Derived from language models by compilation.
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Abstract modelsExamples
• Netlists:– Structural views.
• Logic networks– Mixed structural/behavioral views.
• State diagrams– Behavioral views of sequential logic models.
• Dataflow and sequencing graphs.– Abstraction of behavioral models.
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Data flow graphs
• Behavioral views of architectural models.• Useful to represent data-paths.• Graph:
– Vertices = operations.– Edges = dependencies.
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DataflowDataflow Example Example
xl = x + dxul = u - (3 * x * u * dx) - (3 * y * dx)yl = y + u * dxc = xl < a
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Examplexl = x + dxul = u - (3 * x * u *
dx) - (3 * y * dx)yl = y + u * dxc = xl < a
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Sequencing graphs
• Behavioral views of architectural models.• Useful to represent data-path and control.• Extended data flow graphs:
• Operation serialization.• Hierarchy.• Control- flow commands:
• branching and iteration.• Polar: source and sink.
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Example
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Example of HierarchyExample of Hierarchy
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Example of branching
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Example of iterationdiffeq {read (x; y; u; dx; a); repeat { xl = x +dx; ul = u - (3 * x * u* dx) - (3 * y * dx); yl = y +u dx; c = x < a; x = xl; u = ul; y = yl; } until ( c ) ;write (y);}
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Example of iteration
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Semantics of sequencing graphs
• Marking of vertices:– Waiting for execution.– Executing.– Have completed execution.
• Execution semantics:– An operation can be fired as soon as all its
immediate predecessors have completedexecution
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Vertex attributes• Area cost.• Delay cost:
– Propagation delay.– Execution delay.
• Data-dependent execution delays:– Bounded (e.g. branching).– Unbounded (e.g. iteration, synchronization).
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Properties of sequencing graphs• Computed by visiting hierarchy bottom-up.• Area estimateArea estimate:
– Sum of the area attributes of all vertices.– Worst-case - no sharing.
• Delay estimateDelay estimate (latency):– Bounded-latency graphs.– Length of longest path.
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Summary• Hardware synthesis requires specialized language support.
– VHDL and Verilog HDL are mainly used today:• Similar features.• Simulation-oriented.
• Synthesis from programming languages is also possible.– Hardware and software models of computation are different.– Appropriate hardware semantics need to be associated with
programming languages.
• Abstract models:– Capture essential information.
– Derivable from HDL models.– Useful to prove properties.