st7 peripherals1 st7 microcontroller training 1 - introduction 2 - core 3 - adressing modes 4 -...

ST7 PERIPHERALS 1

ST7 MICROCONTROLLER TRAINING ST7 MICROCONTROLLER TRAINING

1 - INTRODUCTION

2 - CORE

3 - ADRESSING MODES

4 - PERIPHERALS

5 - ST7 SOFTWARE TOOLS

6 - ST7 HARDWARE TOOLS

7 - STVD7

ST7 PERIPHERALS 2

Optional

ST623x BLOCK DIAGRAM

Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT

ProgramOtp / RomInterrupt

Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL

ST7 I/O PORTSST7 I/O PORTS

Optional features : AD converter 16-bit Timer 8-bit Auto Reload Timer SPI SCI I2C EEPROM Programmable OpAmp CAN

ST7 PERIPHERALS 3

ST7 I/O PORTSOverview

ST7 I/O PORTSOverview

ALL THE I/Os ARE INDIVIDUALLY SOFTWARE CONFIGURABLE USING 3 DIFFERENT REGISTERS :

DDR: Data Direction Register DR: Data Register OR: Option Register

ST72254 : 22 MULTIFUNCTION BIDIRECTIONAL I/O LINES 18 Standard I/Os (sink up to 5mA) 8 High Current I/Os (PA0-PA7 can sink up to 20mA) 6 Analog Inputs (PC0-PC5) 16 alternate Functions on 16 pins (for Timers, SPI and I2C) All the I/Os can be set-up as Interrupt inputs

ST7 PERIPHERALS 4

ST7 I/O PORTSafe I/O pin transition

ST7 I/O PORTSafe I/O pin transition

01 00 10 11

Reset State

DDR OR Mode

0 0 Floating input

0 1 Input pull- up with/without interrupt

1 0 Output Open-Drain

1 1 Output Push-Pull

ST7 PERIPHERALS 5

OuputI/OPin

Data Direction Register Bit

Latch Data Output bit

InputI/O

InputReg bit

Read / Write DDRi

Write DRi

Read DRi

SOFTWARE SELECTABLE CONFIGURATION HIGH FLEXIBILITY for software and PC board layout

ST7 I/O PORT Basic structureST7 I/O PORT Basic structure

ST7 PERIPHERALS 6

ST7 I/O PORT Settings & electrical behaviour

ST7 I/O PORT Settings & electrical behaviour

Configuration given when no external Hardware is connected the pins

InputFloating

Input Pull_up

Ouput Open Drain

OuputPush-Pull

DDR 0 0 0 0 1 1 1 1

OR 0 0 1 1 0 0 1 1

Written DR 0 1 0 1 0 1 0 1

I/O Pin Floating Floating Vdd Vdd Vss Floating Vss Vdd

Read DR X X 1 1 0 1 0 1

ST7 PERIPHERALS 7

Interrupt source

Pin 1

Pin 2

Pin N

Pin 1

Pin 2

Pin M

ST7 Interrupt Controller

Edge/level selection

Edge/level selection

Interrupt Source 1

Interrupt Source 2

Negative edge only

Negative edge and low level

Positive and Negative edge

Positive edge only

Pin 1

Pin 2

Latched

Latched

Latched

Not Latched

Interrupt generation

Miscellaneous Register

ST7 EXTERNAL INTERRUPTSST7 EXTERNAL INTERRUPTS

ST7 PERIPHERALS 8

ST7 I/O PORT Block DiagramST7 I/O PORT Block Diagram

PAD

V DD

ALTERNATEENABLE

ALTERNATE OUTPUT

1

0

OR SEL

DDR SEL

DR SEL

PULL-UPCondition

1

0ANALOG

INPUTALTERNATE

INPUTFROMOTHER

BITS

EXTERNALINTERRUPT

SOURCE POLARITYSELECTION

CMOS SCHMITTTRIGGER

REGISTERACCESS

DDR

OR

DR

DA

TA

BU

S

ST7 PERIPHERALS 9

PROGRAMMING TIPSI/O Port (1)


AD CONVERTION Each pin used by the ADC cell must be configured as floating input

(i.e. without pull-up resistors) before activating the analog input mode

ALTERNATE FUNCTION A signal coming from an on-chip peripheral can be output on a port.

In this case, the I/O is automatically configured in output mode.

A signal coming from an I/O can be an input to an on-chip peripheral. In this case, it must be configured as Input without interrupt (Floating Input).

ST7 PERIPHERALS 10



Open Drain Outputs can be used for bus driving where several devices are connected on the same line. They can be wired together to increase current drive capability

Voltages driving an Analog Input should always stay within the absolute maximum ratings (Vss-0.3V to Vdd+0.3V)

Pull-up resistors typically deliver 50µA under 5V

The toggling time on any output pin will be approximately 30ns for a 50pF load

ST7 PERIPHERALS 11

I/O Ports Configuration ExampleI/O Ports Configuration Example

Fill the dedicated I/O port registers in order to have the following configuration:

PB0:PB2 Push-Pull Output (high level)

PB3,PB4 Floating Input

PB5 Input with Interrupt

PB6 Push-Pull Output (low level)

PB7 Ouput (High Impedance)

PBDR

PBDR7 PBDR0

PBOR

PBOR7 PBOR0

PBDDR

PBDDR7 PBDDR0

ST7 PERIPHERALS 12

A/D CONVERTERA/D CONVERTER

Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 PERIPHERALS 13

ST7 AD CONVERTEROverview (1)


8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8 ANALOG CHANNELS: ST72254 : 6 inputs ST72334 and ST725xx : 8 inputs ST72171 : 6 external inputs + 2 internal inputs

FEATURE : Accuracy : 1 LSB Total Unajusted Error MAX : 1 LSB Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz)

FLAGS COCO : end of conversion (Status flag) ADON : ADC on/off bit (to reduce power consumption)

ST7 PERIPHERALS 14



LOW CONSUMPTION MODES Wait mode doesn't affect the ADC Halt mode stops the ADC.

HARDWARE ST72334 and ST725xx : Vdda and Vssa must be connected externally

respectivelly to Vdd and Vss through decoupling capacitors. ST72254 : connection done internally

RATIONETRIC In the Functionnal Range If analog voltage input > Vdd :

converted result = FFh (no overflow indication) If analog voltage input < Vss :

converted result = 00h (no underflow indication)

ST7 PERIPHERALS 15

SAMPLEANALOG

MUX

AIN0AIN1AIN2AIN3AIN4AIN5AIN6AIN7

0COCO CH0CH1CH2-- ADON

(Control Status Register) CSR

AD7 AD0AD1AD2AD3AD6 AD5

(Data Register) DR

&HOLD

Fcpu

ANALOG TODIGITAL CONVERTER

AD4

ST7 AD CONVERTERBlock diagram

ST7 AD CONVERTERBlock diagram

ST7 PERIPHERALS 16

PROGRAMMING TIPSAD Converter

PROGRAMMING TIPSAD Converter

PROCEDURE Step 1 : The analog input pins must be set-up as Input no pull-up no

interrupt Step 3 : assign a channel for the conversion (bit CH0, CH1 and CH2

in CSR register) and set the ADON bit Step 4 : Wait until COCO bit set. A continuous conversion is

performed. To reach the best accuracy, the impedance seen by the analog input pin must be

lower than 10Kohm.

Beginning of a new conversionby writing in the CSR (select the analog channel)

Continuous ADCWrite in CSR :

Stop conversionIf ADON still set : new

conversionElse stop ADCADC init :

–IO config–Channel selected

ADON bit set

t = 3µs t = 3µs t = 3µs

ST7 PERIPHERALS 17

ADC Configuration ExampleADC Configuration Example

Fill ADCCSR register in order to have an analog conversion on AIN4.

What bit has to be tested to know the end of the conversion ?

COCO ADON CH3 CH2 CH1 CH0

ADCDR

ST7 PERIPHERALS 18

ST7 16-bit TIMERST7 16-bit TIMER

Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 PERIPHERALS 19

16-bit TIMEROverview (1)16-bit TIMEROverview (1)

16-bit free running counter driven by a software configurable prescaler

4 different modes : Input capture (2 pins) : to latch the value of the counter after a

transition on the ICAPi pin Output compares (2 pins) : to control an output waveform or to

indicate when a period of time is over One pulse : generation of a pulse when an external event occurs PWM : generation of a signal with frequency and pulse length set by

software (OCR1 and OCR2)

ST7 PERIPHERALS 20

16-bit TIMEROverview (2)16-bit TIMEROverview (2)

The timer clock can be provided by : The internal clock with a configurable ratio An external source : Fext must 4 times slower than the internal clock

(ie Fmax=2Mhz)

CC1 CC0 Timer clock

0 0 Fcpu/4

0 1 Fcpu/2

1 0 Fcpu/8

1 1 External

ST7 PERIPHERALS 21

16-bit TIMER Block diagram16-bit TIMER

Block diagram

TIMER INTERNAL INTERRUPT

ST7 INTERNAL BUS

MCU-PERIPHERAL INTERFACE

16-BIT FREERUNNINGCOUNTERCOUNTER

ALTERNATEREGISTER

OVERFLOWDETECTCIRCUIT

STATUS REGISTER

LOW

BY

TE 8

16

8-BITBUFFER

16-Bit INTERNAL TIMER BUS

ICF1 OCF1 TOF OCF2 0 0 0ICF2

16

ICAP1

LOW

BY

TE

HIG

H B

YT

E

16

LOW

BY

TE

HIG

H B

YT

E

LOW

BY

TE

HIG

H B

YT

E

LOW

BY

TE

HIG

H B

YT

E

OUTPUTCOMPARE

REGISTER 1

OUTPUTCOMPARE

REGISTER 2

INPUTCAPTURE

REGISTER 1

INPUTCAPTURE

REGISTER 2

OUTPUTCOMPARE

CIRCUIT

1/21/41/8

EDGEDETECT

CIRCUIT 1ICAP2

EDGEDETECT

CIRCUIT 2

LATCH 1

LATCH 2

ICIE OCIE TOIE IEDG1 OLVL2FOLV1FOLV2 OLVL2 OC1E OC2E OPM IEDG2 EXEDGCC1PWM CC0

CC1 CC0

EXCLK

OCMP1

OCMP2

CONTROL REGISTER 1 CONTROL REGISTER 2

CPU CLOCK

EXEDG

ST7 PERIPHERALS 22

16-bit TIMERInput capture (1)


Captures the counter value upon input signal edge detection Allows an external pulse length measurement Internal safety process in case of critical interrupts timing

Edge Detector

Timer Counter Register

Input Capture RegisterICAP1A

Software Maskable Interrupt Request

ST7 PERIPHERALS 23

CC0CC1 IEDG2

ICIE

16-BIT FREE RUNNINGCOUNTER

IEDG1

(Control Register 1) CR1


ICF2ICF1 000

(Status Register) SR

ICAP1

ICAP2 EDGE DETECTCIRCUIT2

16-BIT

IC1RIC2R

EDGE DETECTCIRCUIT1



ST7 PERIPHERALS 24

16-bit TIMEROuput compare (1)

16-bit TIMEROuput compare (1)

Event generation (Interrupt request/bit toggling) whenever the compare register matches the counter

Indicates a period of time has elapsed and controls an output waveform

Internal safety process in case of critical interrupts timing

Match?Software Maskable Interrupt RequestPulse generation

Timer Counter Register

Output Compare Register

ST7 PERIPHERALS 25

(Status Register) SR

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R

16-BIT FREE RUNNINGCOUNTER

OC1E CC0CC1OC2E

OLVL1OLVL2OCIE



000OCF2OCF1

16-bit

16-bit

OCMP1

OCMP2

Latch 1

Latch 2

OC2R

16-bit TIMEROutput compare (2)

16-bit TIMEROutput compare (2)

ST7 PERIPHERALS 26

16-bit TIMERReal Time Clock

16-bit TIMERReal Time Clock

In each Interrupt Routine the OCR Register content is updated.

There is no shift time (the counter is never reset externally).

time

FREE RUNNING COUNTER VALUE

Timer IT

FFFFh

0000h

OCR

OCR+T

Timer IT

ST7 PERIPHERALS 27

16-bit TIMEROne pulse mode (1)


Generation of a pulse synchronized with an external event

Allows Phase Locked Loop Generation

On Input Capture event The counter is reset The timer output pin is toggled

On Output compare event The timer output pin is toggled The timer waits for the next Input Capture event

ST7 PERIPHERALS 28



When a external event occurs on ICAP1 pin

When the free running counter reaches

OC1R register value

Free running counter is initialized to FFFCh

OLVL2 bit level is applied on the OCMP1 pin

I CF1 bit is set


ST7 PERIPHERALS 29



FFFFh

Compare 1

OCMP1 Ouput Compare pinTimer output

0000h

FFFCh

ICAP1Input Capture pinTimer input


time

time

time

ST7 PERIPHERALS 30

16-bit TIMERPWM mode (1)16-bit TIMER

PWM mode (1)

Automatic generation of a Pulse Width Modulated signal

Period &pulse lenght set by software: The first Output Compare Register OC1R contains the length of the

pulse The second Output Compare Register OCR2 contains the period of

the pulse

Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of accuracy on the duty cycle

ST7 PERIPHERALS 31

ST7 TIMERPWM mode (2)



OC2R register value


OC1R register value

Free running counter is initialized to FFFCh


ICF1 bit is set


ST7 PERIPHERALS 32



OCMP1 Ouput Compare pinTimer output

FFFFh

Compare 1

0000h

Compare 2

FFFCh

Ttimer × 65535Tmax =

OLVL1=0

OLVL2= 1


time

time

ST7 PERIPHERALS 33

PROGRAMMING TIPS16-bit timer (1)


Define Input capture pins as inputs through the corresponding Data Direction Register

Read MSB first and then the LSB The counter LSB is buffered during the MSB read The counter LSB read accesses the buffered value Any access to the high byte disables the corresponding timer function

until the low byte is accessed Disable the interrupts during any word access

Writing the counter LSB resets the timer at FFFCh

ST7 PERIPHERALS 34



Clearing a status bit is performed by a read access to the status register followed by an access (read or write) to the low byte of the corresponding register

The alternate counter register is always matching the counter

Use the alternate counter register when you do not want to clear the Timer Overflow Flag

No interrupt is generated on compare when the PWM is active, but the ICF1 bit is set every period and can generates an interrupt

Be aware that the implicit reading performed by the emulator might clear the status flags

ST7 PERIPHERALS 35



Reset counter to FFFCh

Reset counter to FFFCh Write

CLR

ACLR

Clear TOF bit

ACLR

ReadCLR bufferedCHR

Any others Instructions

Read

ACLR bufferedACHR

Returns the CLR buffered value CLR

Clear TOF bit

Returns the ACLR buffered value

ST7 PERIPHERALS 36

Timer Configuration ExampleTimer Configuration Example

Fill the Timer registers in order to generate a real time clock at 5ms using an interrupt strategy & a timer clock at 1µs (fCPU = 8MHz).

An interrupt is generated every 5ms using Output compare1.

OCMP1 pin has to be toggled every period

What is the value to add to the TAOC1HR & TAOC1LR every period?

ICIE OCIE TOIE FOLVL2 FOLVL1 OLVL2 IEDG1 OLVL1

TACR1

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXED

TACR2

ST7 PERIPHERALS 37

Serial Peripheral InterfaceSerial Peripheral Interface

Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 PERIPHERALS 38

ST7 SPIOverviewST7 SPI

Overview

THE SPI CELL ALLOWS A FULL DUPLEX SYNCHRONOUS SERIAL COMMUNICATION BETWEEN 2 DEVICES

MAIN FEATURE : Full duplex, 3 wire synchronous transfers Master : 6 frequency available. It rates up to 2 MHz Slave mode : it rates up 4 MHz

THE CLOCK IS PROGRAMMABLE : POLARITY AND PHASE

3 DIFFERENT STATUS FLAG : Data transfer : data transfer completed Write collision : access to SPIDR during a transmission Fault flag : fault in master mode detected

ST7 PERIPHERALS 39

ST7 SPIMaster-Slave communication

ST7 SPIMaster-Slave communication

SPI Clock Generator

8-bit Shift Register 8-bit Shift Register

Master Slave

MISO

MOSI

SCK

MISO

MOSI

SCK

SS SS

5V

ST7 PERIPHERALS 40

SPISTATE

CONTROL

Read Buffer

8-Bit Shift Register

Write

Read Internal Bus

SPIE SPE SPR2-MSTR CPHA SPR0SPR1CPOL

SPIF WCOL MODFMOSI

MISO

SS

SCK

- - - - -

IT request

SERIAL CLOCK GENERATOR

MASTER CONTROLMISCR2

SPISR

SPIDR

SPIOD SSM SSI

SPICR

ST7 SPIBlock diagram

ST7 SPIBlock diagram

ST7 PERIPHERALS 41

MISO

MOSI

MOSI

MOSI MOSI MOSIMISO MISO MISOMISO

SS

SS SS SS SSSCK SCKSCKSCK

SCK

5V Po

rts

SlaveMCU

SlaveMCU

SlaveMCU

SlaveMCU

MasterMCU

ST7 SPISingle master configuration

ST7 SPISingle master configuration

ST7 PERIPHERALS 42

SPI Configuration ExampleSPI Configuration Example

Fill the SPICR register in order to configure the SPI cell in Master mode Serial clock at 5OOKHz (fCPU=8MHz) Sampling on 2nd edge High level after clock signal No interrupt generation

SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0

SPICR

ST7 PERIPHERALS 43

ST7 I2CST7 I2C

Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 PERIPHERALS 44

ST7 I2C OverviewST7 I2C Overview

The I2C cell provides all I2C bus specific sequencing, protocol, arbitration and timing in order to reduce as much as possible the software overhead

Polling Management or Interrupt Driven Cell

Main feature : Multi Master capability Interrupt generation Standard I2C mode (up to 100kHz) and Fast I2C mode (up to 400kHz) 7-bit and 10-bit addressing

ST7 PERIPHERALS 45

ST7 SCIST7 SCI

Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 PERIPHERALS 46

ST7 SCIOverview (1)

ST7 SCIOverview (1)

FULL DUPLEX, ASYNCHRONOUS COMMUNICATION

DUAL BAUD RATE GENERATOR (MAXIMUM SPEED FOR SCI TX and RX : 250kHz)

PROGRAMMABLE WORD LENGTH• 8 bits• 9 bits (8 bits of data plus parity bit)

RECEIVER WAKE FUNCTION BY THE MOST SIGNIFICANT BIT OR IDLE LINE

FcpuFtx =

[16 × PR × 2] × TRFcpu

Frx =[16 × PR × 2] × RR

ST7 PERIPHERALS 47

ST7 SCIOverview (2)

ST7 SCIOverview (2)

3 FLAGS Buffer full Transmit buffer empty End of transmission

MUTING FUNCTIONS FOR MULTIPROCESSOR CONFIGURATIONS

NOISE, OVERRUN AND FRAME ERROR DETECTION

4 INTERRUPT SOURCES WITH FLAGS

ST7 PERIPHERALS 48

ST7 SCISerial data format

ST7 SCISerial data format

Start bit Stop bit

Previous frame or idle line

Optionnal parity bit

8 bit data

LSB MSB

Following frame or idle line

ST7 PERIPHERALS 49

Bit Time

Sampling Time

SCI Sampling Data FormatSCI Sampling Data Format

Each bit time is Divided by 16 by the SCI clock Sampled 3 times on the 8th, 9th and 10th count of the SCI clock

NF flag is set if the 3 sampling are not equal but the reception is still available

Data Sampled values

Received bit value

NF Flag

000 0 0

001 0 1

010 0 1

011 1 1

100 0 1

101 1 1

110 1 1

111 1 0

ST7 PERIPHERALS 50

Transmit data register

Transmit shift register

Receive data register

Receive shift register

Transmit Control

Wake-Up Unit

ReceiveControl

Control Register 2

Status Register

SCI InterruptControl

Transmit rate Control

Receive rate Control

fcpu

/ PR/ 16/ 2Control register 1

RDI pin

TDO pin

Data Register

SCI Block DiagramSCI Block Diagram

ST7 PERIPHERALS 51

ST7 SCI Clock selectionST7 SCI Clock selection

TRANSMITTER

RECEIVER

ETPR

ERPR

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

EXTENDED PRESCALER

CLOCK

CLOCK

RECEIVER RATE

TRANSMITTER RATE

BRR

SCP1

f CPU

CONTROL

CONTROL

SCP0SCT2 SCT1 SCT0 SCR2 SCR1SCR0

/2 /PR/16

CONVENTIONAL BAUD RATE GENERATOR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED TRANSMITTER PRESCALER REGISTER

ST7 PERIPHERALS 52

SCI Configurable Baud RateSCI Configurable Baud Rate

Values given for fCPU =8MHz PR selected by SCP1& SCP0 bits of SCIBRR Register TR selected by SCT2,SCT1 & SCT0 bits of SCIBRR Register RR selected by SCR2,SCR1 & SCR0 bits of SCIBRR Register Reach the industry standard requirement

TR - SCT2:SCT0 RR - SCR2:SCR0

PR - SCP1,SCP0

ETPR /ERPR

Baud Rate

64 - 110 13 - 11 0 300

16 - 100 13 - 11 0 1200

8 - 011 13 - 11 0 2400

4 - 010 13 - 11 0 4800

2 - 001 13 - 11 0 9600

8 - 011 3 - 01 0 10400

1 - 000 13 - 11 0 19000

X X 13 38000

ST7 PERIPHERALS 53

R8 T8 M WAKE

SCICR1

TIE TCIE RIE ILIE TE RE RWU SBK

SCICR2

SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0

SCIBRR

SCI Configuration ExampleSCI Configuration Example

Fill the SCI registers in order to configure the Sci cell in 8 Bit word reception at 9600 Bauds 8 bit word transmission at 1200 Bauds Interrupt generation when RDRF is set (reception flag)

fCPU = 8MHz

ST7 PERIPHERALS 54Optional


Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 EEPROM DataST7 EEPROM Data



Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


SPGA Software Programable Gain Amplifier

SPGA Software Programable Gain Amplifier

ST7 PERIPHERALS 56

Programmable OpAmpOVERVIEW

Programmable OpAmpOVERVIEW

Integrated RAIL to RAIL OpAmp

Internal low programmable Gain (Up to 16)

Integrated reference voltage sources, VCC dependent & independent (Band-Gap).

OpAmp Outputs internally connected to ADC input

Interupt flag in comparator mode

Power on/off bit & active in low power modes

DAC capability with PWM/ART output

ST7 PERIPHERALS 57

SPGABlock Diagram

SPGABlock Diagram

OA1O

OA1NIN

OA1

R=2K

15R /16R

R

AV CL =1, 2, 4, 8, 16,

R3=2K

OA1V

AGND

OA1PIN

NS1[2:0] bits

AZ1 bit

G1[2:0] bits

VR1E, PS1[1:0] bits

VR1[2:0] bitsx V

DDA/8

OA1Interrupt

OA1IE bit

bit8-Step Reference

Voltage 1

Band GapReferenceVoltage(1.2V)

Analog (Amplifier ) or digital (Comparator) output

Reference voltages:*1.2V, Vcc independant*8 steps, VCC dependant

Programmable gain Op-Amp

SPGA1

To ADC Channel 8

ST7 PERIPHERALS 58

OA1NIN

OA1

R=2K

16R

R

AV CL =1, 2, 4, 8, 16,

R3=2K

OA1V

(1.2V)

AGND

OA1O

OA1PINTo ADC Channel 8

NS1[2:0] bits

AZ1 bit

G1[2:0] bits

VR1E, PS1[1:0] bits

VR1[2:0] bitsx V DDA /8

OA1Interrupt

OA1IE bitbit

8-Step ReferenceVoltage 1

Band GapReferenceVoltage

OA1NIN

OA1

R=2K

15R /16R

R

AV CL =1, 2, 4, 8, 16,

R3=2K

OA1V

(1.2V)

AGND

OA1O


NS1[2:0] bits

AZ1 bit

G1[2:0] bits

VR1E, PS1[1:0] bits


OA1Interrupt

OA1IE bitbit



Programmable gain Value

Inverter-1-2-3-4-8

-16

Non Inverter

23458

16

SPGA MODES (1)SPGA MODES (1)

ST7 PERIPHERALS 59

OPAMP MODES (2)OPAMP MODES (2)

OA1O

OA1NIN

OA1

R=2K

15R /16R

R

AV CL =1, 2, 4, 8, 16,

R3=2K

(1.2V)

AGND


NS1[2:0] bits

AZ1 bit

G1[2:0] bits

VR1E, PS1[1:0] bits


OA1Interrupt

OA1IE bitbit



selectablespositive input

Comparatormode

ST7 PERIPHERALS 60

SPGA MODES (3)SPGA MODES (3)

OA1NIN

OA1

R=2K

15R /16R

R

AV CL =1, 2, 4, 8, 16,

R3=2K

AGND

PWM0R / OA1PIN To ADC Channel 8

NS1[2:0] bits

AZ1 bit

G1[2:0] bits

VR1E, PS1[1:0] bits


OA1Interrupt

OA1IE bitbit


(1.2V)


8-bit PWM/ARTimer Channel 1

Channel 2

PWM0

Internal Resistor

ExternalCapacitor

Analog outputcan sink up to

40 mA

8-Bit Digital to Analog Converter



Peripheral

PORT

16-bit timer

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

PowerSupply

WatchdogTimer

Data Ram256 bytes

Oscillator

Reset

Test/Vpp

INT


Controller

8-Bit CORE

SP

PCH

AccuIndex XIndex Y

CC

Data Ram

Data EEprom

PCL


ST7 CANST7 CAN

st7 peripherals1 st7 microcontroller training 1 - introduction 2 - core 3 - adressing modes 4 -...

Documents

st7 peripherals3 st7

input io input reg

output pin

st7 software tools

analog input alternate

pin n pin

st7 hardware tools

pins input floating