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SR Flip-Flop

Waveform:

===========================================================================* Final Report *===========================================================================

Final Results :

RTL Top Level Output File Name : SR_FF.ngrTop Level Output File Name : SR_FFOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : NO

Design Statistics:

# IOs : 5

Cell Usage :

# BELS : 3# LUT2 : 3# FlipFlops/Latches : 2# FDE : 2# Clock Buffers : 1

# BUFGP : 1# IO Buffers : 4

# IBUF : 2# OBUF : 2

Device utilization summary:

Selected Device : 3s400tq144-5

Number of Slices: 2 out of 3584 0%Number of Slice Flip Flops: 2 out of 7168 0%

Number of 4 input LUTs: 3 out of 7168 0%Number of IOs: 5Number of bonded IOBs: 5 out of 97 5%IOB Flip Flops: 2Number of GCLKs: 1 out of 8 12%

Partition Resource Summary:

No Partitions were found in this design.

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RTL Schematic:

TTL Schematic:

XPower Analyzer:

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Power summary:

| I(mA) | P(mW) |Total Vccint 1.20V | 15 | 19 |Total Vccaux 2.50V | 15 | 38 |Total Vcco25 2.50V | 0 | 0 |Inputs | 0 | 0 |

Outputs |Vcco25 | 0 | 0 |Signals | 0 | 0 |Quiescent Vccint 1.20V | 15 | 19 |Quiescent Vccaux 2.50V | 15 | 38 |