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Sonar Challenge Problem Updated May 23, 2001

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Sonar Challenge Problem. Updated May 23, 2001. System Overview. Use existing MFP demo design Insert adaptive front end (MSEDR) between incoming data stream and existing matched field design it will adapt the weights used in the existing k- w beamformer - PowerPoint PPT Presentation

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Page 1: Sonar Challenge Problem

Sonar Challenge ProblemUpdated May 23, 2001

Page 2: Sonar Challenge Problem

System Overview

• Use existing MFP demo design– Insert adaptive front end (MSEDR) between

incoming data stream and existing matched field design

• it will adapt the weights used in the existing k- beamformer

– Use the PE1 and PE2 subvoxel beamformers as-is as much as possible.

Page 3: Sonar Challenge Problem

Challenge Overview

• Form covariance matrix at 3KHz rate– Requires 96GB/sec memory bandwidth !!!!!!

• Inversion of covariance matrix happens every 3-5 seconds– Don’t do inversion

• Determine K smallest eigenvalues – K << N, K ~= 10?

– Use Lanczos’ method to find eigenvalues• A subspace method which hopefully gives good

approximation to R

– Do this part on Pentium

Page 4: Sonar Challenge Problem

Forming Covariance Matrix (R)

• Forming the covariance matrix (R)– 16MB memory locations updated @ 3KHz rate

• Requires 96GB/sec memory bandwidth• SV2 has 6GB/sec memory bandwidth

– Solutions• Downsample input data• Multiple boards

– 8 SV2 boards can form R10 PE’s per SV2read/MAC/write is kernel (2 cycles)pack 2 data elements per memory locationone SV2 can do 10 X 1 kernel per cycle = 1500M

kernels/secrequirement is 4M kernels @ 3KHz rate = 12000M

kernels/sec

Page 5: Sonar Challenge Problem

Forming Covariance Matrix (continued)

• Bernecky has recently (since the Midway meeting) suggested a way of doing the R matrix computation in 50x50 chunks, and avoiding most off-chip memory accesses

• This is an interesting idea that may or may not work better than the previous slide’s approach. It will be investigated.

Page 6: Sonar Challenge Problem

Rest of Algorithm

• Normalization may be required with this algorithm– to be determined by NUWC– prior work (2 years ago) showed normalization

doubled computation required, may be the case here

• Other things may be need to be included depending on results of NUWC Matlab experiments

Page 7: Sonar Challenge Problem

Statement of 1-Year Goals

• Do a lab demonstration of AMFP system– Use recorded data at NUWC– In the absence of a full-up lab demo, have

enough of the pieces completed (sizing, design, simulation, or execution) to make a case for or against the approach.

Page 8: Sonar Challenge Problem

Demonstration Architecture

• 5 SV2 boards– 4 for creating/updating R (PE0 replacement)– 1 for subvoxel interpolation (PE1 & PE2

replacement)

• External Pentium

• Requires ACS API + Myrinet

Page 9: Sonar Challenge Problem

Tasks

• Determine whether subspace methods will work in this problem (NUWC)

• Determine time requirements for Lanczos method on a Pentium (Athanas)

• Determine effects of 2X downsampling on algorithm performance (NUWC)

• End-to-end MATLAB simulation (NUWC)

Page 10: Sonar Challenge Problem

More Tasks

• MSEDR floating point requirements– Formats, rounding modes, etc. (VTech/BYU)

• Determine communications requirements/patterns (all)

• Create single board MSEDR FPGA design (BYU)• Expand to 4 boards (VTech)• Port 4K subvoxel beamformer design to SV2

(NUWC)

Page 11: Sonar Challenge Problem

Yet More Tasks

• Integrate Lanzcos code (VTech)

• System integration/test (NUWC)

Page 12: Sonar Challenge Problem

Schedule

• Determine whether subspace methods will work in this problem (NUWC) (2 months)

• Determine time requirements for Lanczos method on a Pentium (Athanas) (2 months)

• Determine effects of 2X downsampling on algorithm performance (NUWC) (3 months)

• End-to-end MATLAB simulation (NUWC) (3 months)

Page 13: Sonar Challenge Problem

More Schedule

• MSEDR floating point requirements– Formats, rounding modes, etc. (VTech/BYU) (3 months)

• Determine communications requirements/patterns (all) (3 months)

• Virtex-II JHDL support (3 months)

• Create single board MSEDR FPGA design (BYU) (4 months)

• Expand to 4 boards (VTech) (10 months)

• Port 4K subvoxel beamformer design to SV2 (NUWC) (10 months)

Page 14: Sonar Challenge Problem

Yet More Schedule

• Integrate Lanzcos code (VTech) (11 months)

• System integration/test (VTech/NUWC) (12 months)