some irradiation results from a chip in umc018 technology peter fischer for christian kreidl...

Some Irradiation Results from a Chipin UMC018 Technology

Peter Fischer for Christian Kreidl

Heidelberg University

P. Fischer, ziti, Heidelberg

Summary

UMC018 Chip was irradiated with X-rays to 7.5Mrad No degradation after annealing Strange effects around 1.2Mrad

Work done in the frame of the DEPFET project

Measurements by Christian Kreidl Chip by Ivan Peric


DCD1 Chip

The Chip

DCD1 = DEPFET Current Digitizer Readout Chip for DEPFET Sensor columns

RegCasc

I I

ADC

RegCasc

I I

ADC

RegCasc

I I

ADC

MUX

LVDS

RegCasc

I I

ADC

LVDS

RegCasc

I I

ADCslowcotrol

bias

clk

current memory cells to subtract pedestal

DEPFET Sensor goes here…

8 bit ADCsusing current memory cells


More Details...

Generate ADC+ memory cell control signals

Clock Divider600MHz

ADC SteeringSignals

2 ADCs

Sample

ADCOutput Logic

ADC result calculation,

MUX

sync for FPGA, Switcher

Serializer

3 x 6 lines

per pixel

CurrentSubtract

RegulatedCascode

SamplingTest

Injectioncurrent

Monitoring Pad


Chip Layout & Design

UMC 0.18µm technology, 2 x MiniASIC size ADC in radhard layout (enclosed NMOS, guard rings) Digital part without any precautions 72 inputs


Pixel Layout

bump pad with60µm opening

two 8 bit algorithmic current mode ADCs working interleaved

regulated cascode

test injection

digital stuff(conservative

layout)

Size x: 180µmSize y: 110µm


Chip Test Setup

Chip glued & bonded to PCB – no cover Readout via USB


Irradiation Facility in Karlsruhe

60 keV X-Ray tube at Institut für Nuclear Physics, Karlsruhe 100-250 krad/h (depending on distance), calibrated setup Thanks to Dr. Simonis, Mr. Dierlamm and Mr. Ritter for help!


Irradiation

Dose:• 31h @99.5 krad/h (d=180mm) = 3.1 Mrad• 18h @241 krad/h (d=100mm) = 4.4 Mrad• Total = 7.5 Mrad

DCD Operation Mode• clock running permanently• control registers loaded every 30s with default values

(precaution against SEU) Measurements (while tube is on!):

• current consumption on VDD (= analog + digital)• on selected pixels:

- Current memory cell operating range- ADC characteristics- Test injection current value


0 0,61 1,01 1,41 1,81 2,21 2,60 3,00 3,70 4,67 5,63 6,600

20

40

60

80

100

120

140

160

180

200

VDD

Dose [Mrad]

I [m

A]

Current consumption

Total supply current (analog + digital) Current rises until 1.2Mrad, then settles to pre-rad value

Probably bit flipIn Bias DACs

1.2Mrad= pre-rad


Current Memory Cells

Cell keeps input voltage constant within ± 10µA


ADC Characteristic (ADC value vs. Injection DAC)

Test current injected via ON-CHIP injection DAC SEUs during measurement (more at 1.2Mrad !) most effects @<1.2Mrad, some ADCs BROKEN after 7Mrad and 6 days annealing: back to pre-rad behavior

Many SEUs

Pixel 59 Pixel 71

BROKEN @ 1.2Mrad

0 Mrad = after anneal.7 Mrad


Test Injection Current vs. DAC value

Test injection current is ok (not dead). Some variation.


ADC Histograms

Plot deviation from straight line 45nA (@0) 70nA (@1.2-7 Mrad) 44nA (7 day anneal)


ADC noise map

All ADCs back to initial values after anneal

Readout problems due

to setup

Readout problems due

to setup


Summary

No degradation after 7Mrad of 60keV X-rays Strange effects at 1.2 Mrad (power higher, ADC dead)


Thank you!


Bump Bonding Status in HD

Peter Fischer, ziti, Uni Heidelberg

for Christian Kreidl


Reminder

We do gold stud bumping:• Create a gold sphere on bonder• Place ball on chip, Thermocompress, rip off wire• Place all bumps• Flip & press & heat (~50g / bump)• Can put bumps on both sides to reduce forces• Can put isotropic glue with conducting particles

Key parameters:• Diameter of balls~ 45µm• Min. bond pad size ~ 60µm• Min pitch ~ 100µm

Advantages:• single chip (prototype) process, in house, cheap

Drawbacks:• sequential, limited # of pads, large force, possible destruction

of electronics under pad, need hard substrate, no rework


Tests with Dummy Chips

Aluminum on Silicon structures Substrate and ‘chip’ Trace pattern to check contact & shorts

SuS@Uni-Heidelberg


Chip with Bumps


Flipped Assemblies

80g/bump: all bumps connected, no shorts 20g/bump: 4 of 6 snakes connected, chip fell off


SuS@Uni-Heidelberg

Large Size Module

Mechanical demonstrator of ILC vertex detector module• no electrical tests• check how to handle a large silicon device• check how low pitch flipping works

16 DCD (dummy) chips 36 Switcher (dummy) chips 11,9 cm x 1,6 cm No electrical test possibilities

2 x 18‘Switcher’

chips

8 ‘DCD’ chips8 ‘DCD’ chips


Placing Chips Close to Each Other (side view)

Switcher (dummy) chips• 164 bumps each1• ,4mm x 5,8mm

60g/bump = 9,8kg/chip

SuS@Uni-Heidelberg

Edge offlip tool

SuS@Uni-Heidelberg


ILC Mechanical Sample

SuS

@U

ni-H

eide

lber

g


Minimum gap

SuS

@U

ni-H

eide

lber

g

50µm gap

50µm gap


Module End

224 bumps/chip, 1.35mm x 4.95mm, 13.4kg/chip

SuS

@U

ni-H

eide

lber

g

200µm gap


Full sample

One module populated with 52 chips No failures !

SuS

@U

ni-H

eide

lber

g


Effort

Bonding process: cleaning, mounting, aligning, bumping• Switcher: 11min• DCD: 13min

Flipping process: pickup, aligning, thermocompression• 9 min

2 days of work including learning

Improvements:• build better mounting device for single chip bumping

(mechanical clamp)


Thank you!


ADC Design in Heidelberg


ADC Design: Ivan Peric


Content

Algorithmic / Pipeline ADC principles Voltage vs. Current Mode

ADC in DEPFET readout chip Reminder: ADC of David Muthers (Kaiserslautern)

Comparison of figures of Merit


Algorithmic (Cyclic) ADC

Idea:• Compare signal to half scale generate BIT• If BIT = 1: subtract half scale• Multiply result by two• Restart over again

Every cycle produces a new bit

Very popular architecture Resolution limited by precision of Compare / Subtract /

Multiply

Comparator requirements are relaxed by two threshold per stage (and some error correction)


ADC Stage

P. Fischer, ziti, Heidelberg 34

ADC DAC

I in

++

-

k Bit

I out

I q

I r

Pipeline ADC

Shift value through many stages Can process one new value per cycle More hardware Faster Can scale cells for lower precision in later cells


Stage 1 Stage 2Stage

m-1

Bit Alignment + RSD Correction

2 2 2 2

Vin Stage m

Voltage vs. Current

Signal can be voltage or current Voltage:

• Often natural quantity delivered by circuit• Comparison simple• Add / Subtract & duplication with switched capacitor circuits• Large swings• Needs linear capacitors

Current• May require U->I conversion• Low swing operation• Add / Subtract very simple• Duplication with multiple current copy & add• Can do with simple, small capacitors

No obvious winner


Standard Current Memory Cell

Tracking phase: Diode connected transistor Sample on gate capacitance Drawbacks:

• Charge injection is signal dependent• Low output resistance & current dependent• Input potential current dependent• Large storage cap (low leak) decreases speed


Iin / Iout

Pixel Layout


Two 8 Bit ADCs:Current memory cells,Comparators,Reference sources.

Optimized, rad hard layout

ADC timing signals(can be shared)

2 x Output Logic(shift registers…)

Very conservative layoutUsing standard cells

110

µm

ADC Characteristic


8 Bit ADC output vs. injection DAC value

ADC Noise / INL

Plot deviation from ideal value for various inputs Width mostly from noise in input stage


Pipeline ADC (Design Study)


Comparison: ADC from D. Muthers, Kaiserslautern

Voltage mode Cyclic & Pipeline version Early version used in TRAP chip


Comparison


FoM = P / 2ENoB / f * 1012 (small is good) ADC from HD are VERY small

HD, I modeCyclic

HD, I mode Pipeline

KL, V modeCyclic

KL, V mode Pipeline

CommercialIQ-Analog

ENOBs ~ 8 (9) ~ 9 (design) ~ 9.2 @ fin=5MHz

~ 9.7 9

speed 6 MS/s 25 MS/s 10 MS/s 75 MS/s 80 MS/s

Power 1 mW 4.5 mW 9.5 mW 30 mW 8 mW

Layout area

~3.000 µm2

(rad hard)~10.000 µm2

(rad hard)110.000 µm2

(non rad hard)> 200.000 µm2

(non rad hard)210.000 µm2

(0.13µm)

Additionally Shift register

Delay registers

??? ??? -

FoM [pJ/conv]

0.65 0.35 1.6 0.48 0.2

Thank you!


Simple Serial Data Driver



Goal

Study a serial driver suited to directly drive an FPGA Find out how

• Complex• Large• Power hungry

it is.

Later: study copper transmission:• how long can we go ?• How fast can we go ?• For which type of cable ?• for which power requirement ?


Design choices

Use (free) Aurora protocol from Xilinx No back channel No channel bonding

Minimize protocol engine Use radiation hard library for a test


Aurora – Protocol

Physical layer interface – electrical levels, clock encoding, symbol coding

Channel initialization and error handling Link layer:

• Beginning / End of data• IDLE• Clock compensation• 8B/10B encoding

Arbitrary data format, Data packets with arbitrary length 4 Phases:

• Initialization• Synchronization of receiver clock (send some syncs)• Data transmission• Idle

Must inject clock compensation characters from time to time


Components

FIFO: (data buffer) Control FSM 8b/10b Encoder Serializer LVDS-Driver


Initialisation


RESET TXRES_0

TXRES_1zur Validierung

ln_c

nt

< N

+2

res_cnt < 3

Validation


VAL/A/ VAL/R/

VAL/K/

CV_1CV_0

idle_cnt = 32

idle_cnt < 32

IDLE / Daten

idle_cnt = 32

val_

cnt

= 6

0

val_cnt = 60

val_

cnt =

60

von Initialisierung

Idle


IDLE/A/

IDLE/K/

CC_1

IDLE/R/

valid_data & even

valid_data & evenvalid_data & even

von Daten / Valid.

Daten

ccc_cnt = 10000

idle_cnt = 32

idle_cnt = 32

idle_cnt < 32

ccc_

cnt

= 1

0000

ccc_cnt = 10000

ev_cnt < 12

Data Transfer


SCP_0

CC_5_0

CC_5_1

PADDING

CC_4

SCP_1

CC_2_0 CC_2_1

CC_3

DATA

ECP_0ECP_1

!val

id_d

ata

!val

id_d

ata

& eve

n

valid_data

valid_data !valid_data & !even

von

IDL

E /

Val

.

Daten

!valid_dataIDLE

Serializer


For simplicity: Realize in CMOS Use shift register with load Load generation most time critical Several circuits have been compared Minimal speed: 600 MHz Reached 1.9GHz with standard cells

Test circuit on Xilinx Evaluation board

Generate Aurora compatible parallel data stream Send to MGT serializer Loopback via SATA cable Receiver uses Aurora protocol


FSM, 8b/10b

Sample result: data transfer and Idle


Synthesis with VST library


First Using VST library

Simplification


59

Try designs with NO clock compensation characters

Synthesis with Rad hard library


60

Power estimation

No LVDS driver (which will dominate!) Using VST Library Rad hard ~ x4


61

Place & Route


~200 x 200mm2 for rad had design

Next steps

Study realistic, fast LVDS driver Study cable properties & modelling First step: Simulated eye-diagram with Kaiserslautern

driver+ 10 cable, 24AWG (no pre-emphasis)


Thank you!


some irradiation results from a chip in umc018 technology peter fischer for christian kreidl...

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heidelbergsummaryumc018

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