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Solving the Information Technology Energy Challenge Beyond Moore’s Law 2x transistor/2yrs at same power & cost Started slowing ~2007

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Page 1: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Solving the Information Technology Energy Challenge Beyond Moore’s Law

2x transistor/2yrs at same power & cost Started slowing ~2007

Page 2: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

0

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TWH

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Year www.alliancetrustinvestments.com/sri-hub/posts/Energy-efficient-data-centres www.iea.org/publications/freepublications/publication/gigawatts2009.pdf

Projection based on consumer electronics + data centers

The problem: IT projected to challenge future electricity supply

~40% of 2014 world electricity

Page 3: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

0

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4000

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2000 2005 2010 2015 2020 2025 2030

TWH

r

Year www.alliancetrustinvestments.com/sri-hub/posts/Energy-efficient-data-centres www.iea.org/publications/freepublications/publication/gigawatts2009.pdf

Projection based on consumer electronics + data centers

The problem: IT projected to challenge future electricity supply

Even worse if Moore’s Law ends!!!

Page 4: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Photonic

ICs

More efficient architecture in first

10 years

Need more efficient materials/devices for

next 10-20+ years

The path: near and long term

Revolutionary Heterogeneous HPC

architectures & software

Page 5: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Industry Academia

SRC

DARPA

NSF IARPA

Complex Landscape

DOE/National Labs • Support • Collaborate • Partnerships • Early Adoption

Page 6: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

The Opportunity Fundamental

Science • Move revolutionary

low energy devices and architectures from Lab to Fab

• Accelerate

development and manufacturing base for semiconductor devices

• Create public-private partnerships with electronics industry

• Advanced computing

• Multiscale computing benchmarking and modeling

• Next-generation heterogeneous architectures

• New programming

models and application software

• Leverage unique capabilities in material science

• Scientific user facilities

• Computational approaches to materials design

• Grand challenges driven research

Computing Science

Manufacturing Science

Page 7: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Multiscale Multi-Lab Effort

MESAFab

APS

+++

+-

--

--

-

++

VTE

+

++

+

+

--

+

++

++

+

+

--

--

-

PtTaOxTa

On Chip Universal Memory:

Stacked ReRAM

Petabit cm-2

Densities

Replaces DRAM & flash

<1 pJ per write/read

Silicon

On Chip Memristor Accelerator:

Vector or matrix operations

fJs per operationOn Chip Photonics

Chip to chip communication

<1 pJ per bit transfer

High Performance Logic:

TFET, NcgFET

To next

node

x2

x2

x2

x2

w1,1

w2,1

w3,1

w4,1

w1,2

w2,2

w3,2

w4,2

w2,x

w2,x

w3,x

w4,x

...

...

...

...

Mu

ltis

cale

Ev

alu

atio

n

Fra

me

wo

rk

Page 8: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Advanced Materials

Page 9: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Advanced Devices and Manufacturing

Page 10: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Architecture & Algorithms

Page 11: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Multi-Lab Engagement

(F.B.) Rick McCormick Bruce Hendrickson

Dave Sandison Rob Leland

Ramamoorthy Ramesh Patrick Naulleau

John Shalf Horst Simon

Supratik Guha Rick Stevens

Lou Terminello Nathan Baker Malin Young

Trish Damkroger

Gary Grider John Sarrao Toni Taylor

Jeff Nichols

Page 12: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

Building the Public-Private Partnership

Page 13: Solving the Information Technology Energy Challenge Beyond ...cxro.lbl.gov/PDF/DOE_and_meeting_the_future_IT_energy_challenge.pdfx Petabit cm-2 Densities x Replaces DRAM & flash x

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SUMMARY

100’s fewer power plants

• Looming end of Moore’s Law creating rapidly growing energy gap

• Coordinated public-private partnership will drive breakthroughs by leveraging multiple DOE Office leadership and Lab capabilities

These breakthroughs will enable continued affordability of our information economy, saving construction of 100’s of power plants


Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

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Memoria dram

Gather-Scatter DRAM: In-DRAM Address ranslationT …people.inf.ethz.ch/omutlu/pub/GSDRAM-gather-scatter-dram...Gather-Scatter DRAM: In-DRAM Address ranslationT to Improve the Spatial

A Concept: Transmitting and Receiving Fiber Optic Signals with Petabit per Second Capacity

memoria Dram

Solar-DRAM: Reducing DRAM Access Latency by Exploiting …...reads to DRAM cache lines containing “weak” or “strong” cells, and 2) writes to all of DRAM. We evaluate Solar-DRAM

etrij.etri.re.kr · rule -x SRAM 04K SRAM DRAM a 0 16K SRAM 64K DRAM oa 256K DRAM 64K SRAM 1M DRAM 256K SRAM 4M DRAM SRAM 88 16M DRAM SRAM 10 10 10 10 10 0.8 0.6 70 4K DRAM 72 01K

High Speed DRAM Interface - Hanyangiclab.hanyang.ac.kr/research/data/High-speed DRAM interface.pdf · High Speed DRAM Interface Changsik Yoo DRAM Design 3 Samsung Electronics. [email protected]@ieee.org

Scalable Many-Core Memory Systems Topic 1: DRAM Basics …users.ece.cmu.edu/~omutlu/pub/onur-ACACES2013-Topic1-dram-basic… · Solution 1: Tolerate DRAM ! Overcome DRAM shortcomings

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32M x 16 bit DDR2 Synchronous DRAM (SDRAM)

Petabit Switch Fabric Design

Scalable Many-Core Memory Systems Lecture 1, Topic 1: DRAM ...users.ece.cmu.edu/.../onur-ACACES2013-Lecture1-dram... · Solution 1: Tolerate DRAM ! Overcome DRAM shortcomings with

ettrends.etri.re.kr · rule -x SRAM 04K SRAM DRAM a 0 16K SRAM 64K DRAM oa 256K DRAM 64K SRAM 1M DRAM 256K SRAM 4M DRAM SRAM 88 16M DRAM SRAM 10 10 10 10 10 0.8 0.6 70 4K DRAM 72

Adaptive-Latency DRAM: Optimizing DRAM Timing …users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf · Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common

Petabit Switch Fabric Design - EECS at UC Berkeley · PDF fileThe ultimate goal of our project Petabit-Switch Fabric design ... building the test harness around a single router. My

1M x 16Bits x 2Banks Low Power Synchronous DRAM · Rev. A | November 2015 - [email protected] 1 IS42/45SM/RM/VM16200D 1M x 16Bits x 2Banks Low Power Synchronous DRAM Description These

4M x 32Bits x 4Banks Mobile Synchronous DRAM

16Mega x 16 Synchronous DRAM (SDRAM)

1M x 16 bit Synchronous DRAM (SDRAM) · 1M x 16 bit Synchronous DRAM (SDRAM) Alliance Confidential Features • Fast access time: 5.4ns • Fast clock rate: 143 MHz • Self refresh

512M x 8 bit DDR4 Synchronous DRAM (SDRAM) · 2019-10-14 · 512M x 8 bit DDR4 Synchronous DRAM (SDRAM) ... mode S R X * Self Refresh CKE_L CKE_L Bank Active Precharge Power Down

128M - 8M x 16 bit Synchronous DRAM (SDRAM) … · 128M - 8M x 16 bit Synchronous DRAM (SDRAM) ... Operation Mode ... Mode Register Set Idle H X X OP code L L L L

Petastar: a petabit photonic packet switch - Selected Areas in

VRL-DRAM: Improving DRAM Performance via Variable Refresh ... · VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency Anup Das Drexel University Philadelphia, PA, USA

Fine-Grained DRAM: Energy-Efficient DRAM for Extreme ...niladrish.org/pubs/micro17.pdf · Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems Mike O’Connor∗†‡

32Mega x 16 Synchronous DRAM (SDRAM)

Bridging the Disconnect - acm sigcommconferences.sigcomm.org/sigcomm/2003/workshop/...23.888 Petabit-meters per second* 0.270 Petabit-meters per second 0.007 Petabit-meters per second

Co-Architecting Controllers and DRAM to Enhance DRAM ...camelab.org/uploads/Main/Co-Architecting Controllers and DRAM to... · Co-Architecting Controllers and DRAM to Enhance DRAM

Morning Meeting Notes · 1분기 DRAM 고정가격 하락과 아이폰 생산 수요 감소는 예견된 악재 DRAM Exchange는 1분기 DRAM 고정 가격을 QoQ로 PC DRAM -20%,

64M x 4 bit Synchronous DRAM (SDRAM) fileRevision History 256M AS4C64M4SA 54-pin TSOPII PACKAGE

DDR3 Synchronous DRAM Memory - … · DDR3 Synchronous DRAM Memory ... Read/Write leveling . DDR3 Synchronous DRAM 3 8-bit prefetch/burst length . DDR3 Synchronous DRAM 4 Commands

Memory Scaling : A Systems Architecture PerspectiveSolution 1: Tolerate DRAM ! Overcome DRAM shortcomings with " System-DRAM co-design " Novel DRAM architectures, interface, functions

32M x 16 bit DDR2 Synchronous DRAM (SDRAM) · 32M x 16 bit DDR2 Synchronous DRAM (SDRAM) Advanced (Rev. 1.5, Mar. /2016) Features •JEDEC Standard Compliant •JEDEC standard 1.8V