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University of Toronto Faculty of Applied Science and Engineering

ECE 334F – Digital Electronics

Fall 2013

Midterm Exam #1

Examiners: K. Phang and P.G. Gulak

Duration: 60 minutes Closed book; An original 8.5”x11”one-page aid-sheet is allowed (with writing on front and back allowed). Only answers written in pen will be considered for a re-mark. Unless otherwise stated in the problem, assume the CMOS parameters provided on the last sheet. Only silent, non-communicating, non-programmable calculators are permitted. Turn all cell phones off. Cell phones are not permitted as watches or calculators. Only the last sheet (parameter sheet) is allowed to be removed from the test book. Answer all questions in the space provided. No additional exam sheets for answers are permitted. Attempt all questions, since a blank answer will certainly get a mark of 0. Write clearly. It is not the marker’s job to decipher your answers through pages of scribble. Marks assigned to each question are indicated inside [ ]. Write your name and student number in the space below. Do the same on the top of each sheet of this exam book.

Name: ___________________________________ (Underline last name) Student Number: ___________________________________

Lecture section (circle one) LEC101-Gulak LEC102-Phang

Q1 [ /10] Q2 [ /5] Q3 [ /10] Q4 [ /10] Total [ /35]

Solutions

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Question 1. [10 marks]. Combinational Logic, layout to Schematic to Boolean Equation

a) [8 marks] Draw a neatly organized and labeled CMOS transistor schematic diagram that represents the circuit realized in the layout below. Assume the necessary n-well and substrate contacts exist but are not explicitly shown.

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Question 3. [10 marks]. MOSFET Capacitance.

For the terminal voltages shown below, determine the region of operation and calculate all the capacitances for the NMOS transistor based on the layout view and the capacitance parameters provided on the last page. Show your final answer by marking all the capacitances and their calculated values directly on the schematic symbol.

Region of Operation: NMOS in TRIODE because VGS=1.8V > Vtn=0.4V and VGD=1V > Vtn or equivalently VDS=0.8V < VGS-Vtn=1.4V

MOSFET Physical Dimensions !!= 0.09µm for 0.180µm CMOS W = 6!! % = 0.54 µm L = 2!! % = 0.18 µm

Source: AS = (6!!)(7!!) = 0.3402 µm2 PS = 2(6!! + 7!!) = 2.34 µm

Drain: AD = (6•6+4•9)!!^2 = 0.5832 µm2 PD = (6+15+4+9+2+6)!! = 3.78 µm

GATE CAPACITANCE

In the TRIODE region, Cgs = Cgd = 1/2•Co and Cgb = 0 fF

Co = Cox•WL = (8.5fF/µm2)(2!!)(6!!) = 0.8262 fFso Cgs(intrinsic) = Co/2 = 0.4131 fF

Adding the overlap capacitance, Cgs(overlap) = Cgsol•W = 0.1620 fF

gives Cgs = Cgs(intrinsic) + Cgs(overlap) = 0.575fF

Thus Cgs = Cgd = 0.575fF and Cgb = 0fF

At the drain, Vdb = 0.8V soCjbd = CJ•[1 + Vdb/ѱ0]

-MJ

= (0.9)[1+0.8/0.8]-0.4

= 0.6821 fF/µm2

Cjbdsw = CJSW•[1 + Vdb/ѱSW]-MJSW

= (0.3)[1+0.8/0.8]-0.1 = 0.2799 fF/µm

Cdb = AD•Cjbd + PD•Cjbdsw = (0.5832)(0.6821)+(3.78)(0.2799) = 1.456fF

DIFFUSION CAPACITANCE

At the source, Vsb = 0V (zero bias)

Cjbs = CJ = 0.9 fF/µm2

Cjbssw

= CJSW = 0.3 fF/µm

Csb = AS•Cjbs + PS•Cjbssw = (0.3402)(0.9)+(2.34)(0.3) = 1.008fF

Cgd=0.575fF

Cgs=0.575fF Csb=1.008fF

Cdb=1.456fF

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Question 4. [10 marks]. Elmore delay. For the 4-input NAND gate shown below, a) [2 marks] Describe briefly the input conditions that result in the worst-case pull-down delay.

b) [8 marks] Apply the Elmore delay concept to estimate the worst-case pull-down delay, tpdf. Draw and clearly label the equivalent circuit that you use to calculate this Elmore delay. Assume the aspect ratio, W/L, is 8!/2! for all the PMOS transistors and 16!/2! for all NMOS transistors, and use the process parameters on the last page. The capacitors shown represent the total parasitic capacitance at each node and their values are COUT = 10fF, and CW = CX = CY = 2fF.

!

Answer: tpdf =

a) Worst-case pull-down delay occurs when all capacitors are charged to VDD and then discharged when all the inputs go HIGH

So W=X=Y=1 & Z=0 transitions to all HIGH

b)

Equivalent resistance for NMOSR = 2.5/[µnCOX(W/L)(VDD-Vtn)] = 2.5/[(0.17)(16/2)(1.8-0.4)] = 1.313kΩ

Elmore delay:

tpdf = CyR + Cx•2R + Cw•3R + Cout•4R = (6•2fF + 4•10fF)•1.313kΩ = 68.3 psec

68.3 psec

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Parameter Sheet

Physical Constants:

0.18µm CMOS Process parameters: ! NMOS! PMOS! Units! Description!!!!! 1.8!! 1.8!! V! Supply!voltage!!!"#! 180! 180! nm! Minimum!channel!length!(equal!to!!")!!! 0.4! <0.4! V! Threshold!voltage!with!zero!bulk<source!voltage!!!,!!!"! 170! 50! µA/V2! Transistor!current!gain!parameter!!! 0.6! 0.6! V1/2! Body!effect!coefficient!!!!! 0.93! 0.93! V! Surface!potential!!! ! ! ! ! Capacitance parameters:

COX 8.5 !" !"!! Gate capacitance per unit area Cgol 0.3 !" !"! Gate overlap capacitance per unit width CJ 0.9 !" !"!! Drain/source bulk junction capacitance per unit area

CJSW, CJSWG 0.3 !" !"! Drain/source sidewall junction capacitance per unit perimeter (including under the gate)

!!,!!",!!"# 0.8 V Built-in potential of diffusion junction !! 0.4 Junction grading coefficient !!"#,!!"#$ 0.1 Sidewall junction grading coefficient

Commonly used prefixes for Units

Giga G 109 Mega M 106 kilo k 103 milli m 10-3 micro µ 10-6 nano n 10-9 pico p 10-12 femto f 10-15