soi value in ibm silicon technology · 10/19/2011 · ibm pd-soi is delivering industry-leading...

© 2011 IBM Corporation IBM Microelectronics SOI Value

SOI Value in IBM Silicon Technology

19 October 2011

William Clark, Senior Technical Staff,

Technology Strategy &

Ed Nowak, Distinguished Engineer,

Device Chief Designer

IBM Microelectronics

© 2011 IBM Corporation IBM Microelectronics 19 October 2011 2 SOI Value

IBM SOI Benefits Overview

IBM PD-SOI is delivering Industry-Leading Power/Performance

– Performance >20% above demonstrated Industry-Standard Foundry

– Power reduction of 10% to 50%, depending on VDD-min limitations

UTBB-SOI Provides Low-Power Value for 20nm and following nodes

– Enables scaled gate length for density

– Unique scalable back-gated FETs for dynamic Vt control

• Provides dynamic speed boost

• Provides dynamic leakage leakage/power reduction

– Simplest migration path from Bulk CMOS Designs

3D / FinFET Architecture on SOI

– Full Power Spectrum – lowest leakage floor design (no doping isolation)

– Lower Vmin (reduced variability)

– Superior SEU/SER/Latch-up performance

– Ultimate gate-length/VDD scalability beyond 14nm node.


Partially Depleted-SOI


IBM PDSOI Leadership

PDSOI is delivering Industry-Leading Power/Performance

– Performance Leading Best-of-Breed CMOS

– Performance >20% above demonstrated Industry-Standard Foundry

– Power reduction of 10% to 50%, depending on VDD-min limitations

PDSOI Features

– Integration of eDRAM enables Key product leverage

• Better than 3X Memory density of Bulk SRAM

• Less 1/3 Power of Bulk SRAM

• Enables Ultra-Low Soft-Error rate.

IBM SOI Technology Leadership Path + Features

Enable World-Class CMOS Solutions


SOI: Deep Trench (DT) Capacitor Advantages

SRAM Power Reduction

Industry’s first user-transparent leakage reduction system

40% leakage reduction even under 100% memory activity

SOI DTcap

eDRAM Cell

1.66ns random-cycle time (32nm)

41ms retention time

10X lower standby power than SRAM

2 FIT/Mb SER

3X more capacitance than MiMcap

Decoupling capacitor

Power supply noise critical on 400+ MHz design

>20X more decoupling per unit area than Planar capacitor

>1,000X lower leakage per unit area than Planar capacitor

Step Response

Steady-State AC Response

VDD

Glo

bal

1st Stage Sense Amp

DIO DIO2nd Stage Sense

128 X 128

CONTROL

Deco

de

VCS Grid

Deep Trench Decoupling Capacitors

Glo

bal

1st Stage Sense Amp

DIO DIO2nd Stage Sense

128 X 128

CONTROL

Deco

de

VCS Grid

Deep Trench Decoupling Capacitors


eDRAM SOI Integration

SOI Buried Oxide provides

ideal isolation for DRAM

trench capacitor

Charge Storage electrode

SOI Transistor Body (transfer gate)

SOI BOX provides Isolation

Of Trench Cap. From Transfer Gate


Integrated Embedded Memory Solutions

Memory is 50-70% of the die

Memory key to optimizing performance

High Performance eDRAM delivers 3X

more memory at same die size & power

– 3X density benefit vs SRAM

– > 5X standby power benefit

– > 1000X SER benefit

Cell Size (m m2)

Pe

rfo

rm

an

ce

(A

U)

Le

ak

ag

e (

nA

)

0

20

40

60

80

100

00.10.20.30.40.5

0.001

0.01

0.1

1

10

100

SRAMs

Low

leakage

eDRAM

Cell Size (m m2)Cell Size (m m2)

Pe

rfo

rm

an

ce

(A

U)

Le

ak

ag

e (

nA

)

0

20

40

60

80

100

00.10.20.30.40.5

0.001

0.01

0.1

1

10

100

SRAMs

Low

leakage

eDRAM

Power 7 Process Chip

– Eight processor cores

– 32MB on-chip eDRAM shared L3 Cache (0.067 µm2 cell size)

– Equivalent function of 2.7B transistors due to eDRAM efficiency


Integrated Embedded Memory Solutions: Watson meets Jeopardy!

Competitors get an early look at the revolution in computing systems Beats two human competitors on the popular U.S. quiz show "Jeopardy!" in a three-day showdown

that ended on Wednesday

Total scores over two days of play was $77,147 for Watson, $21,600 for Rutter and $24,000 for Jennings.

What’s in Watson?

Watson is powered by 10 racks of IBM POWER 750 systems

Watson runs the Linux operating system

Watson contains 15 terabytes of RAM and 2,880 processor cores

Processor Based on 45 nm SOI Technology with embedded DRAM (eDRAM) memory

Watson can operate at 80 teraflops per second – 80 trillion operations per second

IBM, Nuance to Tune Watson for Use in Health Care & Other Applications


PDSOI Die Leakage vs RO Delay SOI Production part leakage below target

Superior Isolation enables reduced Intra-Die Variation

– Lowers leakage floor

– Enables Lower Vdd operation (Vmin)

Results in Lower Power Chip

Technology ready for production parts a full year ahead of competition

Consistently below target leakage across full-range of operating temperature

Technology Prediction

In-Product Ring Oscillator Delay (ps)

To

tal C

hip

Leakag

e (

a.u

.)


PDSOI Scalablilty: CMOS Circuit Delay

32nm PDSOI 28% faster than 45nm PDSOI

1.E-08

1.E-07

1.E-06

6.0 8.0 10.0 12.0 14.0 16.0

S02 Ring Stage Delay [ps]

S02

Rin

g Io

ff s

um

[A

/um

]

12S0

13S alpha0SLVT

LVT

RVT

HVT

SHVT

28%

FO3 Inverter

Leakage vs. Delay

Invert Delay (ps)

Invert

er

sta

ge l

eakag

e (

A/u

m)

Inverter Delay

Sta

ge L

eakage


Ultra-Thin Body/BOX SOI


UTBB for Low Power CMOS 20nm and Beyond

Ultra-Thin Body/BOX SOI for Low-Power applications

– Body thickness sub 8nm scale suppresses deleterious short-channel effects

– Buried Oxide thickness sub 300nm scale enables VT modulation via voltage to buried wells

UTBB delivers uniquely scalable power-agile features

– Low Vt and low leakage due to superior electrostatics of thin body

On-the-fly Vt adjustment via substrate-well back gate bias

– ‘Back’ bias for Circuit Leakage reduction in standby,

– ‘Forward’ bias for Circuit Delay reduction when active.

K.Cheng, VLSI 2011

Sub

STI

n n p p

N-GP (PW) P-GP(NW)

Well in bulk substrate provide

back-gates for active MOSFETs


Ultra-Thin Body and BOX SOI

Bulk CMOS Limitations in these areas include

– Well bias has limited, small effect on VT

• Range of leakage suppression from reverse bias is very small compared to UTBB

• Scaling continues to reduce the size of this effect in Bulk CMOS

• UTBB VT modulation is large and scalable

• Not limited by doping/junction profiles which degrade Bulk scalability

– Well bias in forward direction is limited due to forward-biased junction leakage from body to source

• Wells in UTTB are not limited by this effect and can be employed to boost circuit speed when required.

Very low VDD operation in SRAM Bit-Cell

Well bias varied from 0 to -2V to demonstrate Cell operation at 0.4V 0.0 0.1 0.2 0.3 0.4 0.5

0.0

0.1

0.2

0.3

0.4

0.5

VR(V

)

VL(V)

Vbb

=0V

Vbb

=-0.5V

Vbb

=-1V

Vbb

=-1.5V

Vbb

=-2V

Vdd

=0.4V


3D Transistors / FinFETs on SOI


Overview of 3D / FinFET Architecture

Double-Gate MOSFET Enables Scaling

Planar approach to DGCMOS

impractical for manufacturing

3D FinFET Structure provides solution

to manufacturing challenge


Why Double-Gate CMOS?

Near-ideal sub-threshold swing

No voltage divider action with substrate

Lower threshold for same leakage

Scale to smallest LPOLY for a given TOX and TSi

Source shielded from drain by two gates

Net is improved density, performance, power.

T INV

L

S D

Gate

Gate Substrate

T INV L

S D

Gate

T INV

X D

Bulk, PDSOI, UTTB-SOI Double-Gate FET


FinFET Cartoon

Cross-section parallel to fin Cross-section perpendicular to fin

Fin

Gate

current flow

source

drain

Tfin = 40nmW contact

Lgate = 140nm

BOXBOX

LGATE

WEFF ~ 2.5 H


SOI Value in 3D / FinFET CMOS Architecture

Vertical Channel FinFET Overview

Bulk-based FinFET Challenges

– Vertical Registration Variability

– Doping-Gradient-Losses

– Freedom from Random-Dopant-Fluctuation-Induced Isolation losses

SOI FinFET Solution:

– Triple-Vertical-Self-Alignment

– Simple Process Integration

– Freedom from Isolation

0

0.2

0.4

0.6

0.8

0 0.2 0.4 0.6 0.8

V in (V)

Vo

ut (

V) 0

50

100

150

200

250

0.4 0.6 0.8V dd (V)

SN

M (

mV

)


SOI FinFET Power/Performance Span

SOI enables wide VT menu to support broad span of product applications

–Minimize product leakage for given path-delay objective

–Can Span from low stand-by power (100pA/um) to high speed (150nA/um)

–Leakage Floor not limited by Junction-Leakage/GIDL from Punch-through stop


buried oxide

SOI-Bulk FINFET Design Compatibility is Very High

PDSOI presented several obstacles for Bulk CMOS design migration

– Floating Body necessitated change to (logic) timing tools to account for history effect.

– MOSFETs required special body-contact physical designs when used in matching-sensitive

applications

– Self-heating simulation for high-duty-factor circuits (e.g. clock buffers).

– SRAM bit-cell stability required worst-case-history simulations (and test).

Designs can be Bulk-SOI Fin compatible

– FinFET bodies are fully depleted of free majority carriers.

• History effect is nearly zero (immeasurable)

– Self-heating exists in both, though somewhat larger in SOI version

• Need self-heating simulation for high-duty-factor circuits in both


Well-Isolated FinFET Engineering Overview

Device Design Fundamentals

– Vertical Registration

• Gate-electrode to Channel-Stop to Source/drain edge

– Doping gradients

• Source/Drain junction abruptness at bottom of FET

– Degraded Rext (roll-off in doping/overlap at bottom of channel)

• Channel Stop/Well at bottom of channel

– Degraded Sub-threshold swing (gradient in suface potential from to bottom of fin)

– Stochastic Dopant Fluctuation in channel-stop Space-Charge Region

• Delta-W mismatch up to ~ 2 x ( YSD – YCS) or ~ 2 x (YGE-YCS) possible

• If achieve registrations ~ of 10% of YCS, would result in ~ 4% random mismatch

Isolation Requirements

– Deep Trench of Intra-Well isolation/Latch-up immunity

– Well contacts

sourc

e gate

Channel-stop Doping

channel

YCS

YSDYGEs

ourc

e gate

Channel-stop Doping

channel

YCS

YSDYGE


Bulk FinFET Isolation Challenges

TCAD Illustration – Gate electrode not shown for clarity

nMOS pMOS

drain diffusion

gradient

drain

Punch-through stop

Bulk substrate

Channel: PTS diffusion gradient

Gate ‘lifted’ to reveal silicon profiles

Punch-through

Non-uniform Vt

Junction Leakage

GIDL


SOI FinFET Solution

SOI Substrate provide Triple-self Aligned FinFET Structure

– Gate-Channel-Junction all stop abruptly at Silicon/Box boundary

Avoids

– Doping-related Junction and GIDL leakages for Low-Power space

– Punch-through related leakages for High-Speed Space

– Parasitic gate-drain capacitances from junction realistic gradients

– Parasitic gate-drain capacitances from vertical registration variance

– Drive/Leakage Loss from punch-through stop gradient in channel

– SRAM Random drive mismatch from punch-through stop Random Dopant Fluctuations

Silicon fin (from SOI layer)

Buried SiO2 (BOX layer)

Silicon substrate of SOI wafer

YSD YCS

YGE

SOI: YSD = YGE = YCS


Circuit Speed vs. Leakage

1. YGE > YSD > YCS

2. YSD > YGE > YCS 3. YGE > YCS > YSD

4. YSD > YCS > YGE

6. YCS > YGE > YSD

5. YCS > YSD > YGE

Leakage (sub-threshold, junction, GIDL)

Speed

SOI: YSD = YGE = YCS


Process Simplicity: Sketch of flows

SOI FinFET

1. Deposit Pad films on

incoming SOI wafer

Bulk FinFET

2. Pattern/etch fins, stop on BOX

3. Deposit and etch dummy gate stack

4. Device Build follows.

9. Deposit and etch dummy gate stack

10. Device Build follows.

1. Deposit Pad films on

incoming bulk wafer


Overall Comparison: Bulk vs. SOI FinFET CMOS

Current front-up flow has common

EG module for SOI and Bulk.

I/O integration

complexity

Degradation due to PTS and potentially higher

well doping in Bulk; impact on Vmin

SRAM Vt MM

Additional variation in bulk FIN

due to alignment challenge

between RMG gate stack and ext,

s/d junction

Defined by FIN height (SOI)

and FIN width (TTM advantage)

More Fin-height variations due to 1 ) Fin etch

depth, 2) STI fill/CMP/recess

Fin height uniformity -

> Weff variation

Dielectric isolation (TTM

advantage)

Junction isolationIsolation

GIDL is more a concern for nFET.Concern about jct lkg and GIDL due to PTSLow-lkg device

(SHVT) feasibility

(<100pA)

Additional benefit from eSiGe,

eSiC in bulk is limited due to

tradeoff in Cj and stress response.

Early IBM assessment shows

5~7% better performance than

bulk.

Further TCAD ongoing

Pros:

- Slightly better embedded stressor benefits

due to additional recess into substrate

Cons: Punch-Thru Stop (PTS) I/I causes

- degradation in Cj/Ij

- increase in Cgc for matched SCE

- higher variability

Performance &

Variability

Similar multi-Vt strategy between

SOI and Bulk

Multi-Vt

Requires either (a) epi growth in

passive area or (b) recess in

logic area.

Generally more flexible due to Si substratePassive integration

complexity

Substrate cost delta is largely

offset by process cost delta

Higher substrate cost

Lower process cost

Lower substrate cost

Higher process cost (FIN formation & isolation)

Cost

CommentsSOI SubstrateBulk substrate

Current front-up flow has common

EG module for SOI and Bulk.

I/O integration

complexity

Degradation due to PTS and potentially higher

well doping in Bulk; impact on Vmin

SRAM Vt MM

Additional variation in bulk FIN

due to alignment challenge

between RMG gate stack and ext,

s/d junction

Defined by FIN height (SOI)

and FIN width (TTM advantage)

More Fin-height variations due to 1 ) Fin etch

depth, 2) STI fill/CMP/recess

Fin height uniformity -

> Weff variation

Dielectric isolation (TTM

advantage)

Junction isolationIsolation

GIDL is more a concern for nFET.Concern about jct lkg and GIDL due to PTSLow-lkg device

(SHVT) feasibility

(<100pA)

Additional benefit from eSiGe,

eSiC in bulk is limited due to

tradeoff in Cj and stress response.

Early IBM assessment shows

5~7% better performance than

bulk.

Further TCAD ongoing

Pros:

- Slightly better embedded stressor benefits

due to additional recess into substrate

Cons: Punch-Thru Stop (PTS) I/I causes

- degradation in Cj/Ij

- increase in Cgc for matched SCE

- higher variability

Performance &

Variability

Similar multi-Vt strategy between

SOI and Bulk

Multi-Vt

Requires either (a) epi growth in

passive area or (b) recess in

logic area.

Generally more flexible due to Si substratePassive integration

complexity

Substrate cost delta is largely

offset by process cost delta

Higher substrate cost

Lower process cost

Lower substrate cost

Higher process cost (FIN formation & isolation)

Cost

CommentsSOI SubstrateBulk substrate


Summary of SOI 3D/FinFET Advantage

Well-isolated FinFETs suffer fundamental problems

– Time to market adder 3-5 Quarters to Manufacturing Ready

– Increased Turn-around-Time vs. SOI

– Challenge for ultra-low-power designs due to GIDL, junction leakage, sub-gate punch-through

Reduced Variabilty

– Isolation RDF in Bulk Punch-through Stopper – SRAM Vmin increase

– Global Delta-W effect in Bulk Hfin

– Intra-Fin Subthreshold swing degradation from PT stopper.

SOI provides immediately available solutions to the tactical and strategic challenges.

– Triple-self-alignment of channel, gate, source/drain

– No Swing loss from punch-through stopper gradients.

– No RDF Vmin increases

Superior Integration with dense memory

– Natural eDRAM isolation

– Natural SRAM Vmin superior matching.


Recapitulation

PDSOI Benefits delivered for many generations

Low Power Space in FDSOI provides unique opportunities

beginning at 20nm node.

SOI continues to provide 3D/FinFET Speed/Power/Cost Value

Beyond the 20nm node.

soi value in ibm silicon technology · 10/19/2011 · ibm pd-soi is delivering industry-leading...

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