software driven low power optimization for arm based mobile architectures … · 2016-10-31 ·...
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Confidential
Software Driven Low Power Optimization for ARM Based Mobile Architectures
Frank Schirrmeister, Synopsys
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AgendaA Mobile Device
Where did all the energy go?Components of Energy Consumption
Software Rules PowerChallengesVirtual PlatformsSystemC TLM-2.0Enabling Virtual Platforms for Low Power
ResultsDemonstration: Freescale i.MX31Demonstration: Texas Instruments OMAP2420
Conclusions
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WHERE DID ALL THE ENERGY GO?
A Mobile Multimedia Device Example
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A Mobile Device
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What’s in a Mobile Device?
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A/V andTransport
LCDDriver
Base band to
RF
Dual LNA
RF to Base band
Mobile Station Modem
Processing
LCDControl
AudioMemory
Memory
Video
PowerAnalogASIC
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And where did all the energy go?
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Six CPUs and Various Accelerators!
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3 CPUs
MemoryMemory
AMSAMS
Audio Processor
2 standard CPUs4-6 accelerators
AMS
AMS
AMS
Control
Analog
A/V andTransport
Mobile Station Modem
Processing
Audio
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Software Rules!
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Software
Control Hardware
Memory
Analog / Mixed Signal
Data Flow Hardware
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Power Optimization Techniques
SWDF HWCTRL HW MemoryAnalog/MS
Layout
Gate Level
RT Level
ES Level
Des
ign
Tim
e
Impact on O
ptimization
Highest Impact Optimizations
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COMPONENTS OF ENERGY CONSUMPTION
A three minute excursion to the basics!
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Sources of Power Consumption
Paverage = Pshort
Energy consumption during the switching of CMOS gates when the complementary parts are
open simultaneously
Energy consumption caused by currents during the non-conducting
state of gates
Dynamic energy consumption happens during the data dependent switching of capacities in transistors and the connections between them
+ Pleakage + Pdynamic
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Short Circuit Energy Consumption
Pshort
Energy consumption during the switching of CMOS gates when the complementary parts are open simultaneouslyShorter transition times can help optimize this type of energy consumptionMain influencing parameters
VoltageOperating Speed
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Leakage Energy Consumption
Pleakage
Energy consumption caused by currents during the non-conducting state of gatesMain influencing parameters:
Supply Voltage Vdd
Threshold Voltage Vt
Transistor Size W/LTransitor StateTemperature
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Dynamic Energy Consumption
Pdynamic
Dynamic energy consumption during data dependent switching of capacities (transistors & connections)Often largest contributorMain influencing parameters:
Vdd (Squared)CapacityActivity
Source: ChipVision
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Energy Consumption Trends
<20
~50
~75
>60
~35
~15>20 ~15 ~10
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
>=70nm 45nm 22nm
Leakage Dynamic Short Circuit
Observations:Smaller geometries require improved handling of leakageDynamic energy due to capacity switching remains significant in mainstream design well into the 65nm technology node
ConclusionOptimize data efficiencyOptimize activity, resourcesOptimize SoftwareReduce voltage
Lower clock speed for slower cells at lower voltage
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Mobile Multimedia Drives EnergyMultimedia is performance hungry
Dominates power consumptionDrives processing speed
Software!Impacts memory (caches)drives processor speeds
Memory accesses!
ConclusionMultimedia/Consumer
Drives higher clock speedDrives lots of data transfers
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Source: Linux World 06’06
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SOFTWARE RULESImpact of Software on Power Consumption
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It’s the Software, Stupid …
“Phone differentiation used to be about radios and antennas and things like that. We think, going forward, the phone of the future will be differentiated by software.”
Steve JobsCEO, Apple
August 11, 2008http://online.wsj.com/article/SB121842341491928977.html
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Software starts late Bugs are expensive
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There really are only two issues …
Software has to wait for prototype => Semi cannot
sell silicon …
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ChipArchitecture
Si ProtoRTL Netlist GDSII
Firmware OS & Driver
ProductArchitecture
Device Proto
OS & Driver Middleware Application SW
SI Prototype
Device Prototype
Trad
ition
al
Des
ign
Flow
SemiconductorHouse
System House
Start Software as Early as Possible
ChipArchitecture
Si ProtoRTL Netlist GDSII
Firmware OS & Driver
ProductArchitecture
Device Proto
OS & Driver Middleware Application SW
Device Proto
End
to E
nd P
roto
typi
ngD
esig
n Fl
ow
SemiconductorHouse
System House
SI Prototype
Virtual PrototypeFPGA Prototype
SI Prototype
Virtual PrototypeFPGA Prototype
Schedule Improvement
SDK usage
SDK usage
Previous Chip (for derivative)
Middleware
Previous Chip
Middleware
Software has to wait for prototype => Semi cannot sell silicon …
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End-To-End Prototyping
FPGA Prototype: Pre-SiliconFully functional hardware
representation of SoC, board, I/O
Implements unmodified ASIC RTL code
Runs at almost real-time with all external interfaces and stimulus
connected
High system visibility and control
Virtual Platform: Pre-RTLFully functional software model of
SoC, board, I/O, user interface
Executes unmodified production code
Runs close to real-time with external interfaces as Virtual I/O
High system visibility and controlincl. multi-core debug
Silicon Prototype: Post-Silicon
Using the real chip
Running at real time
Little visibility and control
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Synopsys’ Virtual Platform PortfolioDesignWare®
System-Level Library Innovator Services
High-performance models to build virtual
platforms
SystemC™ TransactionLevel Models
Processors
DesignWare®
System-Level Library
Pre-Assembled Platforms
DesignWare Cores
DesignWareAMBA
Components
Environment for developing, running &
debugging virtual platforms
Expert services for model creation, virtual platform
assembly & customization
Virtual Platforms
Start SW development early and shrink time-to-market using high-
performance Virtual PlatformsEnhance design quality through
SystemC executable specificationIncrease design confidence through complete HW/SW system verification
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Functional Specification – Defining the overall hardware / software system
RTL to GDSII Implementation Flow (Discovery VCS to Galaxy & Synplicity)
Virtual Platforms in the Design Flow
Platform Creation & Analysis
SynopsysInnovator
Platform Deployment
SynopsysInnovator-RT
3rd Party Software
Debuggers
Model Creation
System Studio
SynopsysCreator (XML)
SystemC
DesignWare® System-Level
Library
Your-lib-1Your-lib-1Your-lib-1
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The Impact of SystemC TLM-2.0Previously proprietary (backdoor) APIs & new additions have now been standardized:
(DMI) Direct Memory InterfaceDirect backdoor access into memoryAllows un-inhibited ISS execution
LT (Loosely Timed) modelingTiming declarationAllows speed/accuracy trade-offs
Temporal DecouplingOnly synchronize when necessaryAllows multicore speedup
1G
100M
10M
1M
100K
10K
1K
100
00 100908070605040302010
% Accuracy
Perf
orm
ance
(IPS
)
ESL
Implementation
Speed & Visibility
Accuracy Hardware development
Application software development
(Platform Level !)
AV: Application ViewLT: SystemC Loosely Timed
AT: SystemC Approximately TimedCA: Cycle Accurate
AV
LT
AT
CAFirmware
development
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The Impact of SystemC TLM-2.0Innovator
PV (LT) modeling PV+T (AT) “timing annotation”
DesignWare® IPImplementation, Verification and System-Level IP
Modeling Services
VCSFor hard CA requirements running in software
Synplicity HAPS
1G
100M
10M
1M
100K
10K
1K
100
00 100908070605040302010
% Accuracy
Perf
orm
ance
(IPS
)
ESL
Implementation
Speed & Visibility
Accuracy Hardware development
Application software development
(Platform Level !)
AV: Application ViewLT: SystemC Loosely Timed
AT: SystemC Approximately TimedCA: Cycle Accurate
AV
LT
AT
CA
Innovator Virtual
Platforms
Firmware development
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LOW POWER ENABLED VIRTUAL PLATFORMS
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Power Instrumentation ObjectivesIncrease visibility
Global system stateIndividual power/clock domains
Power trade-offsPerformance vs. powerPower schemes with “system software” load
Power-related SW developmentRelative power consumption used for optimizationPower management softwareSystem power consumption while running actual software
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Power Modeling SupportThe following power support is added to a TLM platform:
Power management modeling Clock modeling – gating, scaling freq(t), …Voltage distribution - power domains, scaling V(t) , …Power state control – power state sequencing (power down, retention, …)
Power estimation equations – evaluated at run-timeDashboards – clocks, state, voltage, power
Applies both to LT & AT modelingLT
Instantaneous power consumption, at each point in timeAT*
Supports trade-off of performance vs. powerGraphs: Power(t) & Energy(t)Improved accuracy for accounting for (memory) transactions power contribution * Under development
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Clock Modeling
Functional clock modelingModels functional operation of the clock controller, including:
Clock distributionIncludes its control over peripheral clock gatingRegisters, to model software control over clock frequencies
Periph
CPU(s)Instruction
Set Simulator
TLM Bus
Master2Master1
Periph
Clock Controller
Signal is used to transmit value of clock frequency from controller to peripheral; does not model actual clock waveform
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Voltage & Power State Control ModelingFunctional models of:
On-chip Power Manager (SoC)
Control of (internal) voltage distribution & domainsState control & sequencing
Power management chip (PMIC)
Voltage scaling of SoCSoC I2C control interface, power sequencing, LDO regulators control, DC/DC convertors, …
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Power Estimation - ConceptsParametrizable power model, consisting of:
Component power characteristicsComponent power calc. equationsPower accumulator
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Power Analysis Concepts
PV / PVT Model
Power EstimationEquation
PowerAccumulator
VoltageFrequency
Power State
Power request / response APIs
Power eventLogging (file)
Power DashboardExample – PRCM (OMAP2420)
Parametrizable model:• Power characteristics• Power equations• Power accumulator
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Component Characterization for PowerPower parameters
Components are characterized by a set of representative power parameters (‘kernels’)Used in power equations to calculate powerFlexible to support specific component characteristics Interactively changeable by user
SourcePower consumption numbers are delivered by semiconductor companyBased on (1) budget planning, (2) estimations, (3) measurements
ExampleCPU
Power active (mA / MHz)Power dormant (mA)Power inactive (mA)Power shutdown (mA)
Peripherals:Power clock off (mA)Power idle (mA / MHz)Power typical (mA / MHz)Power maximum (mA / MHz)
On-chip Memories (RAM / ROM)Power clock off (mA)Power idle (mA / MHz)Power read (mA / MHz)Power write (mA / MHz)
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Power EstimationSystem power estimations expressions, contain:
Component power characteristicsPower state of APLLs & DPLLs { off, on }Power state of domain { off, ret, on }Voltage applied (to domain)
At run-time power estimation expressions are evaluated on the fly, as triggered by user requests
Complements functional component modelLeverage power state & frequency modeling of func. component modelExpressed in C code (Magic-C or C++)
Expressions can be linear, or more complex, depending on:Component typeData / charatistics which can be measured / estimated
Fixed modeling APIs for voltage, frequency & power state updates, and reporting to accumulator
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Power Estimation - Example
ARM1136 (OMAP2420)
PRCM
Powerupdate request
Power updateresponse
MPU Power State (on, off, …)
MPU Clock(frequency (MHz))
MPU Voltage (Volt)
ARM MPU Power Estimation Component
Power Parameters
Graphical C Power Model
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Platform Analyzer *
Power(t)
Energy(t)
Power EventsVoltage
Clocks
States
time
time
Power Estimation – AT Platform
PMIC
System-on-Chip
CPU(s)Instruction
Set Simulator
TLM Bus
SlavePeriph
SystemI/O
TLM B
us
Camera
MemCtrl
FlashMemory
SystemI/O
System/Device
SlavePeriph
USB
Mem
Fixed power f(V,f,st)
Penalty whenCache miss
(Δcache iss) I$ D$
Penalty for each bus transaction
(Δ transaction (length))Fixed power f(V,f,st) Penalty for each bus
transaction (Δ transaction (length))
Penalty for each bus transaction
(Δ sys memory (length))
APLL
DPLL
Fixed power f(freq,St)
* Under development
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On-chip Power Reset Controller
Power Dashboard
Dashboards Examples
Clock Dashboard
SoC Voltage DashboardVoltage Monitor
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RESULTSDemonstrations
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Demo 1: Linux on OMAP2420
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Demo 2: WinCE on i.MX31
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CONCLUSIONS
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Software Rules Power ConsumptionMultimedia drives power consumption in mobile applications
SoftwareMemory Accesses
Virtual Platforms allow pre-silicon embedded software development
TLM-2.0 enables interoperabilityPower instrumentation allows trade offs and development of power related software
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