SoC Verification HW #2

TA: Wei-Ting TuAssignment: 04/12/06

Due: 04/26/06

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Lab introductions Lab 1-3: examples Lab 4-6: exercises

Lab requirements Implement each task in lab 4~6.

References svtb.pdf: SystemVerilog TestBench Guide svtb_tutorial.pdf: SystemVerilog TestBench Tutorial SVTB_2005.06_SG.pdf: SystemVerilog Workshop Student

Guide SVTB_2005.06_LG_01~3.pdf: SystemVerilog Workshop

examples SVTB_2005.06_LG_04~6.pdf: SystemVerilog Workshop

exercises

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Workshop Goal

Acquire the skills to write a SystemVerilog testbench to verify Verilog/SystemVerilog RTL code with coverage-driven random stimulus.

Acquire the skills to write a SystemVerilog testbench to verify Verilog/SystemVerilog RTL code with coverage-driven random stimulus.

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Target Audience

Design or Verification engineerswriting SystemVerilog testbenches

to verify Verilog or SystemVerilog code.

Design or Verification engineerswriting SystemVerilog testbenches

to verify Verilog or SystemVerilog code.

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Workshop Prerequisites

You must have experience in the following areas: Familiarity with a UNIX text editor Basic programming skills in Verilog, VHDL or C Debugging experience with Verilog, VHDL or C

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What Is the Device Under Test?

A router:16 x 16 crosspoint switch

router

din [15:0] dout [15:0]

frame_n[15:0] frameo_n [15:0]

valido_n [15:0]

reset_n

valid_n [15:0]

clock

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0

1

2

3

4

port port

inputs outputs

frame_n[0]

valid_n[0]

din[0]

frameo_n[0]

valido_n[0]

dout[0]

A Functional Perspective

partial view

0

1

2

3

4

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The Router Description

Single positive-edge clock

Input and output data are serial (1 bit / clock)

Packets are sent through in variable length:Each packet is composed of two parts

Header Payload

Packets can be routed from any input port to any output port on a packet-by-packet basis

No internal buffering or broadcasting (1-to-N)

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Input Packet Structure

frame_n: Falling edge indicates first bit of packet Rising edge indicates last bit of packet

din: Header (destination address & padding bits) and payload

valid_n: valid_n is low if payload bit is valid, high otherwise

clock

din[i] A0 A3A2A1

valid_n[i]

d0 ....x dndn-1 x

frame_n[i]

pad payload

x

x x x x x

dest. address

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Output Packet Structure

clock

dout[i]

valido_n[i] x

dn-3 xx

frameo_n[i]

x

dn-2 dn-1xd1d0 x xd2x d3

Output activity is indicated by:frameo_n, valido_n, and dout

Data is valid only when: frameo_n output is low (except for last bit) valido_n output is low

Header field is stripped

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Reset Signal

While asserting reset_n, frame_n and valid_n must be de-asserted

reset_n is asserted for at least one clock cycle

After de-asserting reset_n, wait for 15 clocks before sending a packet through the router

clock

reset_n

frame_n[i]

15 clock cycles

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The DUT: router.v

The Design Under Test, router.v, is a Verilog file: Located under the rtl directory From the lab workspace: ../../rtl/router.v

router.vlab1/ lab2/ lab6/

lab work files

lab1/ lab6/

solutions/labs/ rtl/

~

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The SystemVerilog Test Environment

Testprogram

Testprogram

interfaceinterface

Monitor

TransactorSelf Check

Observes datafrom DUT

Observes datafrom DUT

Identifiestransactions

Identifiestransactions

Checkscorrectness

Checkscorrectness

Coverage

Driver

Generator

DUT

Transactor

Configure Checkscompleteness

Checkscompleteness

Top level harness file

Top level harness file

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SystemVerilog Testbench Building Process

simv

router.vr.tmp

ntb_template -t router router.v

router.if.vrh

router.test_top.sv

Discard

vcs –sverilog router.test_top.sv router.tb.sv router.if.sv router.v

router.if.sv router.tb.svTop level harness Interface Test program

router.test_top.v

router.v

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Create Verilog Test Harness File

Use VCS template generator

Generates three files: router.test_top.v Verilog test harness file router.if.vrh Discard (for OpenVera only) router.vr.tmp Discard (for OpenVera only)

-t router Specifies DUT module name

router.v DUT source code file

router.test_top.v will be used to help build SystemVerilog testbench files

ntb_template -t router router.v

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interface router_io(input logic clock); logic reset_n ; logic [15:0] din ;//wire clock; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ;endinterface

module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; wire reset_n ; wire [15:0] din ; wire clock ; wire [15:0] frame_n ; wire [15:0] valid_n ; wire [15:0] dout ; wire [15:0] busy_n ; wire [15:0] valido_n ; wire [15:0] frameo_n ;`ifdef SYNOPSYS_NTB ...`endif router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endendmodule

Creating SystemVerilog Interface File

Create interface file from router.test_top.v

Encapsulate signals in interface block

router.test_top.v

Move clock to input argument

cp router.test_top.v router.if.sv

Change wire to logic

router.if.sv

Create from default harness fileChange module to interface

Delete all except wires

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Define Test Program Interface Port

By default all interface signals are asynchronous

Synchronous signals can be created via clocking block and connected to test program via modport

interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; logic [15:0] dout ; logic [15:0] busy_n ; logic [15:0] valido_n ; logic [15:0] frameo_n ; clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; input dout; input busy_n; input valido_n; input frameo_n; endclocking modport TB(clocking cb, output reset_n);endinterface

Create synchronous by placing signals

into clocking block

Define connection for test program

with modport

Monitor

TransactorSelf Check

Coverage

Driver

Generator

DUT

Transactor

Configure

Direction w/respect to test

Synchronous Asynchronous

router.if.sv

Sample/drive skew

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program automatic router_test(router_io.TB router);

// develop test code in initial block:

initial begin

$vcdpluson; // Dumping file control

$display(“Hello World”);

end

endprogram

Build Testbench

Testbench is encapsulated in program block List interface signals in argument

router.tb.sv

Monitor

TransactorSelf Check

Coverage

Driver

Generator

DUT

Transactor

Configure

Both synchronous and asynchronous signals are encapsulated in modport

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program automatic router_test(router_io.TB router); //testbench code in initial block: initial begin $vcdpluson; // Dumping file control// $display(“Hello World”); end initial begin reset(); end task reset(); router.reset_n <= 1’b0; router.cb.frame_n <= 16’hffff; router.cb.valid_n <= ~(’b0); ##2 router.cb.reset_n <= 1’b1; // reset_n can be both synchronous and asynchronous

repeat(15) @(router.cb); endtaskendprogram

Sample Testbench

Develop test program code in initial block

interface router_io(input logic clock); logic reset_n ; logic [15:0] din ; logic [15:0] frame_n ; logic [15:0] valid_n ; ... clocking cb @(posedge clock); default input #1 output #1; output reset_n; output din; output frame_n; output valid_n; ... endclocking modport TB(clocking cb, output reset_n);endinterface

Asynchronous signals are driven without reference to

clocking block

Advance clock cycles via clocking block

Synchronous signals are driven via clocking block

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Driving Synchronous Device Signals

Must be driven with <= (non-blocking assignment)

Can be specified with ##num of clocks delay

Equivalent to:repeat(num) @(router.cb);router.din[3] <= #input_skew_value var_a;

router.cb.din[3] = 1’b1; // error (must be non-blocking)

var_a

din[3]

##1 router.cb.din[3] <= var_a;

clock

Statement executes here Variable expression evaluates

Apply drive here Next statement executes

[##num] interface.cb.signal <= <value> or <variable expression>;

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Sampling Synchronous Device Signals

No delay attribute (## num)

Variable is assigned the sampled value

Sampling of output signal is not allowed

Examples:

data[i] = router.cb.dout[7];

all_data = router.cb.dout;

@(posedge router.cb.frameo_n[7]);

$display(“router.cb.din = %b\n”, router.din);//error

if(router.cb.din[3] == 1’b0) //error

variable = interface.cb.signal;

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Advancing Simulation Time

Asynchronous (Verilog coding style):

#delay;

@(negedge interface.signal); Synchronous (advancing clock cycles):

Verilog coding style:

@(posedge interface.clock_signal);repeat (10) @(posedge interface.clock_signal);

SystemVerilog coding style (clocking block):

@(interface.clocking_block);

repeat (10) @(interface.clocking_block); Each clocking block specifies a clock signal and edge:

interface router_io(input logic clock); clocking cb @(posedge clock); ... endclocking endinterface

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module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; wire reset_n ; wire clock ; wire [15:0] frame_n ; wire [15:0] valid_n ; wire [15:0] din ; wire [15:0] dout ; wire [15:0] busy_n ; wire [15:0] valido_n ; wire [15:0] frameo_n ;`ifdef SYNOPSYS_NTB ...`endif router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endendmodule

Create SystemVerilog Harness File

Create harness file from router.test_top.v

router.test_top.sv

mv router.test_top.v router.test_top.sv

module router_test_top; parameter simulation_cycle = 100; reg SystemClock ; router dut( … ); initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; end endendmodule

router.test_top.sv

Monitor

TransactorSelf Check

Coverage

Driver

Generator

DUT

Transactor

Configure

Delete all wire declarations and all OpenVera stuff

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module router_test_top;parameter simulation_cycle = 100;reg SystemClock ;router dut( .reset_n(reset_n), .clock(clock), .frame_n(frame_n), .valid_n(valid_n), .din(din), .dout(dout), .busy_n(busy_n), .valido_n(valido_n), .frameo_n(frameo_n));initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; endendendmodule

Complete Top Level Harness File

Instantiate test program and interface in harness file

router.test_top.sv

module router_test_top;parameter simulation_cycle = 100;reg SystemClock;router_io top_io(SystemClock);router_test test(top_io);router dut(.reset_n(top_io.reset_n), .clock(top_io.clock), .frame_n(top_io.frame_n), .valid_n(top_io.valid_n), .din(top_io.din), .dout(top_io.dout), .busy_n(top_io.busy_n), .valido_n(top_io.valido_n), .frameo_n(top_io.frameo_n));initial begin SystemClock = 0 ; forever begin #(simulation_cycle/2) SystemClock = ~SystemClock ; endendendmodule

Instantiate interface

Instantiate test program

Connect SystemClock to interface block

Update DUT instantiation using

interface connection

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Compile RTL & Simulate w/ VCS NTB

Compile HDL code: (generate simv simulation binary)

> vcs –sverilog [-debug] router.test_top.sv \

router.tb.sv router.if.sv router.v

Get vcs compiler switch summary:

> vcs -help

Simulate DUT with SystemVerilog testbench: (running simv)

> ./simv

router.test_top.svrouter.test_top.svMonitor

TransactorSelf Check

Coverage

Driver

Generator

DUT

Transactor

Configure

router.tb.svrouter.tb.sv

router.if.svrouter.if.sv

router.vrouter.v