soc & sop technologies for power...
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 1
page 1Filenam e: \PEMC-03\A02 ()\SoC-02Introduct ion to S oC and SiP.ppt
200533
POWERLABNCTU
DSPPower Electronics IC & DSP Control Lab.
Power Electronics IC Design and DSP Control Lab., NCTU, Taiwan
Introduction to SoC & SoP
page 2
Contents
1. SoC: System-on-a-Chip2. Intellectual Property (IP)3. Packaging Technology for Electronic Systems4. SoP: System-on-a-Package5. SoC & SoP for Next Generation Power Supplying
page 3
SoC: System-on-a-Chip
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
page 4
Signals
Continuous-time signals are functions of a real argumentx(t) where t can take any real value
x(t) may be 0 for a given range of values of t
Discrete-time signals are functions of an argument that takes values from a discrete set
x[n] where n {...-3, -2, -1, 0, 1, 2, 3...}
Integer index n instead of time t for discrete-time systems
Values for x may be real or complex
page 5
Signals
( )
=
=
otherwise00for 1
][
otherwise00for 1
kku
ttu
A function, e.g. sin(t) or sin(2 k / 10), useful in analysisA sequence of numbers, e.g. {1,2,3,2,1} or a sampled triangle function, useful in simulationA collection of properties, e.g. even, causal, stable, useful in reasoning about behaviorA piecewise representation, e.g.A functional, e.g. (t)What everyday device uses twosinusoids to transmit a digital code?
page 6
Analog Signal vs. Digital Signal
Amplitude of an analog signal can take any real or complex value at each time/sample
Amplitude of a digita l s ignal takes values from a discrete set
1
-1
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 2
page 7
Systems
A system is a transformation from one signal (called the input) to another signal (called the output or the response).Continuous-time systems with input signal x and output signal y (a.k.a. the response):
y(t) = x(t) + x(t-1)y(t) = x2(t)
Discrete-time system examplesy[n] = x[n] + x[n-1]y[n] = x2[n]
page 8
SoC Definition
SoC = System On ChipDifferent definitions depending on the applicationA SoC can be a system including:Definition 1DSP, Memory, interface circuitry..Definition 2Digital signal processing, mixed signal components and RFcomponents.
page 9
SoC: System on Chip
SystemA collection of a ll kinds of components and/or subsystems that are appropriately interconnected to perform the specified functions for end users.
A SoC design is a product creation process whichStarts at identifying the end-user needsEnds at delivering a product w ith enough functional satisfactionto overcome the payment from the enduser
Also named System-on-a-Chip. System LSI, System-on-Silicon, System-on-.It used to be System-on-a-board, or System-in-acabinet, or System-in-a-room
page 10
SoC Architecture
I/O pads
I/Opa
ds
I/Opads
1149.1 TAP controller
U se r
-def
i ned
logi
c
CPUcore
Sel f-testcontrol
Legacycore
IP hardcore
DSPcore
Memoryarray
Interfacecontrol
EmbeddedDRAM
Hardware Analog : ADC, DAC, PLL, TxRx, RFDigital : Processor, Interface, AcceleratorStorage : SRAM, DRAM, FLASH, ROM
Software Operating System, Application Software, etc.
Memory
DSPor
Special FU
OCB Architecture
ProcessorEmbeddedSof tware
RTOS
ConfigurableHardware
RF
Mixed Signal
JTAG
interface
peripherals
page 11
SoC - An Example: Complete Bluetooth Radio op Chip (Alcatel isscc 2001)
page 12
SoC - An Example: A Mobule Computing Chip
Mobile Computing
SDRAMROMFlas h
PCcardCF
RF
RGB Moni tor LCD Mono/Colour(S TN/ TFT)
Speaker/ Mic RF 115k to 4 Mkeyboard SIM PC
RS232
RS232
MMC
Joys tick
Pen
MemoryAnd
ExpansionControlModel
Incl. PCMCIA
RTCTimerGPIO
IRQ contrPower man
JTAG de bugPLL & SOC
HWAcceleration
VGAController
LCDcontroller
VoiceCodec
SoundContr
BasebandCodec
K/BContr
IrDAContr
SmartCardContr
USBContr
APB BridgeDMA Contr UART#1(16C550)
UART#2(16C550)
SPI
JoystickContr
Digitizer
ASBAPB
On chipMemorySRAM,ROMFlash
EEROM
DSPcore
MemoryX
MemoryYCache MMU
ARMCore
CacheContr
Write buffer
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 3
page 13
System Integration of a Mobile Phone
page 14
System Integration of a PCMCIA Wireless Card
page 15
SoC Applications
CommunicationDigital cellular phoneNetworking
ComputerPC/WorkstationChipsets
ConsumerSet top box, Game boxDigital camera
Power ElectronicsMotor Control, Robotics, DVD Drives, etc. Power Supply Control, Power Management, etc.
page 16
Benefits of Using SoC
Reduce overall system costIncrease performanceLower power consumptionReduce size
page 17
Intellectual Property (IP)
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
page 18
Challenges in SoC Era
Time-to-marketProcess roadmap accelerationConsumerization of electronic devices
Complex systemsCs, DSPs, HW/SW , SW protocol stacks, RTOSs, digita l/analogIPs, On-chips buses
Deep submicron effectsCrosstalk, electronmigration, wire delays, mask costs
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 4
page 19
How to Conquer the Complexity in SoC Design?
Use a known real entityA pre-designed component (IP reuse)A platform (architecture reuse)
PartitionBased on functionalityHardware and software
ModelingAt different levelConsistent and accurate
page 20
What is IP?
Intellectual Property (IP) Intellectual Property means products, technology, software, etc.that have been protected through patents, copyrights, or trade secrets.
Virtual Component (VC)A block that meets the Virtual Socket Interface Specification and is used as a component in the Virtual Socket design environment.Virtual Components can be of three forms Soft, Firm, or Hard. (VSIA)
Also named mega function, macro block, reusable component
page 21
Reusable Component
A design objectThis refers to the type of components for which a physical implementation exists that can be reused.For example, ALU chips or macrocells that can be embedded in larger chips, etc. These designs are largely implemented in specific technologies.Limited parameter ization may be possible. These design objects typically exist in technology librar ies from one or more suppliers.
Reference: EDA Industry Standard Roadmap 1996page 22
Types of IP
Process porting
Technology fixed
Specific library Characterized cells Fixed process rules
Poly gon dataRouting verification
Soft Not flexible Very predicable
Library mapping
Technology generic
Reference library Footprint Timing model Wiring model
RTL & constraints netlist
Sy nthesis floorplanningplacement
Firm Flexible Predicable
UnlimitedTechnology independentN/ABehav ioral RTLSy stem design
RTL design
Soft Very f lexible Not predicable
PortabilityTechnologyLibrariesRepresentationDesign Flow
page 23
IP Value
Foundation IP Cell, MegaCellStar IP ARM ( low power )Niche IP JPEG, MPEGII, TV, FilterStandard IP USB, IEEE1394, ADC, DAC..
page 24
IP Sources
Legacy IPfrom previous IC
New IPspecifically designed for reuse
Licensed IPfrom IP vendo
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 5
page 25
Why IP?
Dont know how to do itCannot wait for new in-house developmentStandard/Compatibility calls for it
PCI, USB, IEEE1394, Bluetoothsoftware compatibility
page 26
Differences in Design Between IC and IP
Limitation of IC designNumber of I/O pinDesign and Implement all the functionality in the silicon
Soft IPNo limitation on number of I/O pinParameterized IP Design: design all the functionality in HDL code but implement desired parts in the silicon IP compiler /Generator: select what you want !!More high level auxiliary tools to verify designMore difficult in chip-level verification
Hard IPNo limitation on number of I/O pinProvide multiple level abstract modelDesign and Implement all the functionality in the layout
page 27
SoC Development Platform
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
page 28
Modern PC Design: System-on-a-Chip
in both hardware and software co-design,as well as in embedded applications,be familiar with optimization techniques to perform the specific program using the least size, power, and time.
How do we design such large systems.
12 million logic gates can now be placed on a single chip
Computer designers must be experienced:
page 29
A Design Challenge: SoC Design for Celluar Phone
Audiointerface
RFInterface
Speaker Mic
User Display
Keyboard
SIM Card
DSP Core
ARM RiscCore
S/W
S/W
AS
IC B
ackp
lane
Op Amps
Switches
Regulators
Touch ScreenSingle chip
Digital baseband
RF section
Receive
Mo dulator
SynthesizerPowerAmp
Drive r
page 30
SoC Development Platforms
Hardware IP Development Using High-Level IC Design Tools
VHDLVerilog
32-Bit ARM (Advanced RISC Machine) ProcessorInstruction SetsSystem Software
Advanced Single-Chip DSPInstruction SetsPortable Digital Signal Processing SoftwareReal-Time Embedded Operating SystemsHigh-level programming langualtes
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 6
page 31
Future Electronic System Development Platform
Integration and Improvement
Power Supply, Control, and Management
DC/DC Battery Charger Power Mgmt.
page 32
Architecture for Digital Design
MACUnit
AddrGen
mP
Prog Mem
Embedded Processor
(lpArm)
Direct MappedHardware
EmbeddedFPGA
DSP(e.g. TI 320CXX )
Flex
ibili
ty
Area or Power
ReconfigurableProcessors
(Maia)Factor of 100-1000
100-1000 MOPS/mW
10-100MOPS/mW
.5-5MIPS/mW
page 33
Abstraction Levels and Synthesis in VLSI IC Design
Architectural level Logic level Circuit level
Beh
avio
ral
lev
elS
truc
tura
l le
vel
For I=0 to I=15Sum = Sum + array[I]
0
0 0
0
State
Memory
+
Control
Clk
Archi tecturesynthesi s
Logicsynthesi s
Circui tsynthesi s
Layout level
La youtsynthesi s
Silicon compilation (not a big success)
(Library)(register level)
page 34
Basic IC Design Methdology
Requirements
SimulateRTL Model
Gate-levelModel
Synthesize
Simulate Test Bench
ASIC or FPGA Place & Route
TimingModel Simulate
page 35
IC Design Flow
The process of converting an idea to a chip is called the VLSI Design Process.VLSI Design Process involves a sequence of steps Flow.Tools that enable the design process are called CAD (Computer Aided Design) tools for VLSI.
page 36
Cell-Based Design Flow
RT Level
Gate Level
SPW
Verilog-XL Polaris, VSS
Design compiler VirrSythesis
Verilog-XL
Silleon Ensemble DraoulaApollo Hercules
Timertil, star-timeStar-skit
Visual Architect
BCNeS
HDL Debugger
Cell UbraryComparsion [0. Bum 26un]
Sma rt model
GDSII
Tapeout
RC Extraction (Star-RC, Dracula)
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 7
page 37
N-Dimensional Design Space
Design is finding the optimal point in this space meeting the erformance requirement(s) with minimal power and area.
page 38
Area of Processor Cores = Cost
30
25
20
15
10
5
027 16.9 15.0 12.4 9.1 7.1 6.0 4.5 3.0
Inte
l 386
Mot
orol
a C
PU
32+
LSI R
3000
NE
C V
910 H
itach
SH
-2
AR
M6
AR
M7
Por
anha
-32
Por
anha
-16
Cor
e A
rea
in m
m2
Nintendo Processor Cellular phones
page 39
Five Degrees of Freedom for Low Power Design
5 degrees of freedom inherent in the low-power design space
Supply voltage (voltage scaling)Switching activity (scheduling)Total no. of transistors (circuit minimization)Operating frequency (IC layout, process innovation)Physical capacitance (process innovation)
These parameters are not completely orthogonal and cannot be optimized independently.
NfCV21P c2ddD =
page 40
IC Design with Power Density
Formal definition of a hotspotAn area of high power density
Power Density = Power
Area
Processor
high power density
low power density
page 41
Y-Chart: VLSI IC Design in Three Domains
Behavioral domain Structural domain Physical domain
StructuralDomain
Behav ioralDomain
Processor
Regist erALU
Leaf Cell
Transistor BooleanEquation
ModuleDescription
FiniteState
Machine
Algorithm
Mask
CellPlacement
ModulePlacement
ChipFloor plan
Physical Domain
Si
page 42
Design Environment for SoC WLAN
Synopsys ,Cade nce, Unica d
Structur
alAmplifiers , Fi lters, A/D, PA, InductorsDedic ate d Logic, Pleiades , VHDL,
Sche matic s
Embe dded P, Progra mmable DSP
(C, As sembl y)
Spectre and Spectre RF
ARM ulator,ARM Compiler
Anal og RF, Passiv es, Mi xed
Signa l Behavio
ralCommunications Engi neeri ng/DSP
Protocol s/Contr ol
VCCMa tla b
Simul inkSimul ink,State fl ow
C, Sta teflow
Physica
lAnal og Compone nt Librari es
(La yout, S KILL)
Func. Module s (RAM, ROM, Mult)
Standar d CellPlace and Route
Agile nt ADS ASITI CCade nce
Progra mmable Cores DSP, ARM,
FPGA(C, V HDL, Asse mbl y
ARMFP GAs
Unica dCade nce, MentorPower & TimeMill
Conceptu
alSpecificationMatlab, Opnet
Opne t, VCCMatla b Matla b
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 8
page 43
VHDLVery high speed integrated circuit Hardware Description Language
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit. VHDL describes the behavior and structure of electronic systems, but is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs, such as ASICs andFPGAs as well as conventional digital circuits.VHDL aims at modeling or documenting electronics systems. Due to the nature of hardware components which are always running, VHDL is a highly concurrent language, built upon an event-based timing model.VHDL is a notation, and is precisely and completely defined by the Language Reference Manual (LRM). VHDL is an international standard, regulated by the IEEE. The definition of the language is non-proprietary.
page 44
VHDL Advantages
Standard: VHDL is an international standard, regulated by the IEEE.US Government support: The Department of Defense (DOD) requires contractors to supply VHDL for all Application Specific Integrated Circuit (ASIC) designs.Industry support: Companies use VHDL tools not only with regard to defense contracts, but also for their commercial designs.Portability: The same VHDL code can be simulated and used in many design tools and at different stages of the design process.Modeling capability: VHDL was developed to model all lev els of designs, from electronic boxes to transistors. VHDL can accommodate behavioral constructs and mathematical routines that describe complex models, such as queuing networks and analog circuits. It allows use of multiple architectures and associates with the same design during various stages of the design process.Reusability: Certain common designs can be described, verif ied, and modified slightly in VHDL f or future use.Technology and foundry independence: The f unctionality and behavior of the design can be described with VHDL and verified, making it foundry and technology independent.Documentation: VHDL is a design description language which allows documentation to be located in a single place by embedding it in the code.New design methodology: Using VHDL and synthesis creates a new methodology that increases the design productiv ity, shortens the design cycle, and lowers costs.
page 45
VHDL Modeling Capability
Transistor
VHDL Mod
eling Capa
bility
Board
Box
System
ModuleASIC
BlockGate
page 46
Top-down VHDL-based Design Methodology
VHDL Description
Functional Simulation
Synthesis
Timing verification
Floorplan, placement and routing
page 47
Philips SoC Solution for Automotives
Most importantly, we combine cutting-edge embedded SoC capabilities (including a strong focus on ARM-based systems) with a proven track record in automotive applications. From innovative CAN devices to world-beatingDSPs, Philips Semiconductors extensive range of automotive products underlines our commitment to this market. And when it comes to applying our automotive know-how to SoCdev elopment, we hav e resources second-to-none, from the most advanced prototyping tools to a worldwide network of Technology Centers prov iding specialized design support at a local level.
Talk to Philips Semiconductors and discover an automotive SoC partner who speaks your language.
page 48
SoC in Automotive Applications
Sys te m Diagnosis Trans miss ion engi ne braki ng sus pens ion
Nav igati onGl obal posi ti oni ng digi tal ma p
Audio pr ocessi ngDigi tal ra dio compact disk graphic equaling s ound enhance me nt
Cellul ar phoneVoice diali ng filteri ng
Ada ptiv e ride control car lev el control
Activ e sus pe nsi on s yste mHydra ulic or air press ure c ontrol car atti tude dynami c control
Electronic steeri ng4-whee l ste ering
Voice c omma ndSpeec h rec ogniti on (E. G. lights, window) speaker v erifica ti on for sec ure lock
Anti-l ock brakesTracti on control
Engi ne c ontr olIn-k nock c ontrol trans missi on control
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 9
page 49
ARM Cores Power PhilipsAutomotive SoC Designs
400
Mips
ARM - CP U c ores a da pte d by P hili ps ARM c ores offer the high per for mance 32 -bit, e mbe dded R ISC architecture v ital for ne xt ge nerati on a utomotiv e SoCs, a nd P hili ps Semi conduc tors prov ides unique expertise to build ARM-base d s olutions. We hav e more ex perie nce in ARM core s tha n any other semic onductor supplier, with a pr ov en tra ck recor d of ov er 150 embedde d ARM desi gn-ins (ofte n incor porati ng a de dica ted DSP co-pr ocess or core ) and more tha n one hundre d milli on ARM-base d SoCs shi pped to c us tomers. This exce pti onal k now-how c omple me nts the i nherent and numerous adv anta ges of ARM c ores the mselv es. Their robus t, eas y arc hitecture is base d on an ex tens iv e roa dma p for low c ost, low power dev ices suppor ting numer ous opera ting s ys tems and ens uring excelle nt code de nsi ty. Furthermore, third party IP bloc ks a nd desi gn tools are av ailable, i ncl uding Phili ps Se mic onductors unique Vel ocity. Rapi d Silicon Pr ototypi ng (RSP) s ystem ori ginall y dev eloped for ARM7 and now bei ng extende d to the ARM946 archi tec ture.
100
200
ARM7 TDMIARM7 -S
ARM9 TDMIARM9E -S ARM966E -S
ARM740 T
ARM94 oTARM946E -S
ARM720 T
ARM920 /22 TARM926E -S
ARM102 0EARM102 0EJ
Functionality
ARM-CPU cores adapted by Philips
Bas
icco
r es
Un-c
ache
d cor
e s
for h
ard re
al-ti
me
app l
icatio
n s
Cach
ed co
res
for e
mbed
d ed
rea l
-
time
app l
icatio
n s
Cach
ed co
res
for f
ull M
MU
supp
ort f
o r p
latfo
rm
OS:
Win
CE &
Ep o
c
page 50
IP Portfolio for SoC Development
And much more
GSM GPS Ethernet Bluetooth ADC
I2C CAN SPIUSB UART 1394
AMBA
ARM DSP
SRAM ROM DRAM NV-Flash
OSC PLL Control Speech Audio Video HF
ConnectivityPeripherals
Bus peripheralsArchitectureFramework
Bi-Core
Core
Memories
Analogue
Std. Cell & I/O
Extended IP Portfolio
page 51
System Integration Simulation Using Simulink-ModelSim
What is ModelSim? ModelSim sim ulates Verilog (and VHDL) source code. In contrast, the Xilinx andAltera simulators simulate from an EDIF file, which has advantages anddisadvantages. One advantage: EDIF is more similar to the hardware. A strong disadvantage: the synthesizer removes or renames signals as it sees fit - it can be hard to recognize your own design. A big advantage of using ModelSim: it 's very pedantic about suspicious coding style.
page 52
Mapping the Simulink Algorithm into Hardware
RF XMI T Channel
Pilot ACK
Sampled Sig nal
Pilot ACK
Known Value
Data Sym bols
Connected S ignal
Phase Correc tion
Data outBasebandTransmitter
I
Q
symbols
Baseband Trans mitte r
RF T ransmit ter(Baseband Eq uivalen t)
Channel(Baseband Eq uivalen t)
In1
In2
Out1
Out2
rf (baseband equ iv.)
ReIm
Freq. Co rrecte d Si gnal
Pilot Sy mbol ACK
Known P ilot Sym bols
Frequenc y Cor rection
Data Clock
Symbo l Clock
Signal In
Tim ingSynchr onizati on
DA/DD Phase Locked Loo p
Im( u)
Re(u)
Complex t oReal-lmag
NotZ-1
In_r
In_i
Out_r
Out_i
matched filte r
|u|u
Complex t oMagnitude -Angle3
ReIm
u|u|
Symbo l phase
Symbo l amp
Complex t oMagnitude -Angle1
page 53
Mapping the Algorithm into Hardware
page 54
Packaging Technology for Electronic Systems
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 10
page 55
Development of Electronic Technmology
Vacuum tubesDiscreteIntegratedCPLD (digital)FPGA ( digital logic including DSP, memory, interface ..)DSP (AVR, PIC -> Shark ..)Wired cards, PCB, flexible, u-vias ...BGA, CSP ...
page 56
Evolution of Packaging Technology
page 57
Hierarchical Assembly of an Electronic System
LSI
FCWBTAB
CSP
MCM()
FCWBTAB
(BGAPGAQFPSOP
)()
()
Back Board()
page 58
Trend of IC Package
1980 1990 2000
Den
sity
QFP
BGA
ConventionalCSP
Wafer LevelCSP
1970
page 59
Chip Package Products
Plastic Ball Grid Array (PBGA) Packages
Quad Flat Packs (QFPs)
page 60
Evolution of Silicon Design
0.13u
8~6
3~210~25 M
Ubiquitous computing intelligent, interconnected controllers
0.18u
10~8
4~24~6 M
Internet appliances, anything portable
0.25u
12~10
6~41~2 M
Set-top boxes, wireless PDA
0.35u
18~12
8~6200~500 k
Cellular, PD As, DVD
Process technology
Design cycles (month)
Derivative cycle (month)Silicon complexity (gate)
Applications
2002199919981997Year
Source: Surviving the SOC Revolution - A Guide to Platform- Based Design by Henry Chang et al, Kluwer Acad emic Publishers, 1999
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 11
page 61
Electronic System Assembly
Front End UCrate UPDUcrate = TRD electronic crateUBP = TRD backplaneUPD = TRD power distribution boxUPC = TRD power controller (USCM)
UPSFE = TRD power supply for front endUDR = TRD data reduction boardJINF = data concentrator and link to higher DAQ for TRDUHVG = TRD high voltage generatorUFE = TRD tube endUHVD = TRD high voltage distributor
DC
/DC
UPD
to P DB
UBP
UPCUPSFE
UDR
JINF
UHVG
UFEUTEUHVD
T emp. m
eas .
HV
Power/ Data
Data
PowerCtrl
CAN bus
toTrigger/DA Q
page 62
Electronic System Packaging Technology
Third Level package(Mother board)
First Level package(Multichip Module)First Level package(Single chip Module)
Second Level package(PCB or Card)
Wafer
Chip
COB
page 63
PCB-Based Interconnect and Packaging Design
Product Enclosure
Package
Die
Packaged PartPrinted Circuit Assemblies
Interconnect Substrate
Die
page 64
System Interconnect
The term system interconnect refers to the logical, physical, and electrical connection of a signal, its associated return path, and its power delivery system.
The system interconnect travels from an IC I/O buffer through a bump and package substrate to a package pin, across a printed circuit board and connector, back through another PCB, to a package pin and through a package substrate and bump, to another IC I/O buffer. Currently, the system interconnect is designed and implemented sequentially across the domains of IC, IC packaging, and PCB in a relatively long and costly process.
Transmitting I/Obuffer on chip
I/O padon chip
Pad onIC package
Board to board Receiving I/Obuffer on chip
I/O padon chip
Pad onIC package
page 65
Package for Cooling of Advanced Microprocessors
Package types: Below 1 watt: Plastic Below 5 watt: Standard ceramic Up to 30 watt: Special
Passive heat sink Active heat sink Water cooled mainframe computer
page 66
Interconnect and Packaging Design
Technology
Physical Component Placement Bare Board Design Layout templates Layers non-planar,
conductive & non-conductive Material product
Geometrically Bounded 2-D Wireframe with Topology Surfaces Advanced BREP Solids Constructive Solid Geometry
Part Functionality Analysis Support Shape 2D, 3D Package Material Product Properties
Configuration Mgmt Identification Authority Effectivity Control Requirement Traceability Analytical Model Document References
Product Structure/Connectiv ity
Functional Packaged
Fabrication Design Rules Product Design Rules
Requirements Design Allocation Constraints Interface Rules
Geometric Dimensioning and Tolerancing
Geometry
Design Control
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 12
page 67
SoC Integration Technology Roadmap
Integration
Size
Vacuum tubes
Programmable
Discrete
Integrated
SoP
SoC
page 68
Today System-on-a-Chip
Digital logic Mixed components RF/Analog components
SoC System on Chip
page 69
SoP: System-on-a-Package
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
page 70
SoC or SoP ?
CostElectrical PerformanceManufacturabilitySizeRoutabilityTestabilityThermal Management
Trade-off ParametersSoC System on Chip
SoP System on Package
Organic, Laminate based (Low-cost)High Dielect Electrical Constant Materials (40 @2,4GHz)Embedded PassivesDesign Libraryfor Embeddedpassives
page 71
SOC & SOP Solutions
SoC & SoP SolutionsSoC & SoP Solutions
TBGA Flip Chip BGA Sys te m on a Chi p (SoC) Performance die, high pin coun t B GA Die/package are a ratio
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SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 13
page 73
SoC and SoP: its not just to put everything together ...
Productivity Crisis Designers ability are not tracking the
Moore curve ( ~ 20K gates/m) Bad design flow: rework, iteration of
design cycles Partially tackled with reuse and IPR-
based design, virtual components
Dependability Issues Deep submicron technologies Signal integrity, power integrity Mixed-signal coupling Availability of components Veri fication and test
page 74
System Implementation: SoC and SoP
Figure-of-Merit = Performance (function)
Cost x Time-to-Market
SoC (System-on-Chip): A single chip integrated system or system
platform, including system hardware (digital, analog/RF) and embedded software/OS
Based on DSM CMOS technology
SoP (System-on-Packaging): A convergent microsystem integrated on a
microboard; also a platform based system, includin g hardware (digital, analog/RF, MEMS) and embedded software/OS
Based on advanced packaging and assembly technologies;
Overcome formidable integration barrierswithout compromising individual chip or component technologies
page 75
Techniologies Integration for System-on-Chip
System on Chip
Embedded systems & software
Deep submicrondigital circuits
RF and mixed signal
SoC and interconnectcentric architectures
System modelingand validation
Reusability and intellectual property
Testability andfault tolerance
Digital system engineeringand System-on-Package
ASIC design
Methodologyand CAD tools
page 76
Future Development Trend of SPS
Development of SoC & SoP Technologiesfor Next Generation Power Supplying
DSPPower Electronics IC Design & DSP Control Lab.
Powe r Electronic s IC Design and DSP Control Lab., NCTU, Taiwan
page 77
Development Status of Switching Power Supplies
Changes in technology are APPLICATION driven Distributed Power Supplies
50V, 100A
withPFC
PRE-REGULATO RS
Power Factor Correction
High power densityon board converters
Soft switching techniquesLow voltage converters (1V)Planar magnetics
page 78
Powering Advanced Microprocessors
Pentium IV: 5,500 , .13 m3.2GHz, 1.7VRated: 92W, Peak: 110W
New specs demand new power solutions!
Inte l Pentium IV
-
SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 14
page 79
What are the new applications?
Be Mobile
HumanImplants
Mobilephones
PDAs
HandhelpPC
NotebookComputers
MobileIndustrialsensors
MobileIndustrialactuators
HumanImplants
Mobilephones
PDAs
HandhelpPC
PER
FOR
MA
NCE
PROCESSOR ENERGY
Challenges for the New Millennium
MobileIndustrialsensors
MobileIndustrialactuators
ComputersTablet
page 80
What are the new applications?
Multidisciplinary
EnergyGeneration
EnergyStorage
RFtransceiver
Processor Digital logic Memory
EnergyConversion
ENERGY MANAGEMENTENERGY MANAGEMENT
EnergyGeneration
EnergyStorage
RFtransceiver
Processor Digital logic Memory
EnergyConversion
ENERGY MANAGEMENT
page 81
Possible Power Supply for Future (2010) Microprocessors
Possible Specs:Distributed power supply within the chip packageDC input range: 0.5VMaximum Current: 250AInput Voltage: 48VDC or 12VDCEfficiency > 90%Size: 0.1x044x0.1 inchPower Density: 1000W/in3
DC-DCConverter
Multiple SystemsONA Chip
FilterCapacitor
page 82
Multi-Phase Converters
DC/DC
DC/DCDC/DCDC/DCDC/DCDC/DC
IIN/N
Paralleling
Phase shiftMultiMulti--phase convertersphase converters
N N Integration
Digital controlHomogeneous powerHomogeneous power
page 83
Digital Control of Multi-Phase Converters for Advanced mP
Discrete implementation
Digital control
page 84
Power-Digital-Analog Integrated Design Methodology
R, L, CEctraction
De-featuring
R , CExtraction
ParameterExtraction
StatisticalReliability
CostDrivers
Time-ScaleSeparation
ParameterExtraction
OrderReduction
ModelDatabase
Design Process Control
Optimization analysis modeling
Algebraic LumpedParams.Finite
Elements
Electro-magnetics
Solid-StatePhysics
Solid BodyGeometry
Thermo-dynamics
StructuralMechanics
Physicsof Failure
Manufact-uring
Circuits &Topologies
Systems& Control
-
SoC & SoP Technologies for Power Electronics
NCTU 2005 Course Notes: SoC & SoP for Power Electronics 15
page 85
Integration of Power and Control Electronics
CPES: Integrated Power Electronic Module (IPEM)page 86
PIIPM50P12B004: Programmable Isolated IPMfrom International Rectifier
PIIPM5012B004: EconoPack 2 outline compatible
FEATURES:DSP (TMS320LF2406A) EmbeddedNPT IGBTs 50A, 1200V10us Short Circuit capabilitySquare RBSOALow Vce(on) (2.15Vtyp @50A, 25 C )Positive Vce(on) temperature coefficientGen III HexFred TechnologyLow diode VF (1.78Vtyp @50A, 2 5 C )Soft reverse recovery2m sensing resistors on all phase outputs and DCbus minus railT/C < 50ppm/CEmbedded flyback SMPS for floating stages (single 15Vdc @ 300mA input required)
TMS320LF2406A
40MIPS
DC Link Input
Power Module
Current sensecircuit
IR 2213 based gate driver
Encoder/Hall interface
JTAG interface
PI-IP M50P1 2B004
RS4
22
inte
rface
AC/DC motor
page 87
Challenges in SoC & SoP Design for Power Electronics
Power ManagementPower ManagementDigital Control TechniquesDigital Control TechniquesEMI Reduction Reductions EMI Reduction Reductions Low Power Design TechniquesLow Power Design Techniques
Development Platform for System Integration Design and Development Platform for System Integration Design and TestTest
page 88
References [1]
Recommended Readings[1] R. R. Tummala and V. K. Madisetti, "System on chip or system on package?" IEEE Design & Test of
Computers, vol. 16, no. 2 , pp. 48-56, April-June 1999. [2] Li-Rong Zheng, Meigen Shen, and H. Tenhunen, "System-on-chip or system-on-package: can we make an
accurate decision on system implementation in an early design phase?" IEEE Southwest Symposium on Mixed-Signal Design, pp. 1-4, 23-25 Feb. 2003.
[3] D. Samani, "Industry challenges for system-on-a-chip," Proceedings of the IEEE Interconnect Technology Conference, pp. 10 -12, 1-3 June 1998.
[4] G.A. Frantz, "System on a chip: a system perspective," IEEE International Symposium on VLSI Technology, Sy stems, and Applications, Proceedings of Technical Papers, pp. 1-5, 18-20 April 2001.
SoC Design[5] Michael Keating and Pierre Bricaud, Reuse Methodology Manual for System-on-A-Chip Designs, 2nd
Ed., 1999.SoC Verification[6] P. Rashinkar, P. Paterson, L. Singh, SYSTEM-ON-A-CHIP VERIFICATIONMETHODOLOGY AND
TECHNIQUES, Kluwer Academic Publishers, 2001.
page 89
References [2]
References for SoC Design, Implementation, & Verification[7] Steve Furber, ARM System-on-Chip Architecture, 2nd Ed., 2000. [8] K. K. Parhi, VLSI Digital Signal Processing Systems, 1999. [9] VSIA web site, www.vsi.org[10] Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, and Robert G. Meyer, Analysis and Design of Analog
Integrated Circuits, Fourth Edition, John Wiley & Sons, Inc., 2001. [11] M. Michael John and Sebastian Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997. [12] J. Rabaey, Digital Integrated Circuits, A design perspectiv e, Prentice Hall 1996[13] N. Weste et al., Principles of CMOS VLSI Design, Addison Wesley, 1985-96[14] A. Chandrakasan et al: Design of High Perf ormance Microprocessor Circuits, IEEE Press 2001[15] Vinod Kumar Khanna, IGBT: Theory and Design, IEEE Press and Wiley-Interscience, 2003. [16] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design,
John Wiley & Sons, 3rd Edition, 2003.
page 90
References [3]
VHDL[17] , , VHDL, , 2003. [18] , , , SoC VHDL, , 2004. [19] D. Perry, VHDL, 3rd Edition, McGraw-Hill, 1998. [20] J. R. Armstrong and F.G. Gray VHDL Design Representation and Sy nthesis,[21] Himanshu Bhatnagar, Advanced ASIC Chip Synthesis: Using Sy nopsys Design Compiler, Physical
Compiler, and Primetime,[22] Digital Systems Design with VHDL and Synthesis - An Integrated Approach, Chang [23] P. J. Ashenden, The Students Guide to VHDL,