SoC Final ProjectSoC Final Project--JPEG EncoderJPEG Encoder

Team 1Team 1

D90522024D90522024 劉志鵬劉志鵬R91522803 R91522803 鍾書耘鍾書耘R91522810 R91522810 張明輝張明輝

OutlineOutline

Explain DCT for Explain DCT for MYIP.vMYIP.v• Lifting Scheme• BinDCTBinDCT• MYIP.vMYIP.v

HW / SW PartitionHW / SW Partition Modify ProgramModify Program HW / SWHW / SW 1D_DCT1D_DCT Compressed Image FileCompressed Image File ConclusionConclusion && Future workFuture work

Explain DCT for Explain DCT for MYIP.vMYIP.v

Lifting Scheme BinDCT MYIP.v

Lifting Scheme Predict ：使用一個 input

sample 去預測另一個，計算出剩餘值。

T0=X0-P ． X1 Update ：用剩餘值去

update 原先的 input sample 。

T1=X1+ U ． T0 Scaling ：調整 Predict

與 Update 後的輸出值。 Y0=K0 ． T0 Y1=K1 ． T1

[1]

Lifting Scheme

所有 Predict 與 Update 的步驟都是 2 冪次倒數的線性組合，只要加法與移位即可實做之。

在上圖中，不會找到 Scaling 這個步驟，因為 BinDCT 把這個步驟並到 JPEG 編碼流程的 Quantization 上，

BinDCTBinDCT The BinDCT is an

approximation of the DCT.

It works only with integer numbers.

its set of operations is restricted to sums and shifts.

the BinDCT algorithm is used and implemented in hardware through the Verilog HDL hardware description language.

[2]

BinDCTBinDCT

BinDCT algorithm uses a finite-state machinewith a reduced number of states. Thereby, a 9-state machine was achieved, with 8 computation states and one initialization state.

[2]

MYIP.vMYIP.v

MYIP.vMYIP.v

MYIP.vMYIP.v

HW / SW PartitionHW / SW Partition

Hardware

[3]

Modify ProgramModify Program

Before.cpp

1. delete “SW” DCT_1D function

2. call “HW” DCT_1D function (driver.cpp)

Modify ProgramModify Program

MYIP.v

HW / SWHW / SW 1D_DCT1D_DCT

Hardware Software

Compressed Image FileCompressed Image File

bmp(192KB) sw_jpeg(13.3KB) hw_jpeg(8.24KB)

ConclusionConclusion & Future & Future workwork

已成功的將助教所給的已成功的將助教所給的 codecode ，完整的，完整的實現出來，但對於其顯示之結果，仍有實現出來，但對於其顯示之結果，仍有相當值得存疑的部分，在書面報告中會相當值得存疑的部分，在書面報告中會針對此一部份特別列出加以討論分析。針對此一部份特別列出加以討論分析。

期望能在下週前，將期望能在下週前，將 ASICASIC 實驗中實驗中RGBtoYUVRGBtoYUV 硬體實現的部分，加入硬體實現的部分，加入final projectfinal project 中。中。

ReferenceReference

[1]http://access.ee.ntu.edu.tw/course/VLSI_SP_89second/student/Final_Project/R89921046_report.pdf[1]http://access.ee.ntu.edu.tw/course/VLSI_SP_89second/student/Final_Project/R89921046_report.pdf[2] [2] Gustavo André Hoffmann; Eric Ericson Fabris; Diogo Zandonai; Sergio Bampi, “The BinDCT processor”, UFRGS Federal Univ. – Microelectronics Group Caixa Postal 15064 91501-970 Porto Alegre, Brazil.[3] http://access.ee.ntu.edu.tw/course/SOC_LAB/index.html/ip_design.zip