snooping based cache coherence protocol · multiprocessor cache coherence a read by a processor p...
TRANSCRIPT
![Page 1: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/1.jpg)
M4 – Parallelism
Snooping based Cache Coherence Protocol
![Page 2: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/2.jpg)
Outline
● Parallelism● Flynn’s classification● Vector Processing
– Subword Parallelism
● Symmetric Multiprocessors, Distributed Memory Machines– Shared Memory Multiprocessing, Message Passing
● Synchronization Primitives– Locks, LL-SC
● Cache coherence
![Page 3: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/3.jpg)
Cache Coherence
![Page 4: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/4.jpg)
Shared Memory vs. Distributed Memory
PP
CC
Main MemoryMain Memory
PP
CC
PP
CC
PP
CC
PP
MM
InterconnectInterconnect
PP
MM
PP
MM
PP
MM
![Page 5: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/5.jpg)
Multiprocessor Cache Coherence
CPU ACPU A CPU BCPU B
MemoryMemory
![Page 6: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/6.jpg)
Multiprocessor Cache Coherence
![Page 7: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/7.jpg)
Multiprocessor Cache Coherence
![Page 8: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/8.jpg)
Multiprocessor Cache Coherence
![Page 9: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/9.jpg)
Multiprocessor Cache Coherence
![Page 10: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/10.jpg)
Multiprocessor Cache Coherence
![Page 11: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/11.jpg)
Multiprocessor Cache Coherence
![Page 12: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/12.jpg)
Multiprocessor Cache Coherence
![Page 13: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/13.jpg)
Multiprocessor Cache Coherence
![Page 14: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/14.jpg)
Multiprocessor Cache Coherence
![Page 15: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/15.jpg)
Multiprocessor Cache Coherence
CPU B reads X
![Page 16: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/16.jpg)
Multiprocessor Cache Coherence
CPU B reads X Return which value to CPU B?
Return which value to CPU B?
![Page 17: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/17.jpg)
Cache Coherence● Coherence
– Which value to return on a read
![Page 18: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/18.jpg)
Cache Coherence● Coherence
– Which value to return on a read
● A memory system is coherent if:–
![Page 19: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/19.jpg)
Cache Coherence● Coherence
– Which value to return on a read
● A memory system is coherent if:– Write Propagation
●
– Write Serialization●
![Page 20: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/20.jpg)
Cache Coherence● Coherence
– Which value to return on a read
● A memory system is coherent if:– Write Propagation
● A write is visible after a sufficient time lapse
– Write Serialization●
![Page 21: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/21.jpg)
Cache Coherence● Coherence
– Which value to return on a read
● A memory system is coherent if:– Write Propagation
● A write is visible after a sufficient time lapse
– Write Serialization● All writes to a location are seen by every processor in the
same order
![Page 22: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/22.jpg)
Cache Coherence● Directory based protocols
–
● Snooping protocols–
–
![Page 23: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/23.jpg)
Cache Coherence● Directory based protocols
– Sharing status maintained in a directory
● Snooping protocols–
–
![Page 24: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/24.jpg)
Cache Coherence● Directory based protocols
– Sharing status maintained in a directory
● Snooping protocols– Sharing status is stored in the cache controller
– Cache controller snoops broadcast medium
![Page 25: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/25.jpg)
Cache Coherence● Write Invalidate protocols
–
● Write Update protocols–
![Page 26: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/26.jpg)
Cache Coherence● Write Invalidate protocols
– Invalidates other processors' copies on a write
● Write Update protocols–
![Page 27: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/27.jpg)
Cache Coherence● Write Invalidate protocols
– Invalidates other processors' copies on a write
● Write Update protocols– Updates all data copies on a write
![Page 28: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/28.jpg)
Cache Coherence● Sharing Status
– Invalid (I)
– Shared (S) (or Clean)
– Modified (M) (or Dirty)
![Page 29: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/29.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
![Page 30: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/30.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
![Page 31: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/31.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
Cache Miss
![Page 32: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/32.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
Cache Miss
Cache Miss Cache Miss
![Page 33: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/33.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
Cache Miss
Cache Miss Cache Miss
Cache Miss
![Page 34: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/34.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
![Page 35: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/35.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
![Page 36: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/36.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
CPU A reads XCPU A reads X
SharedShared
![Page 37: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/37.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
![Page 38: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/38.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
![Page 39: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/39.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
Cache Miss
![Page 40: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/40.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
Cache Miss
Cache Miss
![Page 41: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/41.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
Cache Miss
Cache Miss
Cache Miss
![Page 42: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/42.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
![Page 43: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/43.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared
CPU B reads XCPU B reads X
SharedShared
![Page 44: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/44.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
![Page 45: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/45.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
CPU A writes XCPU A writes X
![Page 46: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/46.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
CPU A writes XCPU A writes X
Write Invalidate X
![Page 47: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/47.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
CPU A writes XCPU A writes X
Write Invalidate X
Write Invalidate X Write Invalidate X
![Page 48: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/48.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
CPU A writes XCPU A writes X
Write Invalidate X
Write Invalidate X Write Invalidate X
![Page 49: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/49.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared InvalidInvalid
CPU A writes XCPU A writes X
Write Invalidate X
Write Invalidate X Write Invalidate X
![Page 50: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/50.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared InvalidInvalid
CPU A writes XCPU A writes X
![Page 51: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/51.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
CPU A writes XCPU A writes X
![Page 52: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/52.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
![Page 53: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/53.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
CPU B reads XCPU B reads X
![Page 54: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/54.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
CPU B reads XCPU B reads X
Cache Miss
Cache Miss
![Page 55: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/55.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
CPU B reads XCPU B reads X
Write Back
![Page 56: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/56.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
ModifiedModified InvalidInvalid
CPU B reads XCPU B reads X
![Page 57: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/57.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared InvalidInvalid
CPU B reads XCPU B reads X
![Page 58: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/58.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared InvalidInvalid
CPU B reads XCPU B reads X
![Page 59: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/59.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared InvalidInvalid
CPU B reads XCPU B reads X
![Page 60: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/60.jpg)
SMP - Write Invalidate
CPU ACPU A CPU BCPU B
MemoryMemory
SharedShared SharedShared
CPU B reads XCPU B reads X
![Page 61: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/61.jpg)
![Page 62: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/62.jpg)
Slides Contents
● Rajeev Balasubramonian, CS6810, University of Utah.
●
![Page 63: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/63.jpg)
Extra
![Page 64: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/64.jpg)
Shared Memory vs. Message Passing● Shared Memory Machine: processors share
the same physical address space– Implicit Communication, Hardware controlled
cache coherence
● Message Passing Machine– Explicit communication – programmed
– No cache coherence (simpler hardware)
– Message passing libraries: MPI
PP
CC
Main MemoryMain Memory
PP
CC
PP
CC
PP
CC
PP
MM
InterconnectInterconnect
PP
MM
PP
MM
PP
MM
![Page 65: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/65.jpg)
Cache Coherence● Consistency
– When should a written value be available to read
– Memory Consistency Models
● Coherence– Which value to return on a read
● A memory system is coherent if:– Write Propagation
● A write is visible after a sufficient time lapse
– Write Serialization● All writes to a location are seen by every processor in the
same order
![Page 66: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/66.jpg)
Multiprocessor Cache Coherence
● A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P.
● A read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses.
● Writes to the same location are serialized; that is, two writes to the same location by any two processors are seen in the same order by all processors.
![Page 67: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/67.jpg)
Write Invalidate Coherence Protocol
Writeback / WritethroughEnforcing write serialization
• Bus Arbitration
Tag Contention, Duplication
![Page 68: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/68.jpg)
SMP Cache Coherence
● MSI Protocol● MESI Protocol
– Exclusive state: No invalidate messages on writes.
– Intel i7 uses MESIF
● MOESI Protocol– Owned state: Only valid copy in the system. Main
memory copy is stale.
– Owner supplies data on a miss.
![Page 69: Snooping based Cache Coherence Protocol · Multiprocessor Cache Coherence A read by a processor P to a location X that follows a write by P to X, with no writes of X by another processor](https://reader033.vdocuments.site/reader033/viewer/2022050208/5f5adf9456f4044bbf712bde/html5/thumbnails/69.jpg)
SMP Example
ProcessorA
Caches
ProcessorB
Caches
ProcessorC
Caches
ProcessorD
Caches
Main Memory I/O System
A: Rd XB: Rd XC: Rd XA: Wr XA: Wr XC: Wr XB: Rd XA: Rd XA: Rd YB: Wr XB: Rd YB: Wr XB: Wr Y