smarresearch full featured hart modem ht3012 … · intrinsic safety configuration tools...

©Smar Research Corporation 1 HT3012DS - 0802

HART®

Fieldbus Profibus Intrinsic Safety Configuration Tools Semiconductors Training Custom Design

SmarResearch TechnologySource

Features

• Integrates the SRC HT2012 HART Modem core: • Operates at the Bell 202 Standard Forward Bit Rate

(1200 bits/second) • 1200 Hz and 2200 Hz Bell 202 Shift Frequencies • Superior Carrier Detect • Frequency Shift Keying (FSK) • 1200 Baud Transmit and Receive Modulation • Optimized for Intrinsically Safe Applications

• LCD driver for up to a 160-segment display • LCD can be oriented in multiple positions with the use of

automatic orientation detection and segment reorganization

• 15-bit D/A converter with an approximate resolution of 0.5uA per bit

• Floating-Point Coprocessor to significantly increase performance

• Compatible with Motorola and Intel buses • Engineering support services available for development of

software source code and PCB designs • Simplifies design • Shortens development schedule • Reduces part count • Lowers ownership and manufacturing costs

Full Featured HART Modem HT3012

Datasheet

Visit the SmarResearch technology center at: www.smarresearch.com


The SmarResearch HT3012 is a single chip solution that combines a HART Modem, an LCD Driver, a D/A Converter, and a Floating-Point Coprocessor in a single unit.

By combining these functions in a single chip, The HT3012 results in a variety of benefits, including lower ownership and manufacturing costs, better performance, simpler design and a quicker time to market.

Design requirements are minimized; the development schedule is

shortened resulting in a quicker time to market. PCB wiring is reduced, the component count for the final design is lowered, and the integrated 15 bit D/A Converter and Floating Point Coprocessor increases performance without additional expensive components.

The results of incorporating the HT3012 into the design of a HART instrument are greater reliability; lower overall cost of both design and manufacture, and faster time to market.

General Description

Figure 1 - Block Diagram

BUS CONTROL LOGIC MODULE

TIMING CONTROL

D/A CONVERTER

15 bits

LCD DRIVER

160 SEGMENTS

PW2

PW1

PW0

BPL1 (2:0)

BPL2 (2:0)

BPL3 (2:0)

BPL4 (2:0)

PIN1 (3:0)

SEG

CLK_19K2

HT

3012

Gen

eral

Des

crip

tio

n


Internal Register Operation

The HT3012 has a set of registers which are used for each of its modules.

Each register can be programmed to take full advantage of the HT3012’s capabilities.

Table 1 - Internal Registers

Note: All registers should be interpreted from MSB to LSB for consecutive addresses

Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB LSB

XX00 FLPACA3

FLPACA2

FLPACA1

FLPACA0

FLPACB3

FLPACB2

FLPACB1

FLPACB0

XX08 PPOS3 PPOS2 PPOS1 PPOS0 FLPEN OPCODE2 OPCODE1 OPCODE0

XX09 FLPRDY - - - - NAN INF ZERO

XX0A - DAVH

XX0B DAVL

XX0E OCD - - LTMSK HTEN DPLX - TXEN

XX0F DACLK1 DACLK0 FLPCLK1 FLPCLK0 HTCLK1 HTCLK0 LCDCLK1 LCDCLK0

XX10 DSEG19

DSEG18

DSEG2

DSEG1

XX23 DSEG0

XX24 LOADLCD

HT

3012

Inte

rnal

Reg

iste

r


Bus Control Logic Module

The CPU addresses the HT3012, which generates all chip select signals necessary for other modules. The HT3012 through its Bus Control Logic module, controls the interface among the CPU, the HT3012’s internal modules, and all external PROM or RAM memories. The regions are accessed and the chip select signals CSRAM, CSIO0, CSIO1, and CSROM are generated according to Table 2 - Memory Mapping Addressing.

The CSROM, CSRAM, and CSIO1 pins can generate chip select signals to external PROM, RAM and EEPROM memories, respectively. These pins generate external chip select signal for interfacing with external devices like memories or dedicated integrated circuits. In this case the HT3012 generates the LSB of address bus A [7:0].

The CSIO0 pin generates a chip select signal that allows a software application to access the HT3012’s internal memory registers. Every time an address between the range from $1100-$11FF is accessed the HT3012 generates an external signal through this pin to signal that its internal registers can be read or written to.

The CSIO0 should be connected to the CSIN pin as the CSIN input signal selects the access to the HT3012 internal modules.

The Bus Control Logic module can also be used when the user decides to

use another method to access external memories (via micro-controller I/O pins or external glue logic). This architecture will restrict the Bus Control Logic module to access only the HT3012 modules and their functionality. The user must provide the HT3012 internal module addresses via data bus (DB) while the CSIN pin is active low.

The HT3012 Internal Registers can be accessed by addressing any memory location between $XX00 and $XXFF. The MSB address byte of the Internal Registers can be positioned anywhere within the microprocessor memory. Each segment size is limited to 256 Bytes.

The pins called MODE and MUXON should be used for interfacing with different CPU types. They need to be configured to operate the hardware correctly.

The MODE pin should be connected to GND when the CPU is a Motorola type, resulting in a single pin for the R/W signal. The MODE pin should be connected to VCC when the CPU is an Intel type, resulting in two separate pins for the R/W signal.

The MUXON pin should be connected to VCC when the CPU multiplexes the low-order eight bits of the address with data. This pin should be connected to GND when the CPU does not have the low-order eight bits of the address multiplexed with data. A(7:0) then

Segment Range Pin Size (Bytes) External PROM $2000-$FFFF CSROM 56K External EEPROM $1200-$1FFF CSIO1 3.5k HT3012 Internal Registers $1100-$11FF CSIO0 256 Reserved (HC11 Internal Registers) $1000-$103F -- 256 External RAM $0200-$0FFF CSRAM 3.5K Reserved (HC11 Internal RAM) $0000-$01FF -- 512

Table 2 - Memory Mapping Addresses

HT

3012

Bu

s C

on

tro

l Lo

gic

Mo

du

le


This module is the primary time control system of the HT3012. It outputs four different timer subsystems. Each of those subsystems generates a programmed clock source for a specific module existing within the HT3012. The timer subsystem involves a register and control bits that can be configured by software to set the most appropriate clock rate. This timer and its subsystems provide programmable clock rates for the Digital-to-Analog Converter, Floating-Point Unit, HART® Modem and LCD Driver modules. Each module has an independent set of clock rates, which are described later.

The source-input clock comes from the same source clock used for the CPU and an oscillator can be used from a minimum of 460 kHz to a maximum of 3,68 MHz. (See the “HT3012 AND MICROCONTROLLER ENVIRONMENT” section for details)

Programming and flexibility are

achieved via software, which accesses the memory-mapped register address of this module. When nDA, nFLP, nHART and nLCD have been properly chosen, the clock divider factor divides the unique input clock (typically 1.8432 MHz) by a factor n, which is selected by the software. Each timer subsystem supplies a programmed clock source output (see Figure 2).

Timing Control Module

Figure 2 - Timing Control Module

HARTCLK

CLK/nDAV

CLK/nLCD

Clock Divider 1

Clock Divider 2

CLK/nFLP

Clock Divider 3

Clock Divider 4

CLK

FLPCLK

D/ACLK

LCDCLK

C L K S E T

160 k Hz

CLK/nHART

HT

3012

Tim

ing

Co

ntr

ol M

od

ule


Clock Setup Register– CLKSET

The central element of the main timer system within the HT3012 is an 8-bit read/write register which defines the clock rates for four different modules.

Each clock source can be selected by writing a pre-scale factor described by two bits.

7 6 5 4 3 2 1 0

DACK1 DACK0 FLPCLK1 FLPCLK0 HTCLK1 HTCLK0 LCDCLK1 LCDCLK0

0 0 0 0 0 0 0 0 RESET CLKSET $XX0F

DACLK[1:0] – DIGITAL-TO-ANALOG CONVERTER CLOCK RATE SELECTS

These bits select the clock source rate for the Digital to Analog Converter module. Table 4 - D/A, FLP and HART® Clock Rate Encoding, defines the possible clock rates. Note that MSB and LSB are DACLK1 and DACLK0 respectively. These bits form the pre-scale factor for the timer sub-system of the Digital to Analog Converter Module. The CLK Output column shows the clock rate output results for each combination selected.

For optimum operation use a clock of 460 kHz for the D/A Converter. The clock input should be divided by a factor that provides an output clock of 460 kHz for this module. As can be seen in the table below (Table 4 - D/A, FLP and HART® Clock Rate Encoding), the pre-scale factor bits DACLK1 and DACLK0 are both selected as (00H), resulting in an output clock divided by four (4).

FLPCLK[1:0] – FLOATING-POINT UNIT CLOCK RATE SELECTS

These bits select the clock source rate for the Floating-Point Unit. Table 4 - D/A, FLP and HART® Clock Rate Encoding defines the possible clock rates.

Note: MSB and LSB are FLPCLK1 and FLPCLK0 respectively. These bits form the pre-scale factor for the timer sub-system of the Floating-Point Unit. The CLK Output column shows the clock rate output results for each combination selected. A maximum clock of 3.68 MHz can be used for the Floating Point Unit. The pre-scale factor bits FLPCLK1 and FLPCLK0 are both selected as (00H), resulting in an output clock divided by four (4).

Table 4 - D/A, FLP, and HART Clock Rate Encoding

Clock Input divided by (nDA, nFLP, nHART)

Pre-Scale Factor

CLK Output (kHz) Input Clock @ 1.8432 MHz

MSB LSB

4 0 0 460.800

2 0 1 921.600

1 1 0 1.8432

8 1 1 230.400

D/A, FLP and HART Clock Rate Encoding Table

HT

3012

Tim

ing

Co

ntr

ol M

od

ule


HTCLK[1:0] – HART® MODEM UNIT CLOCK RATE SELECTS

These bits select the clock source rate for the HART® Modem Unit. Table 4 - D/A, FLP and HART ® Clock Rate Encoding defines the possible clock rates. MSB and LSB are HTCLK1 and HTCLK0, respectively. These bits form the pre-scale factor for the timer sub-system of the HART® Modem Unit. The CLK Output column shows the clock rate output results for each combination selected.

The HART® Modem Unit requires

a fixed clock of 460 kHz to operate correctly. The input clock should be divided by a factor that provides an output clock of 460 kHz for this module. The pre-scale factor bits HTCLK1 and HTCLK0 are both selected as (00H), resulting with an output clock divided by four (4).

LCDCLK[1:0] – LCD DRIVER CLOCK RATE SELECTS

These bits select the clock source rate for the LCD Driver Clock Unit. Table 5 - LCD Driver Clock Rate Encoding below defines the possible clock rates.

The CLK Output column shows the

clock rate output results for each combination selected. The data is actually displayed as the CLK Output rate divided by four as there are four back-plane signals. Please refer to the LCD Driver Module for more details.

Note: MSB and LSB are LCDCLK1 and

LCDCLK0 respectively. These bits form the pre-scale factor for the timer sub-system of the LCD Driver Clock Unit.

Table 5 - LCD Driver Clock

Clock Input divided by (nLCD)

Pre-Scale Factor

CLK Output (Hz)

Actual Data Rate at Display (Hz)

MSB LSB

4 0 0 225 56.25

2 0 1 450 112.5

1 1 0 900 225

8 1 1 112.5 28.125

LCD Driver Clock Rate Encoding Table

HT

3012

Tim

ing

Co

ntr

ol M

od

ule


Digital To Analog Converter Module

The Digital-to-Analog Converter module is a low speed 15-bit D/A converter that uses the three-phase PWM technique for conversion. The current output is a result of the sum of PW(2), PW(1) and PW(0) consecutively, providing ± ½ least significant bit (LSB) accuracy over the complete operating temperature range of -40 to +85 °C. The digital current value is provided as the input is loaded by the CPU through memory mapped register addresses. The resulting three outputs PW(2), PW(1) and PW(0) should be added together to be used in an analog output.

The CPU loads a digital value for

data conversion from a digital input to an analog output through software and memory-mapped register addresses. The three analog outputs PW(2), PW(1)

and PW(0) are components that are added to provide the actual analog signal. A conventional op-sum analog circuit can perform this addition easily. The Digital-to-Analog Converter’s source clock signal is generated by the main timer sub-system within the HT3012.A clock of 460 kHz should be used for optimum operation.

Conversion starts when the 15 bits

are written in the DAV register. The three analog outputs have an updated analog value available after 32 cycles of CPU after the digital value has been written in the register.

Figure 3 - Digital to Analog Converter Module

DIGITAL - TO - ANALOG Converter

@D/A CLK32

PW2

PW1

PW0

D/A CLK

M D A V

L D A V

HT

3012

Dig

ital

to

An

alo

g C

on

vert

er M

od

ule


Digital-to-Analog Converter Register – DAV All bits in this register may be read or written and all bits are cleared by reset.

DAV[14:8] – MOST SIGNIFICANT D/A BIT VALUES – MDAV This register stores the seven (Digital-to-Analog Converter Value) most significant bits of DAV.

DAV[7:0] – LEAST SIGNIFICANT D/A BIT VALUES - LDAV This register stores the eight (Digital-to-Analog Converter Value) least significant bits of DAV. Note: The Motorola notation is used for

addressing type: the MSB byte followed by the LSB byte for consecutive bytes of address.

7 6 5 4 3 2 1 0

- DAV14 DAV13 DAV12 DAV11 DAV10 DAV9 DAV8

0 0 0 0 0 0 0 0 RESET DAV $XX0A

7 6 5 4 3 2 1 0

DAV7 DAV6 DAV5 DAV4 DAV3 DAV2 DAV1 DAV0

0 0 0 0 0 0 0 0 RESET DAV $XX0B

HT

3012

Dig

ital

to

An

alo

g C

on

vert

er M

od

ule


HART Modem Unit

Description The HART® Modem Unit incorporates the core of the field proven Smar HT2012 HART® Modem, which implements FSK (frequency shift keying). It meets HART® physical layer requirements and operates at the Bell 202 Standard Forward Bit Rate (1200 bits/second). The HART® Modem Unit offers an excellent interface with the CPU since it requires fewer pins from the CPU. In addition, the CPU can use the memory map feature to access some of the HART® control signals. The HART® Modem Unit requires a fixed clock of 460 kHz to operate correctly; the input clock should be divided by a factor that provides an output clock of 460 kHz for this unit.

Function Blocks The HART® Modem Unit has four major function blocks: Clock and Timing, Demodulator, Modulator, and Carrier Detect. The bit rate is nominally 1200 bits per second and it uses shift frequencies of nominally 1200 Hz (digital one) and 2200 Hz (digital zero). This module has two inputs and four outputs, all through a register that stores control signals. The TXEN, HTEN and DPLX signals are described later in this section. The HART_CLK is generated at the Timing Module. Its default value is set to 460 kHz.

Figure 4 - HART Modem Module

HART CLK @ 480 kHz CLOCK

TIMING

MODULATOR

DEMODULATOR

CARRIER

ITXD OTXA

ORXD IRXA

OCD

CLK_19K2

TXEN

RESE

HT

3012

HA

RT

Mo

dem

Mo

du

le


Clock & Timing A digital input frequency of 460.8 kHz is accepted from the timer control module. This signal is used to generate several internal clocks. All circuit operations can be performed with a master clock frequency of 460.8 kHz, significantly lower than clock frequencies used in other single chip modems and resulting in far lower power requirements. Power consumption is further reduced by various sections of the modem being shut down (not clocked) when not in use. One internal clock at a nominal frequency of 19.2 kHz is brought to an output pin. This signal is available when the HART modem is enabled and can be used as clock source for any purpose through HTEN of the HART® Status register. Demodulator The Demodulator accepts an FSK signal at the IRXA input. The original modulating signal is reproduced at the ORXD output. Both the input and the output signals are digital. Digital data in NRZ form is accepted at the ITXD input. An FSK modulated signal is generated at the OTXA output. The input signal from the IRXA pin is a digital pulse train consisting of the FSK modulated square waves. The demodulated data stream is buffered at the ORXA pin as a digital output signal.

Maximum Demodulator Jitter: +/- 12% of one bit time Conditions: Input frequencies @ 1200 Hz +/-10 Hz; 2200 Hz +/- 20 Hz Clock frequency of 460.8 kHz +/- 0.1% Input (IRXA) asymmetry = 0

Modulator

The Modulator provides phase continuous modulation. The phase angle of the modulated signal is not affected when switching between shift frequencies. The incoming IRXA signal frequencies (1200 Hz to 2200 Hz range) activate the low Carrier Detect. Digital data in NRZ form is accepted at the ITXD input. AN FSK modulated signal is generated at the OTXA output. An important feature of the modulator is its preservation of the phase integrity of each frequency when switching between frequencies to accurately reconstruct the original modulating signal at the output of the demodulator. The clock/timing section generates timing and reference frequencies for the modulator. Output transitions are quantified as to when they can occur; limiting the maximum accumulated timing error to 12 microseconds, the period of the slower modulation frequency.

Modulator Output Frequency (at OTXA pin): 2194.3 Hz - Nominal high frequency 1196.9 Hz - Nominal low frequency Modulator output frequencies are proportional to the input clock frequency. Modulator Phase Continuity Error: Maximum +/- 10 degrees

HT

3012

HA

RT

Mo

dem

Mo

du

le


Carrier Detect

The carrier detect output is active low whenever a valid carrier tone between 1000 and 2575 Hz (inclusive) is detected. Detection occurs when timed transitions remain within the band of the 1200 and 2200 Hz periods for 9 to 15 milliseconds. Loss of carrier for 1 millisecond or more causes the carrier detect line to go inactive high.

Incoming signal frequencies in the

1200 Hz to 2200 Hz range activate the low carrier detect. If several successive time measurements fall within specific limits as interval times between input transitions are measured, carrier detect is indicated, and carrier detect output is asserted. If, after the carrier has been detected, the measured interval time falls outside these limits for a period of time (need to specify time period), carrier detect output is unasserted.

Time from Carrier Input to Carrier Detect:

The time from the start of a valid carrier signal at IRXA until OCD goes to logical low (0). 0.9 milliseconds (minimum) 1.44 milliseconds (maximum)

Conditions:

Clock frequency of 460.8 kHz +/- 0.1% Max. input (IRXA) asymmetry = 5.0%

Time from Carrier Loss to Carrier Undetected:

The time to lose a valid carrier signal at IRXA before OCD goes to a logical high (1). 1.048 milliseconds (maximum)

Carrier Detect Frequency Range:

The range of frequencies applied at IRXA over which OCD must go low (logical 0) 1000 Hz to 2575 Hz.

HART® Status Register – HTSTAT

This register can be both read and written. For the HART® Modem to work properly the least significant valid bits should be written to their specific values. Some of these bits need only be

written once on reset, particularly the bit 0. The TXEN bit should be written regularly as the HART® device either listens or speaks to the communication line.

7 6 5 4 3 2 1 0

OCD - - LTMSK HTEN DPLX - TXEN

0 0 0 0 0 0 0 0 RESET HSTAT $XXOE

HT

3012

HA

RT

Mo

dem

Mo

du

le


OCD – Output Carrier Detect Bit

This bit indicates if the carrier is present on the communication line.

0 = Carrier not detected 1 = Carrier detected

HTEN – HART Communications Enable

To minimize power consumption the HART modem can be deactivated by selecting this bit. This capability provides added ability to control power, and is particularly valuable when devices are subject to a surge of power at start-up or are delivered without HART capability.

The CLK19K2 output pin is a general-purpose clock at a nominal frequency of 19.2 KHz. It is disabled with the HTEN bit is set to disabled.

0 = Disable the HART® Modem 1 = Enable the HART® Modem

LTMSK – Latch Mask Enable Bit

When this bit is (1) the least significant bits of the address are not being multiplexed with the data bus Latches on the address and data lines to external memories are disabled. No external capture data and address information is needed during program execution as internal memory is being used. This feature is used to minimize power consumption when an internal area of memory is being accessed.

0 =Normal operation 1 = Special operation

DPLX – Half/Full Duplex Select Bit

While The HART® protocol requires half-duplex capability, full-duplex mode may be selected. To reduce the operating current when the HT3012 modem operates as a half-duplex the transmitting circuits are shut down when receiving and the receiving circuits are shut down when transmitting.

0 = Half duplex 1 = Full duplex

TXEN – Modulator/Demodulator Select Bit

The HT2012 modulates a signal when the demodulator is off and demodulates a signal with the modulator is off. This conserves energy by powering down the source clock of one side based on activity, and lowers power consumption when the communication line is active.

0 = Enables the HART® Modem’s demodulation mode

1 = Enables the HART® Modem’s modulation mode

HART protocol specifications designate half-duplex mode as the normal way to use the HT3012. The physical layer interface is determined by a set of transmit and receive primitives. At any given instant the interface may undertake either a transmit or receive primitive sequence, but not both simultaneously (i.e. the interface is half- duplex). The transmit/receive state machine controls the modulation/demodulation mode.

There are applications where a full-duplex mode is more useful such as a Master protocol interface implementation , when the Master is transmitting a frame and its echoed frame can be listened and received for later handling to check if the Master’s hardware interface is working properly.

In full-duplex mode (when the DPLX bit is (1)), the HT3012 is always listening from the IRXA line input and the TXEN bit should be set to (1) to modulate the line OTXA output. If the TXEN bit is zero the HT3012 will not be capable to transmit anything; just listen to the network. When the HT3012 is working on full-duplex mode, the modulation mode should be selected (TXEN bit = (1)).

HT

3012

HA

RT

Mo

dem

Mo

du

le


All interface lines are digital and can directly connect to CMOS or TTL level components. To use the HT3012 chip two interfaces must be provided; one to the CPU and a second to the medium.

A typical application will send

transmitted data over a signal medium and receive data over the same medium in a half duplex mode. The signal medium interface will vary and in most cases will contain an input band-pass filter as well as an output wave-shaping filter. The input filter consists of a band-pass filter and a square wave shaper to regenerate the digital square waves to the HT3012.

The square wave shaper is a

comparator that functions as a zero cross detector. The comparator has a threshold set at half signal level, squaring the input signals and regenerating the sharp edges required by digital circuits. The timing characteristics of the originally transmitted signal are preserved for accurate decoding of Manchester data.

The band-pass filter is used to

reduce induced noise on the received signal. The pass band starts at around 1200 Hz and cuts off at around 2200 Hz . The band-pass is needed to smooth

sharp transitions and eliminate high frequency components of the input signal.

Depending on the signal medium and transmit signal levels front-end gain might be required before applying the signal to the band-pass filter. The output wave shaping filter functions as a current to voltage modulator and smoothes transition edges to minimize spurious frequencies and harmonics over the transmission lines. This helps eliminate false triggers at the remote receiver due to noise centered on the transition threshold. A simple integrator can be used, depending on the medium interface. In some applications an output filter is not required if the transmission medium can accept square waves directly without inducing or radiating unacceptable levels of noise. An important characteristic of both filter designs is that they exhibit relatively constant phase delays over the operating bandwidth. This helps assure accurate timing characteristics for the regenerated demodulated signal.

Figures 5 & 6 show a typical Input

Band pass Filter and a typical Output Wave Shape Filter respectively.

Medium Interfacing

HT

3012

Med

ium

Inte

rfac

ing


Figure 6 - Typical Output Wave Shape Filter

Figure 5 - Typical Input Bandpass Filter

2U2

TLC27 U4

HT

3012

Med

ium

Inte

rfac

ing


The HT3012 has an integrated a display driver to minimize the cost associated with fabricating displays while still benefiting from using conventional LCD technologies. The LCD Module is capable of driving a three-ledger 160-segment display, and has the added capability of detecting the display position and reorganizing the data segments appropriately.

Displaying any information

requires accessing the right segments distributed all over the four back-planes totaling up to 160-bit of display data. Each segment is accessed via memory map addressing. The user only needs to set a specific combination of display data segments to generate a piece of information on the LCD (See Figure 7).

The CPU buffers 20 bytes (Seg 0

- Seg 19) to the HT3012 This data is stored as a buffer in the 160-bit register

of the module. These bits carry all the on/off states of each segment on the LCD. The LCD module then carries this information; transferring it to the 160-bit latch register. Those bits will be latched for the segment decoder unit to decode them in four sets of 48 available output pins to drive the LCD segments. (Note there are an additional 32 pins that are not used but are necessary for the implementation of the free rotate mechanism). The clocking source provides the serialization of data which is generated by the main timer module. (refer to the Timer Control Module Section to determine the correct clock rate to select) The clock source feeds the segment selector, which decodes all segments ,detects the location of pin 1, and reorganizes all of the segments in the right position.

LCD Driver Module

Figure 7 - LCD Module

HT

3012

LC

D D

rive

r M

od

ule


Control Register – (CNTRL)

All bits in this register may be read and some of them can be written. PPOS[3:0] stores the information regarding the position of the LCD Pin1 and are read only. This information is generated each time by the LCD driver and by the back plane generator module. Pin 1 orientation is changed each time the user changes the LCD display enabling detection of the LCD display position. Each PPOS bit indicates

a specific location for pin 1 when its bit is read as (1). They are exclusive bits, with only four positions available. The LCD display can be rotated in ninety degree (90°) steps (see Table 6). To read only the PPOS bits the user should use a mask for the four most significant bits. The four least significant bits are used only to control the Floating-Point Unit.

7 6 5 4 3 2 1 0

PPOS3 PPOS2 PPOS1 PPOS0 FLPEN OPCODE2 OPCODE1 OPCODE0

X X X X 0 0 0 0 RESET CNTRL $XX08

PPOS[3:0] – LCD Pin1 Position

Table 6 - LCD Pin 1 X HT3012 Position

Parameter Symbol Min Max Unit Notes

LC Supply Voltage (Referenced to GND) VLC -0.5 7.0 V

CD Supply Voltage (Referenced to GND) VCD -0.5 7.0 V

CA Supply Voltage (Referenced to GNDA) VCCA -0.5 V

Input Voltage (Referenced to GND) Vin -0.5 VCC* + 1.0 V

Output Voltage (Referenced to GND) Vout -0.25 VCC* + 0.5 V

Input Current, per Pin Iin µA

Output Current, per Pin Iout µA

LC Supply Current, VLC and GND Pins ILC µA

CD Supply Current, VCD and GND Pins ICD µA

CA Supply Current, VCCA and GNDA Pins ICCA µA

Storage Temperature Tstg -55 150 °C

Lead Temperature TL - 300 °C 10 seconds

Clock Frequence fmax DC MHz

HT

3012

LC

D D

rive

r M

od

ule


LCD Segments Register – DSEG

The DSEG register is a write only register. It is comprised of a set of twenty 8-bit registers, which can be accessed from the $XX10 to $XX24 range of addresses. All twenty registers have the same structure. The following describes only the most and least

significant registers, respectively. To display any information on the LCD, it is necessary to select the segments that will be on and those that will be off by writing ones and zeroes in the appropriate registers.

7 6 5 4 3 2 1 0

SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0

0 0 0 0 0 0 0 0 RESET DSEG20 $XX10

SEG[7:0] – Data Segment Register This register stores the eight most significant bits of the data to be sent to the display.

7 6 5 4 3 2 1 0

SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153 SEG152

0 0 0 0 0 0 0 0 RESET DSEG0

SEG[159:152] – Data Segment Register This register stores the eight least significant bits of data sent to the display.

Load Display - LOADLCD This register is write -only and it is responsible for latching the data to the display. The LCD Driver Module assumes that whenever data is written to this register, all other registers already have their data stored. The LCD display should be loaded by

writing from the MSB registers to the LSB registers and then writing a dummy byte in the LOADLCD register. This operation acts as a trigger for the 160-bit latch register to hold all bits latched.

7 6 5 4 3 2 1 0

XX XX XX XX XX XX XX XX

0 0 0 0 0 0 0 0 RESET LOADLCD $XX24

HT

3012

LC

D D

rive

r M

od

ule


The HT3012 incorporates an LCD driver for up to a 160-segment display. There are 160 bits to interface with the LCD. The CPU accesses these bits via 20 byte registers ($XX10-$XX23). The HT3012 multiplexes these bits since it has only 48 pins available for the electrical connection to the LCD, and uses the four back-planes to scan all 160-bits. Each back plane is alternately activated, displaying the segments related to it. Each of the four (4) back-planes is sampled at the LCD Clock rate divided by four. For example, if the LCDCLK output signal is 225 Hz, the data will be refreshed at a frequency of 56.25 Hz.

The HT3012 can auto-detect a

reference pin (pin 1) from the LCD electronic circuit. This automatic

orientation detection and segment reorganization feature allows the LCD to be oriented in multiple positions (0°, 90°, 180° and 270°) on the fly.

The following four (4) figures show

the relation of the 160 bits and the 160 LCD segments in each of the four possible 90° positions. The information for each possible 90° position is noted within one of the four columns radiating out from the HT3012. Each of these columns contains a reference (P), which indicates the location of pin 1. Note that each figure shows only the 40 segments corresponding to one back plane. All four figures need to be referenced to determine how all 160 segments are composed and accessed by the available 40 pins.

HT

3012

LC

D D

rive

r M

od

ule


Figure 8 - LCD and Segment Mapping Back-Plane I

HT

3012

LC

D D

rive

r M

od

ule


Figure 9 - LCD and Segment Mapping Back-Plane II H

T30

12 L

CD

Dri

ver

Mo

du

le


Figure 10 - LCD and Segment Mapping Back-Plane III

HT

3012

LC

D D

rive

r M

od

ule


Figure 11 - LCD and Segment Mapping Back-Plane IV

HT

3012

LC

D D

rive

r M

od

ule


Figure 12 - Floating Point Module

Floating Point Coprocessor

There are several advanced 8-bit micro-controllers in the market with low power consumption and the resulting cost-effectiveness. The HART protocol calls for all HART® devices to support the IEEE 754 standard for floating point operations. The floating-point operations are always present on all internal calculations performed by these devices, such as polynomial compensation, linearization, strapping-table interpolation, measurement and calibration methods calculations.

Even though they are 8-bit micro-

controllers, these popular CPUs perform 32-bit floating-point calculation by using one of the various existing mathematical IEEE 754 libraries available for each type of microcontroller. Coding in Assembler and/or C language accomplishes this code implementation by incorporating many different mathematical functions in the application program. These routines

contain extensive code due to a lack of built-in support by the CPU. All internal 16-bit and 8-bit registers need substantial external code to perform 32-bit float operations such as addition, subtraction, multiply, division, floating-point to integer conversion and integer to floating-point conversion as well. The result is poor floating-point operation performance and the degradation of the device’s overall performance.

The floating-point unit within the HT3012 was designed to compensate for these constraints and requirements. to the HT3012 assumes responsibility for all existing floating-point applications of CPU. This increases the processing speed of any calculation, which is floating-point intensive, and releases the CPU to perform other tasks, improving the performance of the entire system.

FLOATING POINT CONTROL MODULE

Operand, Operation

START

FLP CLK Operand, Operation

FLOATING POINT UNIT

NAN, INF, ZERO FLP_RES(31:0)

FLP RDY

HT

3012

Flo

atin

g P

oin

t C

op

roce

sso

r


The CPU executes a floating-point operation on the fly by accessing the Floating-Point Controller memory mapped register addresses. The Floating-Point Controller (FPC) Module in the HT3012 controls the Floating -Point Unit (FPU) via a two-way handshaking protocol using the FLPRDY and START signals ( Figure 12 - Floating Point Module Diagram). Each floating-point operation is initiated by the signaling of the START signal generated by the CPU which initiates the FPU computation on behalf of the CPU. FLPRDY signals the cpu when the computation has been completed. The FPu recognizes this signal and goes into a sleep state until the next operation. This approach reduces power consumption and

maximizes overall cost effectiveness. The Floating-Point Unit is the heart

of Floating-Point Module. Basically, it is an arithmetic calculator based on the 32-bit IEEE 754 standard for floating-point number representation, and can be set to perform all four basic operations (addition, subtraction, division and multiplication). It is also capable of performing 32-bit number conversion operations: floating-point numbers to integers and integers to numbers. The Floating Point Unit is designed to operate with a maximum clock of 5 MHz. (The maximum input clock allowed for the Timing Control Module is 3.68 MHz)

Control Register – CNTRL

This register, may be read or written at any time and is used to control the operation of the Floating-Point Module Unit. It configures the type of mathematical operation required and enable/disables the FPU.

The three least significant bits, OPCODE[2:0] encode the eight possible FPU operations( Table 7 - Floating Point Opcode Operations describes each operation available). Bit 3 (FLPEN) enable/disables the FPU. The FPU starts its computation whenever a written event occurs in this bit. A logic “0” on FLPEN resets the FPU, whereas a logic “1” requests FPU

to compute the operation encoded on OPCODE[2:0] bits.

A CLRA operation should be

performed sfter the CPU reset.This clears the FPU internal control states to its operational state.

The four most significant bits are

used for controlling the LCD Driver. This register has double functionality acting on the LCD and Floating-Point Modules. When configuring the FPU these specific bits must be manipulated. A mask on the four most significant will keep the bits unchanged.

7 6 5 4 3 2 1 0

PPOS3 PPOS2 PPOS1 PPOS0 FLPEN OPCODE2 OPCODE1 OPCODE0

0 0 0 0 0 0 0 0 RESET CNTRL $XX08

HT

3012

Flo

atin

g P

oin

t C

op

roce

sso

r


FLPEN – Floating Point Operation Enable

This bit enables the Floating -Point Unit and initiates its computation. The FPU starts its computation whenever a written event occurs in this bit. A logic “0” on FLPEN resets the FPU; a Logic “1” requests the FPU to compute the operation encoded on OPCODE [2:0] bits after the Floating-Point Accumulators have been loaded with the operand and operator respectively. To maximize the power performance of the FPU, this bit disables automatically after the result is available. OPCODE[2:0] – Floating Point

Coprocessor Operation Code Select

There are the eight operations available on the FPU. (Table 7 - Floating Point Opcode Operations) The operation is selected by choosing a combination of these three bits encoding the possible operations to be performed by the Floating-Point Coprocessor as follows :

Table 7 - Floating Point Opcode Operations

Floating-Point Status Register – FSTAT

Each time an operation is executed it can be monitored by reading the contents of the FSTAT register. This

register indicates by status if the result is ready and available for reading and if some exception occurred during the calculation.

7 6 5 4 3 2 1 0

FLPRDY - - - - NAN INF ZER

0 0 0 0 0 0 0 0 RESET FSTAT $XX0A

OPCODE [ 2:0 ] OPERATION DESCRIPTION

000 NOP Null Operation

001 SUB Subtraction

010 ADD Addition

011 MUL Multiplication

100 DIV Division

101 FLT2INT Floating-Point-to 32 bit signed Integer Conversion

110 INT2FLT 32 bit signed Integer-to-Floating-Point Conversion

111 CLRA Clear the contents of Accumulator A

HT

3012

Flo

atin

g P

oin

t C

op

roce

sso

r


FLPRDY – Floating Point Unit Ready Flag

This MSB bit indicates when the FPU is executing an operation or is ready for another one. The FPU sets this bit equal to 0 to indicate that that an operation is being executed. After the necessary cycles of operation the result of the computation become available on Accumulator A of the FPU. This is indicated by a transition from low to high in this bit. NAN – Floating Point Unit Not-A-Number Flag

This bit represents a Not-a-Number result from the Floating-Point Coprocessor. This flag will be asserted upon an invalid operation according to the IEEE-754 standard. INF –Floating Point Unit Overflow

Flag

This bit represents an infinite result from the Floating-Point Unit. This flag will be asserted upon an overflow operation or a division by zero operation. ZER –Floating Point Unit Underflow Flag

This bit represents a zero result from the Floating-Point Unit. This flag will be asserted upon an underflow operation.

Floating-Point Accumulator Registers

Each floating-point number needs four bytes to represent a 32-bit IEEE Standard 754 number. The HT3012 has two accumulators, FLPACA and FLPACB. They are necessary for most of the floating-point operations, functioning respectively as Operand and Operator. The FPU always stores the result of any mathematical operation on the FLPACA accumulator without

changing the content of the FLPACB. It permits the optimization of the process by using the FPU, since the user can implement a multiple sequence of operations by loading only the Accumulator B and keeping the sub-results on the Accumulator A without saving them on auxiliary memory registers.

HT

3012

Flo

atin

g P

oin

t C

op

roce

sso

r


Floating-Point Accumulator A – FLPACA

This accumulator is a composition of four single byte registers, and is used for two purposes. It is both the Operand, and the FPU provides the result of each floating-point operation on this accumulator after completion of each operation.

For example, the operation A + B

= C should be manipulated as follows:

* The Operand A should be stored into the Accumulator A. * The Operator B should be stored into the Accumulator B. * The Result C will be available after completion into the Accumulator A. * The Operator B remains unchanged.

These four registers store the 32-bit Floating Point Unit operand A. The most significant byte (MSB) must be stored at $XX00, the second MSB at $XX01, etc.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET FLPACA3 $XX00

These eight bits store the most significant byte of the 32-bit Floating Point Unit operand A.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET FLPACA2 $XX01

These eight bits store the second most significant byte of the 32-bit Floating Point Unit operand A.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET FLPACA1 $XX02

These eight bits store the third most significant byte of the 32-bit Floating Point Unit operand A.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET FLPACA0 $XX03

These eight bits store the least significant byte of the 32-bit Floating Point Unit operand A.

HT

3012

Flo

atin

g P

oin

t U

nit


Floating Point Accumulator B (FLPACB)

These four registers store the 32-bit Floating Point Unit operand B. The

most significant byte (MSB) must be stored at $XX04, the second MSB at $XX05, etc.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET

These eight bits store the most significant byte of the 32-bit Floating Point Unit operand B.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET

These eight bits store the second most significant byte of the 32-bit Floating Point Unit operand B.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET

These eight bits store the third most significant byte of the 32-bit Floating Point Unit operand B.

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 RESET FLPACB0 $XX03

These eight bits store the least significant byte of the 32-bit Floating Point Unit operand B.

FLPACB1 $XX02

FLPACB2 $XX01

FLPACB3 $XX00

HT

3012

Flo

atin

g P

oin

t U

nit


Floating-Point Unit Performance

The Floating-Point Unit can compute up to eight different operations. (See Table 8 for the performance for each operation). These numbers of cycles are the numbers of clocks necessary for the completion of an

operation. They are independent of the floating-point numbers’ value and are a fixed number of cycles for each type of operation. Table 8 describes how the performance of the FPU exceeds the average performance of the CPU.

Table 8 - Floating Point Unit Performance

Operation Number of Cycles

Addition/Subtraction 52

Multiplication 28

Division 27

Floating-Point to Long Integer Conversion 25

Long Integer to Floating-Point Conversion 32

Clear Accumulator A 2

NOP 1

HT

3012

Flo

atin

g P

oin

t U

nit


Pinouts In Pin Order

Continued on next page

Pin Signal 1 VLC 2 PIN1-1 3 SEG35 4 SEG0 5 SEG1 6 SEG2 7 SEG3 8 SEG4 9 SEG5

10 SEG6 11 SEG7 12 SEG8 13 SEG9 14 SEG10 15 BPL1-2 16 BPL1-1 17 BPL1-0 18 NC 19 NC 20 NC 21 NC 22 NC 23 MODE 24 CSIO1 25 CSIN 26 CSIO0 27 CLK19K2 28 D7 29 D6 30 D5 31 D4 32 D3 33 D2 34 D1 35 D0 36 GND

Pin Signal 37 VCD 38 A0 39 A1 40 A2 41 A3 42 A4 43 A5 44 A6 45 A7 46 CLK 47 R/W 48 E 49 AS 50 MUXON 51 NC 52 NC 53 NC 54 NC 55 NC 56 PIN1-2 57 SEG11 58 SEG12 59 SEG13 60 SEG14 61 SEG15 62 SEG16 63 SEG17 64 SEG18 65 SEG19 66 SEG20 67 SEG21 68 SEG22 69 BPL2-2 70 BPL2-1 71 BPL2-0 72 GND

Pin Signal 73 VLC 74 PIN1-3 75 SEG36 76 SEG37 77 SEG38 78 SEG39 79 SEG40 80 SEG41 81 SEG42 82 SEG43 83 SEG44 84 SEG45 85 SEG46 86 SEG47 87 BPL3-2 88 BPL3-1 89 BPL3-0 90 NC 91 NC 92 NC 93 NC 94 NC 95 NC 96 WRRAM 97 CSRAM 98 CSROM 99 OE 100 A8 101 A9 102 A10 103 A11 104 A12 105 A13 106 A14 107 A15 108 GND

Pin Signal 109 VCD 110 VCCA 111 PW2 112 PW1 113 PW0 114 GNDA 115 OTXA 116 IRXA 117 OCD 118 ITXD 119 ORXD 120 FLPRDY 121 NC 122 NC 123 NC 124 NC 125 NC 126 NC 127 RST 128 PIN1-0 129 SEG23 130 SEG24 131 SEG25 132 SEG26 133 SEG27 134 SEG28 135 SEG29 136 SEG30 137 SEG31 138 SEG32 139 SEG33 140 SEG34 141 BPL4-2 142 BPL4-1 143 BPL4-0 144 GND

HT

3012

Pin

ou

t D

etai

ls


SYMBOL TYPE PIN DESCRIPTION VCD I Voltage Reference - 3.0 - 5.0 Vdc VLC I LCD Display Voltage - 3.0 - 5.0 Vdc GND I Ground - 0.0 Vdc PIN[1-3: 1-0] I Pins that indicate the position of pin 1 of the selected backplane by the LCD position

detector. The LCD Driver uses these four bits to drive the data segments of the LCD accordingly to its position.

SEG[47:0] O Data Segments that drives the LCD BPL[4-2:4-0] BPL[3-2:3-0] BPL[2-2:2-0] BPL[1-2:1-0]

O Display back-plane Signals responsible for controlling the four-phase 160 segments into the LCD

NC N/A NOT Connected CSIN I This input pin shoould be connected to the CSIO1 output signal in order to select the

HT3012 internal registers access. CSIO1 O This Chip Select signal can be used to access an external device like a memory or any

other hardware interface component. The pins MODE and MUXON need to be connected accordingly following the CPU's architecture type chosen.

CSIO0 O This Chip Select signal is used to select the HT3012 internal registers when connected to the CSIN pin.

CLK19K2 O User Clock (nominally 19.2 kHz) D[7-0] I/O Data Bus/Address Bus carries the data generated from the CPU. When AS is asserted it

carries the lower 8 bits of the addresses generated from the CPU GNDA I Ground Reference - 0 V A[15-8] I Address Bus carries the upper 8 bits of the address generated from the CPU A[7-0] I Address Bus carries the lower 8 bits of the address generated from the HT3012 to access

external memories CLK I Clock signal generated by the same oscillator used by the CPU R/W I Read/Write specifies a read/write operation regarding the HT3012 E I E Clock generated by the CPU

AS I Address Strobe indicates whether the D7-D0 signals are addresses or data

WRRAM O Read/Write RAM specifies a read/write operation regarding the RAM memory CSRAM O RAM Chip Select selects an external RAM memory, which can be accessed via A15-A0

pins CSROM O EPROM Chip Select selects an external EPROM memory, which can be accessed via

A15-A0 pins OE O Output Enable used to enable the output data signals from HT3012 and external memories

PW[2-0] O D/A Analog Output Signals are the three components of the analog output from the D/A converter that should be added together and can be used directly in the analog environment

OTXA O Analog Communication Output provides a 1200Hz square wave FSK in response to a logical 1; 2200Hz in response to a logical

IRXA I Analog Communication Input accepts 1200 or 2200 Hz modulated square wave

OCD O Carrier detect (logical 0 when carrier is detected)

ITXD I Digital Communication Input is the modulator input and accepts input data (logical 0 or 1) for carrier output modulation at OTXA

ORXD O Digital Communication Output provides a logical 1 in response to a 1200Hz FSK square wave signal at IRXA; a logical 0 TO 2200Hz

FLPRDY O Floating Point Ready is an active low signal, which can be used to monitor Floating Point Coprocessor. A transition from high to low implies that this Coprocessor has started a computation, whereas a transition from low to high implies that its computation has finished and the result can be read via memory map

RST I Reset clears the internal registers of the chip and causes it to reinitialize. During RST assertion, the input pins are ignored and the output pins are placed in their non-asserted state

Pin Descriptions

HT

3012

Pin

ou

t D

etai

ls


HT3012 Pin Layout

HT

3012

Pin

Lay

ou

t


The HT3012 has the flexibility to interface with different types of micro-controllers. When interfaced properly The HT3012 can be seen as a part of the CPU memory-map.

There are specific requirements

regarding how the HT3012 should be connected with different CPUs, with memory, and with the analog circuit.

The HT3012 clock CLK signal

should be the same clock frequency as the crystal oscillator used by the CPU. The BUS CLK is the clock used to access external memory devices. The Address Strobe (AS) signal switches the bus (DATABUS) information to be either data or an address. The address bus responsible for memory access is comprised of the ADDRH bus (the eight most significant bits from the CPU) and the ADDRL bus (the eight least significant bits provided by the HT3012 after decoding DATABUS).

Both RESET signals, one from the

CPU and the other from the HT3012, should be tied to the same source for the purpose of assuring system consistency.

The CPU uses the ITXD and

ORXD to receive and transmit HART® signals from/to HT3012. The HT3012 interfaces with an analog circuit through IRXA and OTXA (HART® signals). Finally, the D/A conversion is generated via the PW2, PW1 and PW0 output ports.

An alternate implementation method can be used if the CPU does not

offer many chip select signals. The design shown in Figure 14 uses external PROM and RAM memory. In this case, the CPU accesses all memory addresses via chip select signals generated by the HT 3012. The HT3012 controls the address bus generating the addresses and the chip select signals necessary to interface with external memory devices. The Bus Control Logic Module section of this DataSheet explains in detail how to use these signals in a hardware design. CPU requirements for using of the HT3012: • The HT3012 requires a CPU with

asynchronous serial communication interface (SCI)

• The HT3012 requires a CPU with 8-bit Address/Data bus with Address Strobe signal

Variations of the HT3012 architecture:

When the HT3012 is generating the chip select (CS) pins, pin E should be connected to the CPU bus clock signal.

When the HT3012 is NOT

generating the chip select (CS) pins, pin E should be pulled-up to VCC. In this case, generation of the chip select requires a CPU with multiple chip select (CS) signals or external logic.

Microcontroller Environment

HT

3012

Mic

roco

ntr

olle

r E

nvi

ron

men

t


Application Notes - The HT3012 and HC11 Environment

One of the most common existing platforms for field devices in use today is a system architecture based on the 8-bit Motorola HC11 microcontroller. In this case, the HC11 accesses all memory addresses via chip select signals generated from the HT3012 (The Bus Control Logic Module section of this publication

explains in detail how to use these signals in a hardware design). The HT3012 source clock frequency depends on the chosen crystal for the HC11. The HT3012 has two input clock signals, E and CLK. The E signal is based on the HC11 E Clock, whereas CLK is the clock signal from the crystal.

The HT3012 will interface with some analog components. The OTXA and IRXA signals, respectively, transmit and receive data for HART®

communication. These lines should lead to filter circuits for transmission and reception of digital communication data. Other signals, such as PW0, PW1 and PW2, should be part of an op-sum circuit to compound the 15-bit analog current

value. For more details, please refer to the “HART® Modem Module” and “Digital-to-Analog Converter Module” sections of this publication.

The HT3012 generates all signals

necessary to interface with and access external PROM, EEPROM or RAM memory. These chip select signals are generated when software the application

Figure 14 - HT3012 and HC11 Environment

HT

3012

Ap

plic

atio

n N

ote

s


program writes or reads any addresses within the intervals described in the table below.

(Table 11 - Memory Mapping shows 64KBytes memory mapping as viewed from the M68HC11E1 CPU).

The CSROM and CSRAM signals are automatically generated when the address ranges specified in the Table 11 - Memory Mapping are accessed.

The embedded software must keep the program running in the range from $2000-$FFFF (reserved for PROM/FLASH memory) and use the range from $0200-$0FFF for data by using an external RAM memory when necessary.

The CSIO1 pin generates an external chip select signal for interfacing with an external device such as EEPROM memory or a dedicated integrated circuit. This is an extra chip select signal available for hardware interface purposes.

The CSIO0 pin generates a chip select signal to allow the embedded software to access the HT3012 internal memory registers. Every time an

address between the range from $1100-$11FF is accessed, the HT3012 will generate an external signal through this pin to signal that its internal registers can be read from or written to. Note: The HC11 INIT register controls

the position of the RAM in the internal memory map. The RAM can be repositioned to the beginning of any 4k-byte in the memory map by changing selected bits. After reset, the RAM is initially positioned from $000-$00FF. This register also controls the address for the 64-byte block of internal registers. By changing these bits, the register block is repositioned to the beginning of any 4k-byte page in the memory map. After reset, these registers are initially positioned from $1000-$103F.

Figure 11 - Memory Mapping of the HT3012 and HC11

Segment Range Pin Size (Bytes)

External PROM $2000-$FFFF CSROM 56K

External EEPROM $1200-$1FFF CSIO1 3.5k

HT3012 Internal Registers $1100-$11FF CSIO0 256

Reserved (HC11 Internal Registers)

$1000-$103F -- 256

External RAM $0200-$0FFF CSRAM 3.5K Reserved (HC11 Internal RAM)

$0000-$01FF -- 512

HT

3012

Ap

plic

atio

n N

ote

s


Table 12 - Absolute Maximum Ratings

Electrical Characteristics

Table 13 - Operating Conditions

Table 14 - DC Electrical Characteristics

Absolute Maximum Ranges

Operating Conditions

DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

LC Supply Voltage (Referenced to GND) VLC -0.5 7.0 V CD Supply Voltage (Referenced to GND) VCD -0.5 7.0 V CA Supply Voltage (Referenced to GNDA) VCCA -0.5 V Input Voltage (Referenced to GND) Vin -0.5 VCC* + 1.0 V Output Voltage (Referenced to GND) Vout -0.25 VCC* + 0.5 V Input Current, per Pin Iin µA Output Current, per Pin Iout µA LC Supply Current, VLC and GND Pins ILC µA CD Supply Current, VCD and GND Pins ICD µA CA Supply Current, VCCA and GNDA Pins ICCA µA Storage Temperature Tstg -55 150 °C Lead Temperature TL - 300 °C 10 seconds Clock Frequence fmax DC MHz

Symbol Parameter Min Max Unit

VLC, VCD Digital Supply Voltage (Referenced to GND) 2.0 6.0 V

VCCA Analog Supply Voltage (Referenced to GNDA) 2.0 5.0 V

Vin, Vout DC Input/Output Voltage (Referenced to GND) 0 VCC* V

TA Operating Temperature -40 85 °C

Symbol Parameter Test Conditions VCC* Min Max Unit VIH Minimum High Level Input Voltage 3.3 V

5.0 V V

VIL Maximum Low Level Input Voltage 3.3 V 5.0 V

V

VOH Minimum High Level Output Voltage 3.3 V 5.0 V

V

VOL Maximum Low Level Output Voltage 3.3 V 5.0 V

V

Iin Maximum Input Leakage Current 3.3 V 5.0 V

µA

ICC Maximum Quiescent Supply Current 3.3 V 5.0 V

µA

HT

3012

Ele

ctri

cal C

har

acte

rist

ics


Smar Research Corporation 4250 Veterans Memorial Highway

Holbrook, NY USA 11741 Tel: 631.737.3111 Fax: 631.737.3892

[email protected] www.SmarResearch.com

Smar Research reserves the right to make changes to design and functionality of any product without notice. Smar Research does not assume any liability arising out of the application or use of any product. Smar Research , Technology Source, and the SRC logo are registered trademarks of Smar Research Corporation. The HART, Fieldbus, and Profibus Foundation logos are

trademarks of their respective owners.

smarresearch full featured hart modem ht3012 … · intrinsic safety configuration tools...

Documents