Published by MB/SC 1363 Quality Printed in the Netherlands Subject to modification EN 3122 785 19393

2013-Mar-29

2013 © TP Vision Netherlands B.V.All rights reserved. Specifications are subject to change without notice. Trademarks are theproperty of Koninklijke Philips Electronics N.V. or their respective owners. TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjustearlier supplies accordingly.PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.

Colour Television Chassis

VES1.1ELA

See table of contents on page 3

Revision ListEN 2 VES1.1E LA1.

2013-Mar-29 back to div. table

1. Revision ListManual xxxx xxx xxxx.0• First release.

Manual xxxx xxx xxxx.1• Added the Service Mode menu.

Manual xxxx xxx xxxx.2• Added several new sets to this chassis, see table 2-1 Described

model numbers.• Added the section Hotel Mode setup menu.

Manual xxxx xxx xxxx.3• Added several schematics of the SSB.• Added the schematics of the PSU.

2. Technical Specifications and Connections

Index of this chapter:Technical specificationsDirections for Use

Notes:• Figures can deviate due to the different set executions.• Specifications are indicative (subject to change).

Technical Specifications

For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

Table 2-1 Described model numbers

Directions for Use

You can download this information from the following websites:http://www.philips.com/supporthttp://www.p4c.philips.com

CTN Styling Published in:

19PFL2908H/12 2900 3122 785 19392

22PFL2807H/12 2800 3122 785 19390

22PFL2908H/12 2900 3122 785 19392

24HFL2808D/12 2800 3122 785 19392

24PFL2908H/12 2900 3122 785 19392

26HFL2808D/12 2800 3122 785 19392

26PFL2908H/12 2900 3122 785 19392

32PFL2807H/12 2800 3122 785 19390

Contents 1 Introduction ............................................................................................................................................. 6

1.1 General Block Diagram ................................................................................................................... 7

1.2 SSB Placement of Blocks .................................................................................................................. 8

2 Tuner (TU3) .............................................................................................................................................. 9

2.1 General description of the Sony RE216 tuner .................................................................................. 9

3 Audio amplifier stage with AZAD2102 (U163, U164) ............................................................................. 11

3.1 General description ........................................................................................................................ 11

3.2 Features .......................................................................................................................................... 12

3.3 Absolute Ratings ........................................................................................................................... 13

3.3.1 Electrical Characteristics ....................................................................................................... 13

3.3.2 Operating specifications ....................................................................................................... 14

3.4 Pinning ............................................................................................................................................ 15

4 Audio amplifier stage with TPA3113 (U168) .......................................................................................... 15

4.1 General Description ....................................................................................................................... 15

4.2 Absolute Ratings ............................................................................................................................. 16

4.2.1 Electrical Characteristics ........................................................................................................ 16

4.2.2 Operating Specifications ...................................................................................................... 17

4.3 Pinning ........................................................................................................................................... 17

5 Power stage ............................................................................................................................................ 18

5.1 Power management ....................................................................................................................... 21

6 Microcontroller – MSTAR (U5) ............................................................................................................... 23

6.1 Description ..................................................................................................................................... 23

6.2 MSTAR block diagram .................................................................................................................... 27

6.3 Reset circuit .................................................................................................................................... 28

7 CI interface ............................................................................................................................................. 28

8 USB interface .......................................................................................................................................... 29

9 DDR2 SDRAM K4T1G164QF (U155) ....................................................................................................... 30

9.1 Description ..................................................................................................................................... 30

9.2 Features .......................................................................................................................................... 30

Pinning ........................................................................................................................................................ 31

10 Scaler and LVDS sockets ..................................................................................................................... 32

10.1 LVDS sockets block diagram .......................................................................................................... 32

10.2 Panel supply switch circuit ............................................................................................................. 32

11 SPI flash memory - MX25L1005 (U158) ............................................................................................. 33

11.1 General Description ....................................................................................................................... 33

11.2 Features.......................................................................................................................................... 33

11.3 Absolute maximum ratings ............................................................................................................ 34

11.4 Pinning ............................................................................................................................................ 34

12 NAND Flash memory – NAND512XXA2C (U162) ................................................................................ 35

12.1 General Description ....................................................................................................................... 35

12.2 Features .......................................................................................................................................... 35

12.3 Pinning ............................................................................................................................................ 36

13 LNBH23L (U6) ..................................................................................................................................... 37

13.1 Description ..................................................................................................................................... 37

13.2 Features.......................................................................................................................................... 37

13.3 Block diagram ................................................................................................................................. 38

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3) ....................................................................... 38

14.1 Description ..................................................................................................................................... 38

14.2 Features.......................................................................................................................................... 38

14.3 Pin Assignment .............................................................................................................................. 40

15 LM1117 (U175, U180, U181) .............................................................................................................. 41

15.1 General description ........................................................................................................................ 41

15.2 Features .......................................................................................................................................... 41

15.3 Applications .................................................................................................................................... 41

15.4 Absolute maximum ratings ............................................................................................................ 41

15.5 Pinning ............................................................................................................................................ 42

16 MP2012 (U176) .................................................................................................................................. 42

17 General description ............................................................................................................................ 42

17.1 Features .......................................................................................................................................... 42

17.2 Pinning ............................................................................................................................................ 43

18 RTA8283A (U23, U173) ....................................................................................................................... 43

18.1 General description ........................................................................................................................ 43

18.2 Features .......................................................................................................................................... 43

18.3 Pinning ............................................................................................................................................ 45

19 MP1583 (U174) .................................................................................................................................. 46

19.1 General description ........................................................................................................................ 46

19.2 Features .......................................................................................................................................... 46

19.3 Pinning ............................................................................................................................................ 46

20 FDC642 ............................................................................................................................................... 47

20.1 General description ........................................................................................................................ 47

20.2 Features .......................................................................................................................................... 47

20.3 Pinning ............................................................................................................................................ 47

21 FDC604P ............................................................................................................................................. 48

21.1 General description ........................................................................................................................ 48

21.2 Features .......................................................................................................................................... 48

21.3 Pinning ............................................................................................................................................ 48

22 Connectors ......................................................................................................................................... 49

22.1 SCART (SC1) .................................................................................................................................... 49

22.2 HDMI (CN707, CN708) ................................................................................................................... 49

22.3 VGA (CN711) ................................................................................................................................. 50

23 Service menu mode ............................................................................................................................ 51

23.1 Main service menu ......................................................................................................................... 51

23.2 Video Settings ................................................................................................................................. 52

23.3 Audio Settings ................................................................................................................................ 52

23.4 Options 1 ........................................................................................................................................ 53

23.5 Options 2 ........................................................................................................................................ 53

23.6 Tuning Settings ............................................................................................................................... 54

23.7 Source Settings ............................................................................................................................... 54

23.8 Diagnostic ....................................................................................................................................... 54

23.9 USB operations ............................................................................................................................... 54

23.10 Profile Operations ...................................................................................................................... 57

23.10.1 Upload profile Data from USB ............................................................................................ 57

23.10.2 PQ Files Operations ............................................................................................................ 57

23.10.3 Upload PQ files from USB ................................................................................................... 57

23.10.4 Ci+ credentials key update ................................................................................................. 57

23.10.5 HDCP keys update .............................................................................................................. 57

23.10.6 Edid update ....................................................................................................................... 58

23.10.7 DDR settings update ........................................................................................................... 58

23.10.8 MAC address update .......................................................................................................... 58

23.11 Hotel Mode setup menu ............................................................................................................ 58

23.11.1 Hotel TV welcome image update (only available in Hotel TVs) ......................................... 58

24 Software update ................................................................................................................................. 59

25 Troubleshooting ................................................................................................................................. 59

25.1 No backlight problem ..................................................................................................................... 59

25.2 CI module problem ......................................................................................................................... 61

25.3 LED blinking problem ..................................................................................................................... 63

25.4 IR problem ...................................................................................................................................... 63

25.5 Keypad touchpad problems ........................................................................................................... 64

25.6 USB problems ................................................................................................................................. 65

25.7 No sound problem.......................................................................................................................... 65

25.8 No sound problem at headphone .................................................................................................. 66

25.9 Standby On/Off problem................................................................................................................ 66

25.10 DVD problems ............................................................................................................................ 67

25.11 No signal problem ...................................................................................................................... 67

26 Styling sheet ....................................................................................................................................... 69

27 Schematics .......................................................................................................................................... 70

27.1 SSB .................................................................................................................................................. 70

27.2 PSU ................................................................................................................................................. 79

1 Introduction The SSB is driven by a MStar SOC. This IC is capable of handling Video and audio processing, Scaling-Display processing, 3D comb filter, OSD and text processing, LVDS transmitting, channel and MPEG2/4 decoding, integrated DVB-T/C demodulator and media center functionality.

The TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Also DVB T, DVB-C are supported internal demodulators of Mstar IC and DVB-S/S2 is supported with external demodulator.

Sound system output is supplying max. 2 × 2.5 W (less 10% THD at maximum output) with 4 Ω speakers or 2 × 6 W for stereo 8 Ω speakers.

Supported peripherals are:

1 RF input VHF I, VHF III, UHF @ 75 Ω (Common) 1 Side AV (CVBS, R/L_Audio) 1 SCART socket (Common) 1 YPbPr (Optional) 1 PC input (Common) 2 HDMI 1.3 input (1 HDMI input is common, 1 input is optional) 1 S/PDIF output (Optional) 1 Headphone (Optional) 1 Common interface (Common) 1 USB (Common) 1 DVD (Optional) 1 On-board Keypad (Optional) 1 External Keypad (Optional) 1 External TouchPad (Optional)

1.1 General Block Diagram GPIO D3K

Mstar ••

VGA

HDIJI1

!

i -HPOErecr-.

2XIi'H .O.UDIO AU'

Block Diagram

V1.1 Drawn By Ulas Dere i

03.01.2011

1.2 SSB Placement of Blocks Sat Demod

CI Connector

Nand Flash (U162)

USB

YPbPr SAV HP Satellite Tuner

Keypad

Speaker Con.

Tuner(T3 )

External Keyboard Touchboard

Main IC

(U5)

HDMI Connectors

VGA

SCART Connec tor

Led Con

DVD Connector

Power Connector

LVDS Connectors

DDR2 RAM (U155)

SPI Flash

Adapter DC Input

SPDIF Out

Inv. Con

2 Tuner (TU3) A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3 Bands (From 48 MHz to 862 MHz for COFDM, from 45.25 MHz to 863.25 MHz for CCIR channels). The tuning is available through the digitally controlled I2C bus (PLL).

In the active antenna option, the following circuits are used. ANT_CTRL pin is controlled by microcontroller. If ANT_CTRL is low, ANT_PWR will be low. If ANT_CTRL is high, ANT_PWR will be high.

OVER_CUR_DETECT pin is a monitor for short circuit in antenna. OVER_CUR_DETECT is low, ANT_CTRL will be low, so ANT_PWR will be low. Finally, short circuit protection is done by circuits and microcontroller.

2.1 General description of the Sony RE216 tuner The SUT-RE216 is designed for terrestrial TV (digital & analog) and digital cable reception. It includes a full band tuner and a channel filtering for digital signals. It provides a low IF output after channel filtering to drive a channel demodulator. Tuning, band switching and initialization are made via an I2C bus interface. The module is built on a low-loss printed circuit board carrying all the components in a metal housing frame with top and rear covers. The single aerial connector is mounted on one frame side and all other connections are made via pins at the bottom.

Features:

Full frequency range from 47 to 870 Mhz • Digital Platform (DVB-T/T2, DVB-C, ISDB-T & ATSC) Analog platforms (PAL B/G/I/D/K, NTSC M & SECAM L/L’) Low IF tuner concept

./ Programmable channel Filter bandwidth ./ Fully I2C bus controlled ./ For Hybrid TV applications

3.3V pull up

-

1000 1uF ----)-------w. -

AGC:

I

1KO

:---------------------------------------•------o..-----'M'h\--®f-----....-!-'N\\-OIAocI

---Pinning Table

and Application Block Diagram of Tuner---

3 Audio amplifier stage with AZAD2102 (U163, U164)

3.1 General description This chassis uses two 2.5 W Class D Mono Audio Amplifers for from 16" to 24" TVs. AZAD2102B is a 2.9 Watts (max. can offer 3.0 Watts @ Load = 3 Ω,THD = 10%, AVdd = DVdd = 5.5 Volt) with high efficiency filter-free class-D audio power amplifier in a 1613 mm x 1613 mm wafer chip scale package (WCSP). AZAD2102B uses Current- switch technology to achieve high performance class-d amplifier that features 0.03% THD, 85% efficiency, –70 dB PSRR, to improve RF-rectification immunity.

AZAD2102B provide a Vibration-Spectrum modulation clock for PWM Output. This vibration frequency is around 10 kHz shift (+/- 5 kHz of Fpwm).

The advantage of the small size package (WCSP) makes AZAD2102B very suitable for mobile phone and PDA device application. And the Class-D amplifier structure let AZAD2102B to have highly efficiency power consumption than Class-AB amplifier. AZAD2102B can shrink the application board, reduce system cost, and external components.

ESD level protection I/O embedded in AZAD2102B. For general applications, there is no need to add extra ESD protection devices (like Varistors) in application systems for AZAD2102B’s I/O.

3.2 Features • CMOS Technology • High Efficiency 85% • High PSRR 70 dB at 217 Hz • Differential OP-amp Input • AZAD2102B provides Vibration-Spectrum Modulation clock for reduce EMI • Provide Mute function (set Mute_B to GND will go into Mute status) • For the input stage AZAD2102B built-in a 10Kohm resistors (Gain

setting = 29.5 dB) • Maximum Battery Life and Minimum Heat • Efficiency With an 8 Ω Speaker: • 3.5 mA Quiescent Current • Output Power at 10% THD • 2.85 Watts at AVdd = DVdd = 5.0 Volt, Rload = 4 Ω • 1.45 Watts at AVdd = DVdd = 3.6 Volt, Rload = 4Ω • 0.30 Watts at AVdd = DVdd = 3.0 Volt, Rload = 4Ω • 1.75 Watts at AVdd = DVdd = 5.5 Volt, Rload = 8Ω • 0.87 Watts at AVdd = DVdd = 3.6 Volt, Rload = 8Ω • 0.41 Watts at AVdd = DVdd = 3.0 Volt, Rload = 8Ω • Eliminate Power on and Power-off “Pop” noise • A fewer external components • Optimized PWM output stage eliminates LC output filter • Internally generate 290 kHz switching frequency to eliminate capacitor and resistor • Improve PSRR (–70 dB) and wide supply voltage (3.0 V to 5.5 V) • Fully differential design reduces RF rectification • This chip has been built-in a very strong ESD protection. • System level ESD 4 KV (IEC 61000-4-2 ESD Contact Level) • Wafer chip scale package (WCSP) • TSSOP package with exposed pad

.

3.3 Absolute Ratings

3.3.1 Electrical Characteristics VDD = AVdd = DVdd, VSS = AVss = DVss = Ground

TA = 25C, Filter Bandwidth = 20 Hz -20 kHz

PARAMETER Symbol TEST COND TIONS MNI TYP MAX UNIT

Operating Votlage Vop AVdd-DVdd to AVss-DVss 3.0 5 5.5 v Output offset voltage

vos

VDD = 5.5 V,VI= 0 V,AV = 6 V/V 4.5 6.5

mV VDD = 3.6 V,VI= 0 V,AV = 6 V/V 2.1 4.0

VDD = 3.0 V,VI= 0 V,AV = 6 V/V 1.2 3.0 Power supply rejection ratio

PSRR

VDD = 3.0 V to 5.5 V, AV = 2 V/V input ac grounded with

Ci=2.2uF,Vripple=200mVpp, RL=80 f=217Hz

-68

dB

Common mode rejection ratio

Cf':lRR VDD = 3.0 V to 5.5 V,Vic = VDD/2 to 0.5 V,Vi c = VDD/2 to 0.5 VDD -0.8 V,

-65

dB

High level nput current

IIIHII

VDD= 5.5V,Vi=5.8V

25

uA

Low level Input current

IIlLI VDD= 5.5V,Vi=-0.3V

1

uA

Operation current

lop

VDD = 5.5 V,no load 3.6 5.0

mA VDD = 3.6 V,no load 3.0 4.2

VDD = 3.0 V,no load 2.5 3.5 Output switching frequency

Fpwm

VDD = 5.5 V,no load 290

KHz VDD = 3.6 V,no load 300

VDD = 3.0 V,no load 315 Vibration-Spectrum Modulation clock Ranqe

Fvs

VDD = 5.0 V,no load

+/-5 +/-10

KHz

Under Voltage Protection

UVP

Vin+ and Vin- connect to GND,no load

2.0 2.5 v

Mute_B pin Impedance RMuB Mute_B to Ground 270 KQ Gain

Gain VDD=5.0V,Ri=5K0+10K

O (Av=20V/V)

18 I 20 I 22

V/V

3.3.2 Operating specifications TA = 25°C,Gain = 20 V/V,

PARAMETER TEST COND TIONS MIN TYP MAX UNIT

Pw

Output power

THO+ N = 10%, f = 1kHz,RL = 4Q

VDD = 5.0V 2.85

w VDD = 3.6 V 1.45

VDD = 3.0 V 0.77 THO + N = 1%, f = 1 kHz, RL = 4 Q

VDD = 5.0 V 2.25

w VDD = 3.6 V 1.15

VDD = 3.0 V 0.60 THO+ N = 10%, f = 1kHz,RL = 8Q

VDD = 5.0 V

1.75

w VDD = 3.6 V 0.87

VDD = 3.0 V 0.47 THO + N = 1%, f = 1 kHz, RL = 8 Q

VDD = 5.0 V 1.39

w VDD = 3.6 V 0.70

VDD = 3.0 V 0.36

THD+N

Total harmonic distortion plus noise

VDD = 5.0 V,PO = 1W,RL = 8 Q,f = 1kHz 0.15

% VDD = 3.6 V,PO = 0.5 W,RL = 8 Q, f = 1 kHz 0.12

VDD = 3.0 V,PO = 200 mW, RL = 8 Q, f = 1kHz 0,09

PSRR

Supply ripple rejection ratio

VDD = 3.6 V, Av=20V/V,Inputs connect to grounded with Ci = l.OJ,JF

F = 217 H.z, VRipple = 200 mVpp

-67

dB

SNR Signal-to-noise ratio VDD = 5 V,PO = 1W,RL = 8 Q 95 dB

Vnoise

Output noise level

VDD = 3.6 V,f = 20 Hz to 20 kHz, nputs ac-grounded with Ci = l.OJJF

No weighting 45 J,JVRMS

A weighting

40 CMRR Common mode

rejecti on ratio

VDD = 3.6 V,Vin = 100mVpp f = 217Hz -72

dB

ZI Input impedance 8 10 12 kQ

ZF Feedback resistor 120 150 180 kQ

3.4 Pinning

4 Audio amplifier stage with TPA3113 (U168)

4.1 General Description This chassis uses a 6 W Class D Mono Audio Amplifier for from 26” to 32” TVs. The TPA3113D2 is a 6 W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a "virtual" voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3113D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the TPA3113D2, 87%, eliminates the need for an external heat sink when playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an auto-recovery feature.

3.2. Features • 6 W/ch into an 8-Ω Loads at 10% THD+N From a 10-V Supply • 12-W into a 4-Ω Mono Load at 10% THD+N From a 10-V Supply • 87% Efficient Class-D Operation Eliminates Need for Heat Sinks • Wide Supply Voltage Range Allows Operation from 8 V to 26 V • Filter-Free Operation • SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC

Protection • Flow Through Pin Out Facilitates Easy Board Layout • Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto

Recovery Option • Excellent THD+N / Pop-Free Performance • Four Selectable, Fixed Gain Settings • Differential inputs

4.2 Absolute Ratings

4.2.1 Electrical Characteristics

4.2.2 Operating Specifications AC CHARACTERISTICS TA = 25•c, Vee = 12 V, RL = 8 0 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

KsvR Supply ripple rejection 200 mVpp ripple from 20 Hz-1kHz, Gain = 20 dB,Inputs ac-coupled to AGNO

-70

dB

THO+N Total harmonic distortion +noise RL = 8 0, f = 1kHz, Po = 3 W (half-power) 0.06 % Vn Output integrated noise

20 Hz to 22 kHz,A-weighted filter, Gani = 20 dB

65 IJV

-80 dBV

Crosstalk P0 = 1 W,Gain = 20 dB, f = 1 kHz -100 dB SNR Signa-l to-noise ratoi Maximum output at THO+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted

102

dB

fosc Oscillator frequency 250 310 350 kHz

Thermal trip point 150 ·c Thermal hysteresis 15 ·c

4.3 Pinning

PIN 110/P

DESCRIPTION

NAME Pin Number

so

1

I Shutdown logic input for audio amp (LOW = outputs Hi-Z,HIGH = outputs enabled).TTL logic levels with compliance to AVCC.

FAULT

2

0

Open drain output used to display short circuit or de detect fault status.Votlage compilant to AVCC.Short circuit faults can be set to auto-recovery by connecting FAULT pin to SO pin. Otherwise, both short circuit faults and de detect faults must be reset by cycling PVCC.

LINP 3 I Postiive audio input for left channeL Biased at 3V.

LINN 4 I Negative audio input for left channeL Biased at 3V.

GAlNO 5 I Gani select least significant bit. TTL logic levels with compliance to AVCC.

GAIN1 6 I Gani seel ct most significant bit TTL logic levels with compliance to AVCC.

AVCC 7 p Analog supply

AGNO 8 Analog signalground. Connect to the thermal pad. GVOO

9

0 High-side FET gate drive supply.Nominalvoltage is 7V. Also should be used

as supply for PLIMIT function PLIMIT

10

I Power limti leveladjust Connect a resistor divider from GVOO to GND to set

powerlimit. Connect directly to GVOO for no power limit.

RINN 11 I Negative audio input for right channe.l Biased at 3V.

RINP 12 I Positive audio input for right channeL Biased at 3V. NC 13 Not connected

PBTL 14 I ParallelBTL mode switch PVCCR

15 p Power supply for right channel H-bridge. Right channeland left channelpower

supply inputs are connect internally. PVCCR

16 p Power supply for right channel H-bridge. Right channelandleft

channelpower supply inputs are connect internally. BSPR 17 I Bootstrap 110 for right channel, positive high-side FET.

OUTPR 18 0 Class-0 H-bridge positive output for right channel.

PGNO 19 Power ground for the H-bridges. OUTNR 20 0 Class-0 H-bridge negative output for right channel.

BSNR 21 I Bootstrap 1/0 for right channel, negative high-side FET.

BSNL 22 I Bootstrap 1/0 for left channe,l negative high-side FET.

OUTNL 23 0 Class-0 H-bridge negative output for left channel.

PGNO 24 Power ground for the H-bridges. OUTPL 25 0 Class-0 H-bridge positive output for left channeL

BSPL 26 I Bootstrap 1/0 for left channe,l positive high-side FET. PVCCL

27 p Power supply for left channelH-bridge. Right channel and left channel power

supply inputs are connect internally. PVCCL

28 p Power supply for left channelH-bridge. Right channel and left channel power

supply inputs are connect internally.

5 Power stage The DC voltages required at various parts of the chassis and panel are provided by a main power supply unit. This chassis can operate with the different supplies: IPS60, IPS16, IPS17, PW26, PW27 as main power supply and also with 12V adaptor.

CN706 is used for IPS60, IPS16 and IPS17 and CN1 is used for PW26 and PW27.

JK9 is used for the adapter option and also CN705 inverter socket or DB32 chassis with CN706 is used to supply backlight.

The power supplies generate 18V, 12V, 5V, 3,3V and 12V, 5V, stand- by mode DC voltages. Power stage which is on-chassis generates 5V, 3V3 stand by voltage and 12V, 8V, 5V, 3V3, 2.5V, 1,8V and 1,2V supplies for other different parts of the chassis. Chassis block diagram is indicated below.

The blocks on power block diagram is using dependent to main supply. For PW26 and PW27 just common blocks are enough for proper operation.

For IPS16, IPS17, IPS60 below blocks must work properly.

For adapter case also below blocks are necessary.

Short CCT Protection Circuit

Short circuit protection is necessary for protecting chassis and main IC against damages when any Vcc supply shorts to ground. Protect pin should be logic high while normal operation. When there is a short circuit protect pin shold be logic low. After any short detection, SW forces LEDs on LED card to blink.

5.1 Power management

--- Power Management with Adaptor---

--- Power Management with PW25/ PW26---

--- Power Management with IPS16/IPS17/IPS60/PW05---

--- Power Management with PW03/PW04/PW07---

6 Microcontroller – MSTAR (U5)

6.1 Description MSD9WB9PT-2 (Main IC) (U5)

The MSD9WB9PT-2 is MStar’s most up-to-date system-on-chip solution for flat panel integrated digital television products. Building on the success of MStar’s preceding SOC series, the MSD9WB9PT-2 provides most cost-effective solution for DTV application with creative and attractive features exclusively presented by MStar. The MSD9WB9PT-2 integrates DTV/multi-media all-purpose AV decoder, DVB-T demodulator, VIF demodulator, and Sound/Video processor into a single device. This allows the overall BOM to be reduced significantly making the MSD9WB9PT-2 a very competitive multi-media DTV solution. For ATV users, the MSD9WB9PT-2 provides multi- standard analog TV support with adaptive 3D video decoding and VBI data extraction. The build-in audio decoder is capable of decoding FM, AM, NICAM, A2, BTSC and EIA-J sound standards. The MSD9WB9PT-2 supplies all the necessary A/V inputs and outputs to complete a receiver design including a multi-port HDMI receiver and component video ADC. All input selection multiplexed for video and audio are integrated, including full SCART support with CVBS output. The equipped MStar MACE-5 color engine is the latest masterpiece from MStar famous color engine series providing excellent video and picture quality in Full-HD and large-scale displaying system. To meet the increasingly popular energy legislative requirements without the use of additional hardware, the MSD9WB9PT-2 has an ultra low power standby mode during which an embedded MCU can act upon standby events and wake up the system as required.

The MSD9WB9PT-2 is composed of several modules:

• High Performance Micro-processor

o Ultra high speed/performance 32-bit RISC CPU o One full duplex UARTs o Supports USB and ISP programming o DMA Engine

• Transport Stream De-multiplexer o Supports parallel and serial TS interface, with or without sync signal o Supports TS input and output for external CI module o Maximum TS data rate is 104 Mb/sec for serial or 16 MB/sec for parallel o 32 general purpose PID filters and section filters for each transport stream

de-multiplexer o Supports additional audio/video/PCR filters o Supports TS DMA channel for time-shift o Supports 3DES/DES and AES encryption/decryption

• MPEG-2 Video Decoder o ISO/IEC 13818-2 MPEG-2 video MP@HL o Automatic frame rate conversion o Supports resolution up to HDTV (1080i, 720p) and SDTV

• MPEG-4 Video Decoder

o ISO/IEC 14496-2 MPEG-4 ASP video decoding o Supports resolutions up to HDTV (1080p@30fps) o Supports DivX1 Home Theater & HD profilesOptional o Supports VC-1Optional, FLV video format decoding

• Hardware JPEG o Supports sequential mode, single scan o Supports both color and grayscale pictures o Following the file header scan the hardware decoder fully handles the

decode process o Supports programmable Region of Interest (ROI) o Supports formats: 422/411/420/444/422T o Supports scaling down ratios: 1/2, 1/4, 1/8 o Supports picture rotation

• NTSC/PAL/SECAM Video Decoder o Supports NTSC-M, NTSC-J, NTSC-4.43, PAL (B,D, G, H, M, N, I, Nc),

and SECAM standards o Automatic standard detection o Motion adaptive 3D comb filter o Five configurable CVBS & Y/C S-video inputs o Supports Teletext, Closed Caption (analog CC 608/ analog CC 708/digital

CC 608/digital CC708), V-chip and SCTE • Multi-Standard TV Sound Processor

o SIF audio decoding o Supports BTSC/A2/EIA-J demodulation o Supports NICAM/FM/AM demodulation o Supports MTS Mode Mono/Stereo/SAP in BTSC/ EIA-J mode o Supports Mono/Stereo/Dual in A2/NICAM mode o Built-in audio sampling rate conversion (SRC) o Audio processing for loudspeaker channel, including volume, balance,

mute, tone, EQ,virtual stereo/surround and treble/bass controls o Advanced sound processing options available,for example: SRS1, BBE2,

QSound3, Audyssey4 o Supports digital audio format decoding:

MPEG-1, MPEG-2 (Layer I/II), MP3, Dolby Digital (AC-3), AAC-LC Supports Optional Dolby Digital Plus, Dolby mPulse, and MS10

multistream decoder, including Dolby Digital Encoder for transcoding streams to Dolby Digital 5.1 (DDCO)

Supports MPEG Audio, Dolby Digital, Dolby Digital Plus format AD (Audio Description)

o Supports PVR and time-shifting • Audio Interface

o One SIF audio input interface with minimal external saw filters o Four L/R audio line-inputs o Two L/R outputs for main speakers and additional line-outputs o Supports stereo headphone driver o I2S digital audio input & output o S/PDIF digital audio output o HDMI audio channel processing o Programmable delay for audio/video synchronization

o Analog RGB Compliant Input Port o Three analog ports support up to 1080P o Supports PC RGB input up to SXGA@75Hz o Supports HDTV RGB/YPbPr/YCbCr o Supports Composite Sync and SOG Sync-on-Green o Automatic color calibration o AV-link support o Analogue RGB Auto-Configuration & Detection o Auto input signal format and mode detection o Auto-tuning function including phasing, positioning, offset, gain, and jitter

detection o Sync Detection for H/V Sync

• DVI/HDCP/HDMI Compliant Input Port o Two HDMI/DVI Input ports o HDMI 1.3 Compliant o HDCP 1.1 Compliant o 225 MHz @ 1080P 60 Hz input with 12-bit Deep-color support o CEC support o Single link DVI 1.0 compliant o Robust receiver with excellent long-cable support

• MStar Advanced Color Engine (MStarACE-5) • 10/12-bit internal data processing • Fully programmable multi-function scaling engine

o Nonlinear video scaling supports various modes including Panorama o Supports dynamic scaling for VC-1

• High-Quality DTV video processor o 3D motion video deinterlacer with motion object stabilizer o Edge-oriented deinterlacer with edge and artifact smoother o Automatic 3:2/2:2/M:N pull-down detection and recovery o 3D multi-purpose noise reduction for DTV or lousy air/cable input o MPEG artifact removal including de-blocking and mosquito noise

reduction o Arbitrary frame rate conversion

• MStar Professional Picture Enhancement: o Dynamic brilliant and fresh color o Dynamic Blue Stretch o Intensified contrast and details o Dynamic Vivid Skin o Dynamic sharpened Luma/Chroma edges o Global and local dynamic depth of field perception o Accurate and independent color control o Supports sRGB and xvYCC color processing o Supports HDMI 1.3 deep color format

• Programmable 12-bit RGB gamma CLUT • Output Interface

o Single/dual link 8/10-bit LVDS output o Supports panel resolution up to Full-HD (1920x1080) @ 60Hz o Supports TH/TI format o Supports dithering options to 6/8-bit output o Spread spectrum output for EMI suppression

• CVBS Video Encoder o Supports all NTSC/PAL TV Standard o Stand-alone scaling engine o Programmable Hue, Contract, Brightness o Supports TTX/CC/WSS output

o CVBS Video Output

o Allows CVBS output of all source inputs • 2D Graphics Engine

o Hardware Graphics Engine for responsive o Interactive applications o Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid

draw o BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt o Raster Operation (ROP) o Support Porter-Duff

• VIF Demodulator o Compliant with NTSC M/N, PAL B, G/H, I, D/K, SECAM L/L' standards o Audio/Video dual-path processor o Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution o Maximum IF gain of 37 dB o Programmable TOP to accommodate different tuner gain and SAW filter

insertion loss to optimize noise and linearity performance o Multi-standard processing with single SAW o Supports silicon tuner low IF output architecture

• DVB-T Demodulator o Digital carrier frequency offset correction: ±500KHz o Optimised for SFN channels with pre/post-cursive echoes inside/outside

the guard o Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset o Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test

requirement o ±400kHz internal carrier offset recovery range o 6.8 usecs echo cancellation at 7 Msym/s o Supports IF, low-IF, zero-IF inputs o Ultra-fast automatic blind UHF/VHF channel scan (constellations and

symbol rate) • Connectivity

o Two USB 2.0 host ports o USB architecture designed for efficient support of external storage

devices in conjunction with off air broadcasting • Miscellaneous

o DRAM interface supporting one 16-bit DDR2 @1066MHz o Supports PVR o Supports Common Interface for conditional access support o Bootable SPI interface with serial flash support o Parallel interface for external NAND flash support o Power control module with ultra low power MCU available in standby

mode o 380-ball LFBGA package o Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and

analog)

6.2 MSTAR block diagram

6.3 Reset circuit Reset circuit using for initiliazing main Mstar IC. Reset condition is high and nomal working condition is low for RESET pin.

7 CI interface CI Interface Power Switch: It is used for CI module supply, when Module is inserted (it means CI detect is low) This circuit is opened or closed by CI_POWER_CTRL port of main uController

8 USB interface Main Concept IC has integrated 2 USB 2.0 interface. One of them is used for ethernet function, the other one is used for USB connectivity for last user. Last user can play video, picture and audio files. Also digital channels can be record to external storage device by this interface. All SW files can be updated with interface.

USB circuit has 3 main parts • Integrated USB 2.0 Host interface of D3K (U5) • Protection IC (U145) • Over current protection IC (U8)

9 DDR2 SDRAM K4T1G164QF (U155)

9.1 Description The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver (OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 1Gb (x8) device receive 14/10/3 addressing. The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1 Gb DDR2 device is available in 60 ball FBGA(x8) and 84ball FBGA(x16).

9.2 Features

• JEDEC standard VDD = 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 533MHz fCK for 1066Mb/sec/pin • 8 Banks • Posted CAS • Programmable CAS Latency: 4, 5, 6, 7 • Programmable Additive Latency: 3, 4, 5. 6 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional

feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High • Temperature Self-Refresh rate enable • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <

95°C • All of products are Lead-free, Halogen-free, and RoHS compliant

7

Voo NC Vss OQ14 VssQ UOM

VoDQ OQ9 VooQ OQ12 VssQ DQ11

Voo NC Vss DQ6 VssQ LDM

VoDQ OQ1 VooQ DQ4 VssQ OQ3

VooL VREF Vss CKE WE

BA2 BAO BA1 A10/AP A1

Vss A3 AS A7 A9

Voo A12 NC

VssQ UOQS VoDQ UOQS VssQ DQ15

VoDQ DQ8 VoDQ

DQ10 VssQ OQ13

VssQ LDQS VoDQ

LOQS VssQ OQ7

VoDQ DQO VoDQ OQ2 VssQ OQ5

VssoL CK Voo

RAS CK OOT CAS cs A2 AO Voo

A6 A4

A11 A8 Vss NC NC

F ••• ••

G

Pinning

1 2 3 7 8 9

Ball Locations (x16) 1 2 3 4 s 6 8 9

AB ••••••++++++•·••••• cD •••+++•· ••

• Populated ball + Ball not populated

Top view (See the balls throughpackage)

E•••++++•• •• H •••+++•· ••

KJ +••+++•·• • ML +•••••++++•· •+• N •••+++•· •+ pR +•••••+++•· •+•

10 Scaler and LVDS sockets

10.1 LVDS sockets block diagram

10.2 Panel supply switch circuit This switch is used to open and close panel supply of TCON. It is controlled by port of main ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel supplys are connected to this circuit. All of them are optional according to panels.

11 SPI flash memory - MX25L1005 (U158)

11.1 General Description MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L1005 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L1005 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

11.2 Features • Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 • 1,048,576 x 1 bit structure • 32 Equal Sectors with 4K byte each, Any Sector can be erased individually • 2 Equal Blocks with 64K byte each, Any Block can be erased individually • Single Power Supply Operation

• 2.7 to 3.6 volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 1.5V to 2.5V

11.3 Absolute maximum ratings

RATING VALUE Ambient Operating Temperature

0°C to 70°C

Storage Temperature -55°C to 125°C Applied Input Voltage -0.5v to 4.6v Applied Output Voltage -0.5v to 4.6v

VCC to Ground Potential -0.5v to 4.6v

11.4 Pinning 8-PIN SOP (150mil)

SYMBOL DESCRIPTION CS# Chip select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without

deselecting the device VCC +3.3v Power Supply

GND Ground

12 NAND Flash memory – NAND512XXA2C (U162)

12.1 General Description The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND technology. It is referred to as the small page family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations.

12.2 Features • High density NAND flash memories

o 512-Mbit memory array o Cost effective solutions for mass storage applications

• NAND interface

o x8 or x16 bus width o Multiplexed address/ data

• Supply voltage: 1.8 V, 3 V • Page size

o x8 device: (512 + 16 spare) bytes o x16 device: (256 + 8 spare) words

• Block size

o x8 device: (16K + 512 spare) bytes o x16 device: (8K + 256 spare) words

• Page read/program

o Random access: 12 μs (3 V)/15 μs (1.8 V) (max) o Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min) o Page program time: 200 μs (typ)

• Copy back program mode • Fast block erase: 2 ms (typ)

• Status register • Electronic signature • Chip Enable ‘don’t care’ • Security features

o OTP area

• Serial number (unique ID) option • Hardware data protection

o Program/erase locked during power transitions

• Data integrity o 100,000 program/erase cycles (with ECC) o 10 years data retention

• RoHS compliant packages • Development tools

o Error correction code models o Bad blocks management and wear leveling algorithms

12.3 Pinning

13 LNBH23L (U6)

13.1 Description Intended for analog and digital satellite receivers,the LNBH23L is a monolithic voltage regulator and interface IC, assembled in QFN32 5 x 5 specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

13.2 Features

• Complete interface between LNB and I²C bus

• Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A)

• Selectable output current limit by external resistor

• Compliant with main satellite receivers output voltage specification

• Auxiliary modulation input (EXTM pin) facilitates DiSEqC™ 1.X encoding

• Accurate built-in 22 kHz tone generator suits widely accepted standards

• Low-drop post regulator and high efficiency step-up PWM with integrated power

NMOS allow low power losses

• Overload and over-temperature internal protections with I²C diagnostic bits

• LNB short circuit dynamic protection

• +/- 4 kV ESD tolerant on output power pins

13.3 Block diagram

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3)

14.1 Description The M88DS3002 is an advanced single-chip demodulator for digital satellite television broadcasting. It is fully compliant with the DVB-S/S2 standard and can support QPSK, 8PSK, 16APSK and 32APSK demodulation schemes. The chip provides a fast, easy-to- apply and cost-effective front-end solution for digital satellite receiver. The M88DS3002 accepts baseband differential or single ended I and Q signals from a tuner, then digitizes, demodulates and decodes the signals, and finally outputs an MPEG transport stream. The M88DS3002 supports symbol rate from 1 Msps up to 45 Msps, and code rate from 1/4 to 9/10. Its features cover blind scan, fade detection, timing and carrier recovery, performance monitoring, co-channel interference cancellation, command interface, and DiSEqC™ 2.X interface, etc. The device is controlled via a 2-wire serial bus. The M88DS3002 works properly with 1.25 V and 3.3 V voltage supplies. Typically, the power consumption is around 390 mW. The chip is available in a 64-pin QFN package and is RoHS compliant.

14.2 Features

• Multi-standard demodulation • Compliant with DVB-S/S2 specification • QPSK, 8PSK, 16APSK and 32APSK demodulation schemes • Maximum channel bit rate is 130 Mbps • Maximum symbol rates are: 45 Msps for QPSK and 8PSK; 36 Msps for 16APSK

and 28 Msps for 32APSK

• DSP features

• Symbol rate sweeping • I/Q impairment cancellation • Automatic spectrum inversion • Adaptive equalizer for RF reflection removal • Roll-off factor automatic identification • Blind scan for programming search • High performance on-chip micro-controller • Multi-error monitor • Accurate SNR estimation • Multi-lock indicators • Clipping rate reporter • DC removal • Automatic frequency correction (AFC) • Fast timing loop acquisition • Robust frame synchronization scheme • Phase noise indicator • Fast system recovery from fading or other abnormal conditions • Co-channel interference cancellation • Constellation monitor

• Interface

• DVB-S/S2 common, parallel and serial MPEG output interface compliant • 2-wire serial bus to configure the device • 2-wire bus repeater for tuner configuration • DiSEqC™ 2.X compliant interface • General purpose output (GPO) • Dedicated reference clocks (13.5MHz / 27MHz) generation

• System o On-chip 8-bit ADC o On-chip PLL for master clock from a 27 MHz external clock or quartz

crystal o Sleep mode supported

---Block Diagram of M88DS3002---

14.3 Pin Assignment

15 LM1117 (U175, U180, U181)

15.1 General description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve the transient response and stability.

15.2 Features • Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions • Space Saving SOT-223 Package • Current Limiting and Thermal Protection • Output Current 800mA • Line Regulation 0.2% (Max) • Load Regulation 0.4% (Max) • Temperature Range • LM1117 0°C to 125°C • LM1117I -40°C to 125°C

15.3 Applications • 2.85V Model for SCSI-2 Active Termination • Post Regulator for Switching DC/DC Converter • High Efficiency Linear Regulators 15 • 32” TFT TV Service Manual 10/01/2005 • Battery Charger • Battery Powered Instrumentation

15.4 Absolute maximum ratings

15.5 Pinning

16 MP2012 (U176)

17 General description The MP2012 is a fully integrated, internally compensated 1.2MHz fixed frequency PWM step-down converter. It is ideal for powering portable equipment that runs from a single cell Lithium-Ion (Li+) Battery, with an input range from 2.7V to 6V. The MP2012 can provide up to 1.5A of load current with output voltage as low as 0.8V. It can also operate at 100% duty cycle for low dropout applications. With peak current mode control and internal compensation, the MP2012 is stable with ceramic capacitors and small inductors. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.

17.1 Features • 2.7-6V Input Operation Range • Output Adjustable from 0.8V to VIN • 1 μA Max Shutdown Current. • Up to 95% Efficiency • 100% Duty Cycle for Low Dropout • Applications • 1.2MHz Fixed Switching Frequency • Stable with Low ESR Output Ceramic • Capacitors • Thermal Shutdown • Cycle-by-Cycle Over Current Protection • Short Circuit Protection • Available in 6-pin 3x3mm QFN

17.2 Pinning

Pin #

Name Description

1 FB Feedback input. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage.

2 GND, Exposed

Pad

Ground pin. Connect exposed pad to ground plane for proper thermal performance.

3 SW Switch node to the inductor. 4 PVIN Input supply pin for power FET. 5 VIN Input Supply pin for controller. Put small

decoupling ceramic near this pin. 6 EN Enable input, “High” enables MP2012. EN is

pulled to GND with 1Meg internal resistor.

18 RTA8283A (U23, U173)

18.1 General description The RT8283A is a high-efficiency, monolithic synchronous step-down DC/DC converter that can deliver up to 3A output current from a 4.5V to 23V input supply. The RT8283A's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. The RT8283A also provides output under voltage protection and thermal shutdown protection. The low current (<3μA) shutdown mode provides output disconnect, enabling easy power management in batterypowered systems. The RT8283A is available in a SOP-8 package.

18.2 Features • ±1.5% High Accuracy Feedback Voltage • Integrated N-MOSFET Switches • Current Mode Control • Fixed Frequency Operation : 340kHz • Output Adjustable from 0.8V to 20V • Up to 95% Efficiency • Thermal Shutdown Protection

18.3 Pinning

Pin No. Pin

Name Description

1 BOOT Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW pins.

2 VIN Input Supply 4.5V to 23V. Must bypass with a suitably large ceramic capacitor.

3 SW Phase Node--Connect to external L-C filter.. 4, 9 (Exposed

Pad) GND Ground.

5 FB Feedback Input pin is connected to the converter output. It is used to set the output of the converter to regulate to the desired value via an internal res divider. For an adjustable output, an external res divider is connected to this pin.

6 COMP Compensation Node. COMP is used to compensate the regulation Control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required.

7 EN Enable Input Pin. Logic high enables the converter; a logic low forces the RT8253A into shutdown mode. Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup.

8 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 13.5ms.

19 MP1583 (U174)

19.1 General description The MP1583 is a step-down regulator with a built-in internal Power MOSFET. It achieves 3A of continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. An adjustable soft-start reduces the stress on the input source at start-up. The MP1583 requires a minimum number of external components, providing a compact solution.

19.2 Features • 3A Output Current • Programmable Soft-Start • 100mΩ Internal Power MOSFET Switch • Stable with Low ESR Output Ceramic Capacitors • Up to 95% Efficiency • 20μA Shutdown Mode • Fixed 385KHz Frequency • Thermal Shutdown • Cycle-by-Cycle Over Current Protection • Wide 4.75V to 23V Operating Input Range • Output Adjustable from 1.22V to 21V • Under-Voltage Lockout

19.3 Pinning

Pin No.

Pin Name

Description

1 BOOT High-Side Gate Drive Bootstrap Input. BS supplies the drive for the high-side N-Channel MOSFET switch.

2 IN Power Input. Drive IN with a 4.75V to 23V power source. 3 SW Power Switching Out is the switching node that supplies power to the

output 4 GND Ground. 5 FB Feedback Input. FB senses the output voltage and regulates it. Drive

FB with a resistive voltage divider from the output voltage. FB threshold is 1.222V.

6 COMP Compensation Node is used to compensate the regulation control loop.

7 EN Enable/UVLO. A voltage greater than 2.71V enables operation. For complete low current shutdown the EN pin voltage needs to be at less than 900mV. When the voltage on EN exceeds 1.2V, the internal regulator will be enabled and the soft-start capacitor will begin to charge. The MP1583 will start switching after the EN pin voltage reaches 2.71V.

8 SS Soft-Start Control Input. SS controls the soft-start period.

20 FDC642

20.1 General description This P-Channel 2.5V specified MOSFET is produced using Fairchild’s advanced PowerTrench® process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance.

These devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the larger packages are impractical.

20.2 Features • Max rDS(on) = 65 mΩ at VGS = -4.5 V, ID = -4.0 A • Max rDS(on) = 100 mΩ at VGS = -2.5 V, ID = -3.2 A • Fast switching speed • Low gate charge (11nC typical) • High performance trench technology for extremely low rDS(on) • SuperSOTTM-6 package: small footprint (72% smaller than standard

SO-8); low profile (1 mm thick) • Termination is Lead-free and RoHS Compliant

20.3 Pinning

21 FDC604P

21.1 General description This P-Channel 1.8V specified MOSFET uses Fairchild’s low voltage PowerTrench process. It has been optimized for battery power management applications.

21.2 Features • –5.5 A, –20 V. RDS(ON) = 33 mΩ @ VGS = –4.5 V • RDS(ON) = 43 mΩ @ VGS = –2.5 V • RDS(ON) = 60 mΩ @ VGS = –1.8 V • Fast switching speed. • High performance trench technology for extremely low RDS(ON)(S)

21.3 Pinning

22 Connectors

22.1 SCART (SC1)

22.2 HDMI (CN707, CN708)

-.

22.3 VGA (CN711) 15.

14. VERTICAL SYNC 15. DOC CLOCK _.

23 Service menu mode

To enter the service menu, press MENU-4-7-2-5 keys consecutively, on the remote control. The top-level service menu will appear. All submenus can be selected via Up/Down keys and displayed by pressing OK key. When a submenu is displayed, top-level service menu disappears. Pressing RETURN key, returns to the one level higher menu. Pressing the MENU key will exit service menu.

Some items are changeable at service menu, the values of which are stored in the NVM when the menu is closed. Some items are read-only, which can only be changed by Profile Manager and displayed in service menu for convenience.

23.1 Main service menu Service menu or a sub-menu is displayed on the screen when the TV is in one of the TV/AV/PC modes. It shows what the items are set in Profile Manager. It is a read-only screen, not writable.

It shows the following items:

TV Life Time: The number of minutes the set is in the “On” mode.

Standby SW Version: The version number of the Stand-by software.

Mboot Version: The version number of the Mboot software.

PANEL: The LCD panel identification including the software version information.

PQ: Picture quality tool version information.

PROFILE: TV specific option profile

PIX FILES: Not applicable

HW Profile Version: The version number of the hardware profile.

SW Profile Version: The version number of the software profile.

Lan Profile Version: The version number of the Lan profile.

Customer: Philips

Items exist in the main screen of service menu. Also, software version number and DCF id are written in the header of service menu.

The main items in Service Menu:

23.2 Video Settings RF AGC adjustments for neighbour and image channels exist or don't. Also, ADC Calibration gain

and offset values for RGB separately due to selected sources

23.3 Audio Settings Surround type and surround mode text items are displayed.

23.4 Options 1 Profile options such as AUTO TV off time, Power up mode, EPG type, etc. are displayed in options 1.

23.5 Options 2 Profile options such as APS sorting, Dynamic Menu, Auto zoom mode etc. are displayed in Options 2.

23.6 Tuning Settings Tuner type is displayed.

23.7 Source Settings Enable and disabled sources are displayed.

When TV is disabled, Items which are connected to Tuner are picked off from menu. (Install and Retune Menu, Channel List Menu...).

23.8 Diagnostic The result of various diagnostic tests are displayed here.

23.9 USB operations USB operations are performed by pressing that button.

See Service Menu Design Idea for Menu structure, look and feel, position, etc…

Video Settings • RF AGC SECAM

• RF AGC NEIGHBOUR NO IMAGE NO

• RF AGC NEIGHBOUR NO IMAGE YES

• RF AGC NEIGHBOUR YES IMAGE NO

• RF AGC NEIGHBOUR YES IMAGE YES

• RF AGC

• ADC Calibration Source

• ADC Calibration R Gain

• ADC Calibration G Gain

• ADC Calibration B Gain

• ADC Calibration R Offset

• ADC Calibration G Offset

• ADC Calibration B Offset

Audio Settings • Surround Type

• Surround Mode Text

Options 1 • Auto TV OFF

• Power Up mode

• Backlight Trick Mode

• Cable Support

• EPG Type

• Hotel Mode

• LCN

• PC Standby

• Stby Search

• Test Tool

• Local Key

• Volume Level

Options 2 • Aps Sorting

• Dynamic Menu

• EPG Menus

• Transparent Text

• HDMI Number

• Remote control type

• DCF ID

Tuning Settings • Tuner Type

Source Settings • TV

• EXT1

• EXT2

• EXT2-S

• FAV

• S-VIDEO

• HDMI 1

• HDMI 2

• HDMI 3

• HDMI 4

• YPBPR

• VGA/PC

• Blu-ray

Diagnostic • Remote control test

• UHF test

• VHF test

• Factory reset

• Tuner I2C

• IF I2C

• HDMI I2C

• Ethernet

• EDID Status

• HDCP Status

• DDR Settings

• CI+ Credentials

• MAC Address

USB Operations Press this button to perform USB operations.

USB stick should be connected before this operation.

23.10 Profile Operations VES1.1E LA profile data are kept in the flash file system as separate files. So they can be downloaded to USB memory stick or uploaded to TV from a memory stick individually.

23.10.1 Upload profile Data from USB 1. Create a folder named profile in the USB stick. 2. Copy mb62_swprofile.bin and mb62_hwprofile.bin into the USB profile folder. 3. Plug the USB stick into the TV. 4. Open service menu and select “USB Operations”.

The files will be automatically copied to the TV flash file system.

After a reboot, App/Mw will start to use new profiles. It is possible to upload hardware or software profiles separately.

23.10.2 PQ Files Operations It is also possible to download/upload PQ files from/into the SSB when USB Operations button in service

menu is pressed.

Whenever a USB stick is connected to TV set and USB Operations button in service menu is pressed, /pq folder is checked.

If it exists and if they include some files, necessary copy/delete operations are performed.

23.10.3 Upload PQ files from USB

1. Create a folder named “pq” in the USB stick. 2. Copy VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin and Titania2_Main_Text.bin into USB “pq”

folder. 3. Connect USB stick to TV. 4. Open service menu, select “USB Operations”.

The files named VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin, Titania2_Main_Ex.bin and Titania2_Main_Text.bin will be copied from USB to TV.

23.10.4 Ci+ credentials key update 1. Create a “spi” folder in root of the memory stick 2. Copy mb62_credentials.bin to “spi” folder 3. Connect the USB stick to the TV.

4. Perform USB Operations in the service menu.

23.10.5 HDCP keys update 1. Create a “spi” folder in root of the memory stick. 2. Copy “mb62_hdcp.bin” to “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

23.10.6 Edid update 1. Create a “spi” folder in root of the memory stick. 2. Copy “edid.edid” to the “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

23.10.7 DDR settings update 1. Create a “spi” folder in root of the memory stick. 2. Rename the ddr binary file to be used which resides in the config_mb62 folder as mb62_ddr.bin. 3. Copy the file “mb62_ddr.bin” to the “spi” folder. 4. Connect the USB stick to the TV. 5. Perform USB operations in the service menu.

23.10.8 MAC address update 1. Create “spi” folder in root of the memory stick. 2. Copy the file “mb62_mac.bin” to the “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

23.11 Hotel Mode setup menu The hotel mode setup menu has a normal and a high security mode.

To enter the hotel mode setup menu of a set in the normal security mode, press “MENU 7935” on the remote control belonging to this set.

To enter the hotel mode setup menu of a set in the high security mode, the yellow service remote control is needed. To navigate through the menu, the remote control that belongs to the set is needed. To enter the hotel mode setup menu on a set with high security mode, first put the yellow remote in RC5 mode and then press the “Home/Menu” button.

• Note: To order a yellow remote, use order code: 22AV8573/00 or 12NC 8670 000 67389.

23.11.1 Hotel TV welcome image update (only available in Hotel TVs) In the VES1.1E LA the welcome image can be updated: Copy To USB There are two steps and both are independent of each other. Copy the updated welcome image to USB as “hotel_wel.png”. Copy NVRAM data (service list, preferences, etc.) to the USB device. In this chassis all nvram data is stored in 8 × 32KB Flash files named as Flash0.bin, Flash1.bin ... Flash7.bin. When a Copy to USB is called, those files are copied from TV to USB. Then they can be used for various purposes testing on another TV or testing/debugging on observatory etc. Note that USB should be plugged before this operation. Copy From USB There are two steps and both are independent of each other. If there is file named “hotel_wel.png” in directory “welcome_image”. It is copied to the tv to use as welcome image. Copy from USB device data to NVRAM. Just the reverse operation is done by a copy to USB call. Previously copied nvram files (Flashx.bin) are copied into TV. If there is no flash file or some of them are available on USB, the available ones are copied. If no USB is connected, nothing happens. • Note: For the clone function a USB stick (Copy to USB – Copy from USB) must be formatted to FAT32. If the USB stick is not formatted to FAT32 the other TVs will not accept cloned data and cause performance issues.

24 Software update In the VES1.1E LA there is only one software package. From following steps software update procedure can be seen:

1. MB62_en.bin, mboot.bin and usb_auto_update_T4.txt documents should copy directly inside of a

flash memory(not in a folder). 2. Put flash memory to the tv when tv is powered off. 3. Power on the and wait when the tv is opened. 4. If first time installation screen is displayed, it means the software update procedure is successful.

25 Troubleshooting

25.1 No backlight problem Problem: If TV is working, led is normal and there is no picture and backlight on the panel.

Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin

Backlight pin should be high in open position. If it is low, please check Q181 and panel cables.

Dimming pin should be high or square wave in open position. If it is low, please check S16 for Mstar side and panel or power cables, connectors.

Backlight power supply should be in panel specs. Please check CN705 for the SSB, related connectors for power supply cards.

STBY_ON/OFF should be low for standby on condition, please check R1677.

25.2 CI module problem Problem: CI is not working when CI module inserted.

Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins CI supply shoul be 5V when CI module inserted. If it is not 5V please check CI_POWER_CTRL, this pin should be low.

PCM D7

".

Please check mechanical positions of the CI module.

Detect ports should be low. If it is not low please check the Cl connector pins, Cl module pins and 3V3_VCC on the SSB.

R1632

PCM D3 PCM D4

4 PCM DS

Cl Detect PCM D6

7 PCM CB N 8 PCM AlO

PCM OB_N 10 PCM All 11 PCM A9 12 PCM AS 13 PCM A13 14 PCM A14 3V3_VCC

21 22 23 12p 24 sov 25

27 28 29

Cl Detect 30

'A 31

25.3 LED blinking problem Problem: LED blinking, no other operation

This problem indicates a short on Vcc voltages. Protect pin should be logic high while normal operation. When there is a short circuit protect pin will be logic low. If you detect logic low on protect pin, unplug the TV set and control voltage points with a multimeter to find the shorted voltage to ground.

25.4 IR problem Problem: LED or IR not working Check LED card supply on the SSB.

LED SOCKET Ql70

L--<J SV STBY F259

+----·2-- - -·[>IR IN C949 600R

· H

N

Ql7l

25.5 Keypad touchpad problems Problem Keypad or Touchpad is not working.

@ .-< BC949B

Check keypad supply and keyboard pin on the SSB.

25.6 USB problems Problem: USB is not working or no USB Detection.

Check USB Supply, It should be nearly 5V.

25.7 No sound problem Problem: No audio at main TV speaker outputs.

Check supply voltages of VDD_AUDIO, 5V_VCC and 3V3_VCC with a voltage-meter. There may be a problem in headphone connector or headphone detect circuit (when headphone is connected, speakers are automatically muted). Measure voltage at HP_DETECT pin, it should be 3.3v.

25.8 No sound problem at headphone Problem: No audio at headphone output.

Check HP detect pin, when headphone is. Check 5V_VCC and 3V3_VCC with a voltage- meter.

25.9 Standby On/Off problem Problem: Device cannot boot, TV hangs in standby mode.

There may be a problem about power supply. Check 12V_VCC, 5V_VCC and 3V3_VCC with a voltage-meter. Also there may be a problem about SW. Try to update TV with latest SW. Additionally it is goood to check SW printouts via hyper-terminal (or Teraterm). These printouts may give a clue about the problem.

25.10 DVD problems Problem: DVD is not working.

Check that DVD source is selected in Service menu. Check supply voltage of DVD namely 12V_VCC.

25.11 No signal problem Problem: No signal in TV mode. Check tuner supply voltage; 3V3_TUN. Check tuner options are correctly set in Service menu. Check AGC voltage at IF_AGC pin of tuner.

26 Styling sheet

1

1

DISPLAY ASM 32" LED

8

METAL FRAME 32" LED

SCREW P C ZN YFMB 3 x 9.5

1

IR

17LD98 1

1

1

3

5

6

7

11

9

10

2

1COVER FOOT

2ASM

BACK COVER 32130 LED DVD 1

4

8

BACK COVER METAL 32130

SCREW P C ZN Y

1011

1

2

27 Schematics

27.1 SSB

4k7

R16

12

5V_V

CC

BC848BQ172 ANT_CTRL

FDN336PQ175

10kR1590

3V3_S2_TUN

R15811k

10kR1595

16VC29 10n

S2_AGC

12V_VCC

1kR31

10n16V

C25

R2210k

R159

310

k

F1

60R

TSMISYNC

TSMICLK

3V3_S2_VDDD

SUT-

RE21

6TU

3

5

4

3

2

1

6

7

8

9IF_AGC

IF_P

IF_N

RESET

ANT-DC

+3V3

SCL

SDA

GND

R321k

C26 16V

10n

3V3_S2_TUN

S2_QP

S2_QN

S2_IN

S2_IP

3V3_S2_TUN

C24

50V

27p

M88DS3002

U3

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

32313029282726252423222120191817

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49505152535455565758596061626364N

C5

GPO

VCC_

10 NC4

NC3

VDD

D_4

NC2

NC1

NC9

NC8

LOCK

VCC_

9

LNB_

EN

CKXT

AL_

13 OLF

GN

DD

M_CKOUT

M_SYNC

VCC_8

M_VAL

M_ERR

M_DATA7

M_DATA6

VDDD_3

M_DATA5

M_DATA4

VCC_7

M_DATA3

M_DATA2

M_DATA1

M_DATA0

VCC_6

AA

GC

SCLT

SDA

T

VCC_

3

SDA

SCL

VDD

D_2

AD

DR_

SEL1

AD

DR_

SEL0

VCC_

4

VSEL

DIS

EQC_

IN

DIS

EQC

VCC_

5

CKXT

AL_

27

RESE

T

GNDA_1

XTAL_IN

XTAL_OUT

VDDA_1

GNDA_2

IP

IN

VDDA_2

GNDA_3

QN

QP

NC6

VDDD_1

VCC_1

VCC_2

NC7

LNB_OUT1n

C16

50V 50VC17

1n

50VC18

1n

1V25

_S2_

VDD

I3V3_S2_TUN

R159410k

27MHz

X1

31 42

50V

C23

27p

OVER_CUR_DETECT

3V3_S2_VDDA

3V3_S2_TUN

3k3R39

C2716V

10n

S5 12

S11 12

C965

16V100n

47RR27

R2847R

S12

12

1V2_VCC

F2

60R

S20

12

3V3_VCC

F3

60R3V3_VCC

10n16V

C28

100n

10V

C44

10V

C45

100n

SDA_S2_TUN

R3533R

33RR36

SCL_S2_TUN

S2_IP

20k

R158

6

C21

50V

27p

27p

50V

C22

3V3_

S2_T

UN

3V3_

S2_T

UN

M88TS2022

U4

28272625242322

21

20

19

18

17

16

15

891011121314

1

2

3

4

5

6

7VDDA2

CK_OUT

IP

IN

VDDA1

QN

QP

VDD

A4

TEST

1

TEST

2

TEST

3

VDD

A3

XTA

LN

XTA

LP

RES

CAP

CKDIV_OPT

RFBYPASS

RESET

LNA_IN

TEST

VDA

A5

VDD

_DIG

SDA

SCL

VDD

_REG

AG

C

VDD

A6

S138 12

2R1

TH1

CN17

S25

1

2

50V

C62

2p2

C63

2p250V

33p

C35

50V

50V

1n

C19

10k

R4

L1

4n7

IF_AGC_TUNER

47R

R15831

2

3

45

6

7

8

R4

R1

R3

R2

TS_MDI3

TS_MDI2

TS_MDI1

TS_MDI4

TS_MDI5

TS_MDI6

TS_MDI7

3V3_S2_VDDA

10p

C8

10p

C9

S2_INC30

16V

10n

10nC31

16V

C32 10n16V

S2_QN

10p

C10

C11 10

p

S2_QP

3V3_S2_VDDD

10V

C38

100n

1V25_S2_VDDI

1V25_S2_VDDI

3V3_S2_VDDA

10V

C36

100n

100nC3

710

V

SDA_S2_TUN

SCL_S2_TUN

R13

4k7

12

4k7

R14

12

3V3_S2_VDDD

C910

10V100n

1

2

TS_MDI0

100nC912

10V1

2

R158447R

1

2

3

45

6

7

8

R4

R1

R3

R2

10kR1597

IF_AGC_MSTC2

0

50V

1n

Ulas DereliTUNER&S2_TUNER&DEMOD 8

17mb62-1

87654321

A

B

C

D

E

F

A X M

1 2 3 4 5 6 7 8

A

B

C

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F

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SCH NAME :

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S41

S40

TP471

TP481

TUN_SCL

R2947R

TUN_SDA

TUN_SDA

33pC3

450

V

TUN_SCLACTIVE_ANT_SUPPLY

C904100n

10V1

2

TUN_SCL_MST

10V

100nC5

2

C53

100n

10V

C54

10V

100n

10V

C55

100n

100n

10V

C56

10V

100nC5

747RR30

60R

F43V3_VCC

1k

F304

D20

6

C5V6

TUN_SDA_MST

3V3_S2_TUN

16V22u

C60

3V3_S2_VDDD

FK16

01TU

1

5

4

3

2

1

6

7

8

9IF_AGC

IF_P

IF_N

CLK_OUT

ANT-DC

VCC

SCL

SDA

GND

ACTIVE_ANT_SUPPLY

C61

6V322u

C5822u6V3

22u6V3

C59

3V3_TUNER

DIGITAL_IF_N

DIGITAL_IF_P

IF_AGC_TUNER

27M

Hz

X3

31

42

100RR1963

1 2

10n

C33 16V

18p

C72

50V

S2_AGCR442k

R15

4k7

12

3V3_TUNER

IF_AGC_TUNER

3V3_

S2_V

DD

D

TSMIVALID

DIGITAL_IF_P

DIGITAL_IF_N

SDA_SYS

SCL_SYS

50V18p

C73

33RR3733RR38

100n

10V

C39

C40

10V

100n

3V3_

S2_V

DD

D

C46

10V

100n

10V

C47

100n

1V25

_S2_

VDD

I

DIS

EQC_

OU

T

10V

C48

100n

100n

10V

C49

1V25

_S2_

VDD

I

ACTIVE_ANT_SUPPLY

RESET_S2

C50

100n

10V

1V25_S2_VDDI

1V25_S2_VDDI

1V25_S2_VDDI

3V3_S2_VDDD

47RR26

1V25_S2_VDDI

50V12p

C71

1V25

_S2_

VDD

I

3V3_

S2_V

DD

D

1V25

_S2_

VDD

I

10V

C41

100n

10V

C42

100n

100n

10V

C43

RESET_TUNER

SONY TUNER

NC

NUTUNE/SEMCO/LG

NC

NC

0.5pF

3.3pF

27 MHZ KULLANILACAK

NC

NCNCNCNC

00 SEÇILDI WRITE:D0H READ:D1H

KONTROL EDILECEK

NC

NC

NU

P400

4M5

D5

543

2

1CN711

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R1505470R

75R

R147

91

2

F179

1k

DVD_IR

DVD_IR_ON/OFF

3V3_VCC4k7R694

12

47k

R498

12

Q15

7BC

848B

1

2

3IR_IN

TP2451

CDA4

C16G

TH

D4

12345 6 7 8

12V_VCC

DVD_CVBS_INR1650180R

75RR1652

S801 2

DVD_WAKEUP

FS1

4A/24VDC

1 2

TP2501

R197433R

R197533R

50V

27p C8

28

12

CN7041 2

3 4

5 6

7 8

9 10R161

64k

71

2

DVD_SPDIF

100RR1624

1 2

10V

100n

C628

12

DVD_SENSE

50V

27p

C650

12

TP2471

DVD_IR

C972

50V220pR1623

100R

R197633R

TP491

2k7

R120

9

TP50

1

U5

MSD9WB9PT-2

K2

K3

J2

J3

H1

H3

H2

L6

L5

L3

K1

M3

L2

N3

M2

L1

M5

N4

R2

R3

P2

P1

N1

N2

P3

T1

U2

U3

V2

T3

T2

U1VCOM

CVBSOUT0

CVBS4

CVBS3

CVBS2

CVBS1

CVBS0

SOGIN2

BIN2P

BIN2M

GIN2P

GIN2M

RIN2P

RIN2M

VSYNC1

HSYNC1

SOGIN1

BIN1P

BIN1M

GIN1P

GIN1M

RIN1P

RIN1M

VSYNC0

HSYNC0

SOGIN0

BIN0P

BIN0M

GIN0P

GIN0M

RIN0P

RIN0M

5

SCART_AUD_R_IN

RCA_Y

220RR124

C88447n

16V

Ulas DereliPERIPHERALs 8

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B

C

D

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50V

C823

27p

12

27p

C829

50V

12

RCA_PR

RCA_PB

JK1

7

6

5

4

3

2

1

TP24

21

TP21

TP31

TP131

R161

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2

S91 2

47n

C88216V

JK3

7

6

5

4

3

2

1

R162

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R1

2

S421 2

JK4

12

34

56

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RED

VGA_VSNC

VGA_HSNC

5V_VCC

2k7

R120

6

D3

CDA4

C16G

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265

10k

12

R131

010

k1

2

10V

C663100n

1

2

VGA_B

VGA_R

VGA_G

10k

R131

11

2

75R

R162

01

2

16V

C80747n

16V

47n

C806

C80216V47n

C88116V47n

1nC859

50V

C81016V47n

R104

33k

100RR1243

68k

R103

SC_CVBS_OUT

Q119BC848B

1

2

3

390R

R102

SCART_CVBS_OUT

12V_VCC

BC858BQ146

1

2

3

10V10u

C378

16V

C120

100n

C5V6

D17

1

3n3

C85650V

F202

600R1 2

CDA4

C16G

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4n750V

C858

SC_AUD_R_OUT

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C16G

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12345 6 7 8

C85350V

3n3

C835

50V

220p

12

C833

50V220p

12

3n3

C85450V

SC_AUD_R_IN600R

F2061 2

C831

220p50V

12

100RR1245

1 2

F201

600R1 2

SCART_AUD_R_IN

SCART_AUD_L_IN

RX/SCL_SC

TX/SDA_SC

C836220p50V

12

75RR1482

12

SC_CVBS_OUT

C832

50V220p

12

R11824k71 2

SC_PIN8

220RR1233

R221

100R

SC_CVBS_IN

SC_G

SC_R

SC_B

SC_FB

R148375R 12

10VC664

100n

12

D178

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12

22kR1187

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C857

4n750V

SC_AUD_L_OUT

F205

600R1 2

SC_AUD_L_IN

600R

F2001 2

100RR1244

1 2

SC1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

SCA

RT L

T1

R148

675

R2

600R

F2031 2

C830

220p 50

V

12

SAV_CVBS_IN

SAV_L_IN

SAV_R_IN

3n3

C855

50V

S391 2

47nC80916V

SAV_R

SAV_L

SAV_CVBS_INR142033R

47n16VC808

C8621n 50V

R140933R

16V C885

47n

SAV_L

VGA_R

VGA_G

VGA_B

VGA_HSNC

VGA_VSNC

1n50V

C861470R

R1423VGA_G

SC_R

SC_G

SC_B

SC_CVBS_IN

SC_FB

R141533R SC_CVBS_IN

SAV_CVBS_IN

C80016V

47n

16V C80347n

47n16V C804

100RR1949

47n16V C805

DVD_CVBS_IN

R151

675

R1

2

R142233R

RCA_Y

RCA_Y

RCA_PB

R148175R 12

RCA_PR

470RR1494

16V C88647n

16V47n

C883

R140833R

33RR1421

R141933R

16V47n

C798

C796

16V 47n

C79747n16V

R11

300R

SC_R

SCART_CVBS_OUT

75RR1480

12

75RR1489

12

16V47n

C795

33RR1413

47nC79916V

33RR1412

R141133R

16V C79447n

75R

R148

51

2

75R

R151

51

2

47RR1249

R151

775

R1

2

10uC973

16V

SCART_AUD_L_IN

SC_CVBS_IN

JK7

12

3

4YEL

WHT

RED

TP381

TP44 1

TP42 1

TP4 1

R158775R

TP431

TP11

TP51

16V

47n

C959

33R

R153

0

47p

C860

50V

R620100R

SAV_R

SCART

DVD INTERFACE (for 26" to 32")

!

YPbPr Slim INPUT

INDIA OPTION

SCART VIDEO OUTPUT AMPLIFIER

SAV Slim INPUT

SAV RCA INPUT

PC INPUT

1UF

62R

62R

62R

SC SVHS opt

62R

30064869

NC

30062423

30062840

Ulas Dereli

17mb62-18RAM&NAND&CI

87654321

A

B

C

D

E

F

A X M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

OF:

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

SHEET:

14-03-2011_17:06

R195010k

4k7

R8 R94k7

3V3_VCC

4k7R1971

R166

34k

71

2

R161

84k

71

2

TUN_SCL_MSTTUN_SDA_MST

1V8_VCC DDR18V

R104k7

16V

100n

C913

330R

F812

3V3_TUNER

IF_AGC_MST

R12

4k7

22RR1313

22RR1986

R198722R

22RR1984

R198522R

22RR1603

F181

60R

R1613

22R

1234 5

678R1

R2R3R4

OVER_CUR_DETECT

R1610

22R

1234 5

678R1

R2R3R4

50V4p7

C967

3V3_VCCR1172

4k7

33RR1425

R142733R

100RR5 C905

10V100n

R3333R

C712

10V100n

1

2 C709

10V100n

1

2 C710100n10V

1

2

R6100R

VCC_PCMCIA

10V220n

C1214

DDR18V

AVDD_DDR

R135

61k

22R

R13671234 5

678R1

R2R3R4

1kR1365

DDR18V

1kR1

355

220n10V

C683

1kR1364

C715220n

10V220n

10V

C714

10V220nC716 C711

220n10V

C713

10V220n

DDR18V

C5V6

D20

5

22RR1982

R1380

22R

1234 5

678R1

R2R3R4

R1370

22R

1234 5

678R1

R2R3R4

R1366

22R

1234 5

678R1

R2R3R4

R1609

22R

1234 5

678R1

R2R3R4

22R

R13691234 5

678R1

R2R3R4

U15

5H

Y5PS

1216

21C

J1 R1 M9

J9 E1 A1

G9

G7

G3

G1

E9 C9 C7 C3 C1 A9

J2 J7 H8

H2

F8 F2 E7 D8

D2

B8 B2 A7

P9

N1

J3

E3

A3

K9

K8

J8

K2

L8

K3

L7

K7

L3

L2

R2

P7

M2

P3

P8

P2

N7

N3

N8

N2

M7

M3

M8

R8

R7

R3

L1

E2

A2

B3

A8

B7

B9

B1

D9

D1

D3

D7

C2

C8

F9

F3

E8

F7

F1

H9

H1

H3

H7

G2

G8 DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

LQDS

LQDS_P

LDM

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UDQS

UDQS_P

UDM

NC1

NC2

NC3

NC4

NC5

NC6

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

BA0

BA1

RAS_P

CAS_P

WE_P

CS_P

CKE

CK

CK_P

ODT

VSS1

VSS2

VSS3

VSS4

VSS5

VSSQ

1

VSSQ

2

VSSQ

3

VSSQ

4

VSSQ

5

VSSQ

6

VSSQ

7

VSSQ

8

VSSQ

9

VSSQ

10

VSSD

L

VREF

VDD

Q1

VDD

Q2

VDD

Q3

VDD

Q4

VDD

Q5

VDD

Q6

VDD

Q7

VDD

Q8

VDD

Q9

VDD

Q10

VDD

1

VDD

2

VDD

3

VDD

4

VDD

5

VDD

L

3V3_VCC

R151333R

C906

10V100n

U5MSD9WB9PT-2

C10D21A9

E20B9

E19C9

F20B8

F19D20C8

F21

C13A19A12B19A20B12C19A13B14C18C14A18B18B13B17C15

A16C16A15B15

B16C17

C12B11C20

B20B10A10C21B21D19C11

F18MVREF

A_ODTA_BADR[2]A_BADR[1]A_BADR[0]

A_CASZA_RASZ

A_WEZ

A_MCLKEA_MCLKZ

A_MCLK

A_DQM[1]A_DQM[0]

A_DQSB[1]A_DQS[1]

A_DQSB[0]A_DQS[0]

A_MDATA[15]A_MDATA[14]A_MDATA[13]A_MDATA[12]A_MDATA[11]A_MDATA[10]

A_MDATA[9]A_MDATA[8]A_MDATA[7]A_MDATA[6]A_MDATA[5]A_MDATA[4]A_MDATA[3]A_MDATA[2]A_MDATA[1]A_MDATA[0]

A_MADR[12]A_MADR[11]A_MADR[10]

A_MADR[9]A_MADR[8]A_MADR[7]A_MADR[6]A_MADR[5]A_MADR[4]A_MADR[3]A_MADR[2]A_MADR[1]A_MADR[0]1

BSH

103

Q20

9

R138533R

12345

678 R1

R2R3R4

R11714k7

R151433R

33RR1402

R198322R

U5MSD9WB9PT-2

K21L19M19T12U13V14V12V18

R19P19N21N19V20U20T20T19P17N18U17V16R20R17T16V19

W21U16V17T17V21T14M21P16N20

G21G20G19

U10T9

V11U11U9

T10V9

P18R18T18W19Y21Y19R21T21Y20W20R16

K20L20M20T13U14U12T11U18U19P20K19

W1Y1

AA2Y2

Y3AA3

W5W4

AA4Y4W6Y5GPIO69

GPIO68GPIO67GPIO66

RF_AGCIF_AGC

SIFMSIFP

VIFMVIFP

IMIP

TS0SYNCTS0VALID

TS0CLKTS0DATA[7]TS0DATA[6]TS0DATA[5]TS0DATA[4]TS0DATA[3]TS0DATA[2]TS0DATA[1]TS0DATA[0]

TS1SYNCTS1VALID

TS1CLKTS1DATA[7]TS1DATA[6]TS1DATA[5]TS1DATA[4]TS1DATA[3]TS1DATA[2]TS1DATA[1]TS1DATA[0]

F_RBZ/GPIO136PF_WEZ/GPIO134PF_OEZ/GPIO133PF_CE1Z/GPIO132PF_CE0Z/GPIO131PF_AD[15]/GPIO130PF_ALE/GPIO135

GPIO127GPIO128GPIO125

PCMREG/CI_CLKPCMIOW/CI_WRPCMWAIT/CI_WACKCI_CDPCMWENPCMCEN/CI_CSPCMIOR/CI_RDPCMOENPCM_IRQ/CI_INT

CI_RSTPCMADR[14]/CI_A[14]PCMADR[13]/CI_A[13]PCMADR[12]/CI_A[12]PCMADR[11]/CI_A[11]PCMADR[10]/CI_A[10]PCMADR[9]/CI_A[9]PCMADR[8]/CI_A[8]PCMADR[7]/CI_A[7]PCMADR[6]/CI_A[6]PCMADR[5]/CI_A[5]PCMADR[4]/CI_A[4]PCMADR[3]/CI_A[3]PCMADR[2]/CI_A[2]PCMADR[1]/CI_A[1]PCMADR[0]/CI_A[0]

PCMDATA[7]/CI_DATA[7]PCMDATA[6]/CI_DATA[6]PCMDATA[5]/CI_DATA[5]PCMDATA[4]/CI_DATA[4]PCMDATA[3]/CI_DATA[3]PCMDATA[2]/CI_DATA[2]PCMDATA[1]/CI_DATA[1]PCMDATA[0]/CI_DATA[0]

2

DIGITAL_IF_N

180R

R197

7

VCC_PCMCIA

DIGITAL_IF_P

12V_VCC

33RR1395

12345

678 R1

R2R3R4

VCC_PCMCIAR1177

4k7

R19514k7

CN141123456789

10111213141516171819202122232425262728293031323334

35363738394041424344454647484950515253545556575859606162636465666768

BC848BQ208

1

2

3

VCC_PCMCIA

C966

50V12p

33RR1398

1

2

3

45

6

7

8

R4

R1

R3

R2

R164210k3V3_VCC

3V3_VCC 10kR1632

PCM_CD1_N

C96812p50V

33RR1394

12345

678 R1

R2R3R4

33RR1399

12345

678 R1

R2R3R4

R139633R

12345

678 R1

R2R3R4

R139733R

12345

678 R1

R2R3R4

33RR1392

12345

678 R1

R2R3R4

R140133R

5V_VCC

33RR1424

R139333R

12345

678 R1

R2R3R4

33RR1384

1234 5

678R1

R2R3R4

R139033R

12345

678 R1

R2R3R4

R151233R

10V

C653100n

1

2

10V

C654100n

1

2

R19534k7

3V3_VCC

CI_POWER_CTRL

50V

C96912p

C687

10V220n

R149

64k

7

3V3_VCC

R166

04k

71

2

33RR1942

6V322uC970

BACKLIGHT_ON/OFFR3441k2

33k

R160

5

R160

433

k

R160718k18k

R1606HDMI1_5VHDMI0_5V

BC848BQ181

1

2

3

R16614k71 2

R166

21k

23V

3_VC

C

S81

U162

NAND512-A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24 25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48NC29

NC28

NC27

NC26

I/O7

I/O6

I/O5

I/O4

NC25

NC24

NC23

VDD2

VSS2

NC22

NC21

NC20

I/O3

I/O2

I/O1

I/O0

NC19

NC18

NC17

NC16NC15

NC14

NC13

NC12

NC11

WP

W

AL

CL

NC10

NC9

VSS1

VDD1

NC8

NC7

E

R

RB

NC6

NC5

NC4

NC3

NC2

NC1

PANEL_VCC_ON/OFF

100n

C122

0

10V

1 2

FLH_3.3V

F_RBZ

FLH_3.3V

R14953k9

3V3_VCC60R

F187

100n10V

C6561

2

100n10V

C6571

2

6V3

C86822u

FLH_3.3V

FLH_3.3V

FLH_3.3V

R138833R

12345

678 R1

R2R3R4

R138233R

12345

678 R1

R2R3R4

33RR1383

12345

678 R1

R2R3R4

R138933R

1

2

3

45

6

7

8

R4

R1

R3

R2

R3433R

4k7R47

4k7R48

R494k7

22uC782

6V3

22RR1332

220nC718

10V

R1368

22R

1234 5

678R1

R2R3R4

R504k7

FLH_3.3V

AA_DDR2_DQSB0

AA_DDR2_DQSB0

AA_BADR_BA2

AA_BADR_BA2

AA_MCLK

AA_MCLK

AA_MCLKZ

AA_MCLKZ

AA_DDR2_DQSB1

AA_DDR2_DQSB1

AA_DDR2_DQS1

AA_DDR2_DQS1

AA_DDR2_DQS0

AA_DDR2_DQS0

AA_DDR2_DQM0

AA_DDR2_DQM0

AA_DDR2_DQM1

AA_DDR2_DQM1

AA_BADR_BA0

AA_BADR_BA0

AA_BADR_BA1

AA_BADR_BA1

AA_ODT

AA_ODT

AA_WEZ

AA_WEZ

AA_RASZ

AA_RASZ

AA_CASZ

AA_CASZ

AA_MDATA15

AA_MDATA15

AA_MDATA14

AA_MDATA14

AA_MDATA13

AA_MDATA13

AA_MDATA12

AA_MDATA12

AA_MDATA11

AA_MDATA11

AA_MDATA10

AA_MDATA10

AA_MDATA9

AA_MDATA9

AA_MDATA8

AA_MDATA8

AA_MDATA5

AA_MDATA5

AA_MDATA2

AA_MDATA2

AA_MDATA0

AA_MDATA0

AA_MADR12

AA_MADR12

AA_MADR11

AA_MADR11

AA_MADR10

AA_MADR10

AA_MADR9

AA_MADR9

AA_MADR8

AA_MADR8

AA_MADR7

AA_MADR7

AA_MADR6

AA_MADR6

AA_MADR5

AA_MADR5

AA_MADR4

AA_MADR4

AA_MADR3

AA_MADR3

AA_MADR2

AA_MADR2

AA_MADR1

AA_MADR1

AA_MADR0

AA_MADR0

A_MADR12

A_MADR12

A_MADR11

A_MADR11

A_MADR10

A_MADR10

A_MADR9

A_MADR9

A_MADR8

A_MADR8

A_MADR7

A_MADR7

A_MADR6

A_MADR6

A_MADR5

A_MADR5

A_MADR4

A_MADR4

A_MADR3

A_MADR3

A_MADR2

A_MADR2

A_MADR1

A_MADR1

A_MADR0

A_MADR0

A_MDATA0

A_MDATA0

MVREF

MVREF

A_BADR_BA2

A_BADR_BA2

A_DDR2_DQSB1

A_DDR2_DQSB1

A_DDR2_DQS1

A_DDR2_DQS1

A_DDR2_DQSB0

A_DDR2_DQSB0

A_DDR2_DQS0

A_DDR2_DQS0

A_DDR2_DQM0

A_DDR2_DQM0

A_DDR2_DQM1

A_DDR2_DQM1

A_BADR_BA0

A_BADR_BA0

A_BADR_BA1

A_BADR_BA1

A_ODT

A_ODT

A_MCLKE

A_MCLKE

A_WEZ

A_WEZ

A_RASZ

A_RASZ

A_CASZ

A_CASZ

TS_MDI1

TS_MDI1

TS_MDI2

TS_MDI2

TS_MDI3

TS_MDI3

TS_MDI4

TS_MDI4

TS_MDI5

TS_MDI5

TSMICLK

TSMICLK

TSMIVALID

TSMIVALID

TS_MDI0

TS_MDI0

A_MDATA9

A_MDATA9

A_MDATA2

A_MDATA2

A_MDATA5

A_MDATA5

A_MDATA7

A_MDATA7

A_MDATA8

A_MDATA8

A_MDATA10

A_MDATA10

A_MDATA11

A_MDATA11

A_MDATA12

A_MDATA12

A_MDATA13

A_MDATA13

A_MDATA14

A_MDATA14

A_MDATA15

A_MDATA15

A_MCLKZ

A_MCLKZ

A_MCLK

A_MCLK

PCM_CD2_N

PCM_CD2_N

TSMOSTART

TSMOSTART

TSMOCLK

TSMOCLK

TSMOVALID

TSMOVALID

TS_MDO7

TS_MDO7

TS_MDO6

TS_MDO6

TS_MDO5

TS_MDO5

TS_MDO4

TS_MDO4

TS_MDO3

TS_MDO3

TS_MDO0

TS_MDO0

PCM_WE_N

PCM_WE_N

PCM_IORD_N

PCM_IORD_N

PCM_IOWR_N

PCM_IOWR_N

PCM_IRQA_N

PCM_IRQA_N

PCM_OE_N

PCM_OE_N

PCM_CE_N

PCM_CE_N

PCM_WAIT_N

PCM_WAIT_N

PCM_RST

PCM_RST

PCM_D0

PCM_D0

PCM_D1

PCM_D1

PCM_D2

PCM_D2

PCM_D3

PCM_D3

PCM_D6

PCM_D6

PCM_D7

PCM_D7

PCM_D5

PCM_D5

PCM_A8

PCM_A8

PCM_A9

PCM_A9

PCM_A11

PCM_A11

PCM_A12

PCM_A12

PCM_A10

PCM_A10

PCM_A14

PCM_A14

PCM_A13

PCM_A13

PCM_A7

PCM_A7

PCM_A7

PCM_A6

PCM_A6

PCM_A6

PCM_A5

PCM_A5

PCM_A5

PCM_A4

PCM_A4

PCM_A4

PCM_A3

PCM_A3

PCM_A3

PCM_A2

PCM_A2

PCM_A2

PCM_A1

PCM_A1

PCM_A1

PCM_A0

PCM_A0

PCM_A0

TS0_CLK

TS0_CLK

TS0_SYNC

TS0_SYNC

TS0_VALID

TS0_VALID

TS0_D7

TS0_D7

TS0_D6

TS0_D6

TS0_D5

TS0_D5

TS0_D4

TS0_D4

TS0_D3

TS0_D3

TS0_D2

TS0_D2

P_D0

P_D0

P_D1

P_D1

P_D2

P_D2

P_D3

P_D3

P_D5

P_D5

P_D6

P_D6

P_D7

P_D7

P_A0

P_A0

P_A3

P_A3

P_A4

P_A4

P_A5

P_A5

P_A6

P_A6

P_A7

P_A7

P_A8

P_A8

P_A9

P_A9

P_A10

P_A10

P_A11

P_A11

P_A12

P_A12

P_A13

P_A13

P_A14

P_A14

P_WAIT_N

P_WAIT_N

P_IOWR_N

P_IOWR_N

P_RESET

P_RESET

P_IRQA_N

P_IRQA_N

P_OE_N

P_OE_N

P_IORD_N

P_IORD_N

P_CE_N

P_CE_N

P_WE_N

P_WE_N

F_RBZ

PF_AD15

PF_AD15

PF_CE1Z

PF_CE1Z

PF_CE0Z

PF_CE0Z

PF_ALE

PF_ALE

PF_OEZ

PF_OEZ

PF_WEZ

PF_WEZ

TS1_D0TS1_D0TS1_D1TS1_D1TS1_D2TS1_D2TS1_D3TS1_D3TS1_D4

TS1_D4

TS1_D5

TS1_D5

TS1_D6

TS1_D6

TS1_D7

TS1_D7

TS1_CLK

TS1_CLK

TS1_VALID

TS1_VALID

TS1_SYNC

TS1_SYNC TSMISYNC

TSMISYNC

TS_MDI6

TS_MDI6

TS_MDI7

TS_MDI7

AA_MCLKE

AA_MCLKE

A_MDATA6

A_MDATA6

AA_MDATA6

AA_MDATA6A_MDATA1

A_MDATA1

AA_MDATA1

AA_MDATA1A_MDATA3

A_MDATA3

AA_MDATA3

AA_MDATA3A_MDATA4

A_MDATA4

AA_MDATA4

AA_MDATA4

AA_MDATA7

AA_MDATA7

P_REG_N

P_REG_N PCM_REG_N

PCM_REG_N

P_A1

P_A1

P_A2

P_A2

TS_MDO2

TS_MDO2

TS0_D0

TS0_D0TS_MDO1

TS_MDO1

TS0_D1

TS0_D1

PCM_D4

PCM_D4

P_D4

P_D4

NAND_ALE

NAND_ALE

NAND_CEz

NAND_CEz

NAND_CLE

NAND_CLE

NAND_WPz

NAND_WPz

NAND_WPz

9k1NC

NC

30022165 KULLANILDI

CI INTERFACE

NC

1k

0R

NAND FLASH

128

MEG

ABY

TE

TS IN& OUT

3V3_STBY

R1614

4k7

12

PROTECT

R1915

220k

C1177

100n16V

L120

4u7

SPDIF_OUT

AMP_MUTE

DVD_IR_ON/OFF

4u7

L119

3V3_STBY

10u 10VC119610V

C119510u

C1185

100p

50V

SAV_AUDIO_IN_LSAV_AUDIO_IN_R

C119810V10u

SCART_AUDIO_IN_L

R1838

10k

17mb62S

Ulas Dereli

8AUDIO_IO&HDMI_INPUTs

26-10-2011_15:43

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

T. SHT:

R1601

4k7

12

C15

16V

100n

600R

F512

220R

R1858

100u

C1169

16V

12

16V100u

C116812

CN707

12345678910111213141516171819

2021

HDMI_1_CLKP

HDMI_1_CLKN

HDMI_1_RX0P

HDMI_1_RX0N

HDMI_1_RX1P

HDMI_1_RX1N

HDMI_1_RX2P

HDMI_1_RX2N

HDMI_0_SCLHDMI_0_SDA

CEC

HDMI_1_SCLHDMI_1_SDA

HDMI1_5VHDMI1_HPD 10R

R188112

R188310R 12

R187110R 12

10RR1870

12

R187210R 2

10RR1884

1

R188210R 12

10RR1876

1

CECR187310R 12

R187510R 1

2

47k

R1862

12

47k

R1863

12

R187410R 1

R187710R 1

2

47k

R1864

12

R1865

47k

12

10RR1885

12

R188810R 12

10RR1879

12

R188610R 12

R186810R 1

2

10RR1867

12

10RR1869

12

R188710R 12

10RR1880

12

R187810R 12HDMI0_HPD

HDMI0_5V

HDMI_0_RX2P

HDMI_0_CLKP

HDMI_0_CLKN

HDMI_0_RX0N

HDMI_0_RX0PHDMI_0_RX1N

HDMI_0_RX1PHDMI_0_RX2N

MSD9WB9PT-2U5

E2F3F2G3G2G1E3E1H5H6J6

B2B1C2C1D2D1A2C3J5K4K5

H4

N5L4R5T6P6P5T4T5

N6R6W9AA9Y7AA7

U5U6U4

D4D6F4F5

E4C4D3

P4 SPDIFO

I2S_IN_WSI2S_IN_SDI2S_IN_BCK

I2S_OUT_BCKI2S_OUT_WSI2S_OUT_SDI2S_OUT_MCK

AUVRMAUVAGAUVRP

EAR_OUTREAR_OUTLAUOUTR1AUOUTL1AUOUTR0AUOUTL0

AUR3AUL3AUR2AUL2AUR1AUL1AUR0AUL0

CEC

HOTPLUGBDDCDB_DADDCDB_CK

RXBCKPRXBCKNRXB2PRXB2NRXB1PRXB1NRXB0PRXB0N

HOTPLUGADDCDA_DADDCDA_CK

RXACKPRXACKNRXA2PRXA2NRXA1PRXA1NRXA0PRXA0N

3

CN708

12345678910111213141516171819

2021

50V

C1183

4n7

R1897100R

R1899

220k

R1900100R

C1184

50V

4n7

220k

R1898

DSP_MAIN_R

DSP_MAIN_LMAIN_L

MAIN_R

R190410k

R1919

12k

470p

C1190

50V

10kR1903

R1918

12k

SC_AUD_L_IN 10kR1901

12k

R1920

470p

C1188

50V

SAV_L_IN

C1189

50V

470p

SC_AUD_R_IN

470p

50V

C1187

SAV_R_IN

R1921

12k

10kR1902

SCART_AUDIO_IN_R

SCART_AUDIO_IN_L

SAV_AUDIO_IN_L

SAV_AUDIO_IN_R

22k

R1925

12

R1924

22k

12

SC_R_OUT

SC_L_OUT

50V

100p

C1186

DSP_SCART_L

DSP_SCART_RR222100R 12

100RR223

12

3V3_STBY

SCART_AUDIO_IN_R10V10u

C1197

DSP_MAIN_R

HDMI1_HPD

HDMI0_5V

R1895

4k7

12

4k7

R1896

12

R19091k 12

Q204BC848B

1

2

3

1kR1910

12

BC848BQ203

1

2

3

R19121k 12

10V4u7

C1200

HDMI1_5V

1kR1911

12

HDMI0_HPD

R191710R 12

4k7

R1892

12

12V_VCCSTBY_INFO

10uC1182

10V

10V10uC1170

600R

F30112

12V_VCC

TL062

U1781

2

3

4 5

6

7

8VDD

OUT2

IN2-

IN2+VSS

IN1+

IN1-

OUT182kR1927

1 2

4k7

R17

12

3V3_VCC

DSP_MAIN_L

4k7

R1656

12

DSP_SCART_L

PL1

PL4

PL2

PL3

R191433k

12

47p50V

C1206

R192682k1 2

47p

C1205

50V

R191333k1 2

V+

V+

C1181

10V10u

SC_L_OUT20kR1928

1 2

SC_AUD_L_OUT

SC_AUD_R_OUT

1u

C1203

6V3

R192920k1 2SC_R_OUT

12V_VCCV+R1916220k

S921 2

Q202BC848B

1

2

3

50V

220p

C11781

2

C1202

6V31u

SPDIF_OUTR1907100R1 2

4k7

R1889

12

4k7

R1890

12

5V_VCC

C1175

100n10V

1 2

C1176

100n10V

1 2

C5V6

D199

12

220p50V

C1179

1 2

R1908

1k

12JK10

1

23

DSP_SCART_RDSP_HP_LDSP_HP_R

10k

R1840

100n16V

C1174 C12016V3

1u10VC119910u

3V3_VCC

HDMI_1_RX2P

ANT_CTRL

HDMI_1_RX2N

HDMI_1_RX1NHDMI_1_RX1P

HDMI_1_RX0NHDMI_1_RX0P

HDMI_1_CLKNHDMI_1_CLKPHDMI_1_SCLHDMI_1_SDA

HDMI_0_SDA

HDMI_0_CLKNHDMI_0_CLKP

HDMI_0_RX0NHDMI_0_RX0PHDMI_0_RX1NHDMI_0_RX1PHDMI_0_RX2NHDMI_0_RX2P

HDMI_0_SCL

TP251

1

RESET_TUNER

R1836

10k

3V3_STBY

10u10V

C1171

R1859

220R

HP_R

HP_L DSP_HP_L

DSP_HP_R

10u

C1180

10V

R1839

10k

RESET_S2

R761k 12

LM809U9

1

3

2RST

VCCGND

10R

R74

12

3V3_STBY

10R

R75

12

6V3

C1

1u

NC

HDMI2

HDMI1

AUDIO OUTPUTs

MODE SELECTION

AUDIO INPUTs

PRE-AMP for SCART AUDIO

COAX SPDIF OUT

MODE SELECTION

NC

NC

COMMON

OPTIONAL

MODE SELECTION

NC

60R

F281F297

60R

12V_VCC

R168410k1 2

VDD_AUDIO

F285

60RVDD_AUDIO_PWR

5V_VCC

3k9

R1711

12

R1712

15k

12

C1123

1u50V

12V_VCC

VDD_AUDIO

S871 2

R1718

100k

12

220nC1045

25V

5V_VCC

1N4148

D191

12

Q186BC848B

1

2

3

50V

C945

1n

C944

1n50V

F298

60R

F299

60R

C943

1n50V

C942

50V

1n

R_AUDIO_P_OUT

R_AUDIO_P

L_AUDIO_N

L_AUDIO_P

R_AUDIO_N

1u25V

C1073

R168710k 10k

R1696

S85

6V3

C10771u

1uC10756V3

HP_L

R1854

10k

12

MAIN_R

L_AUDIO_P_OUT

L_AUDIO_N_OUT

R_AUDIO_N_OUT

R_AUDIO_P_OUT

U168

TPA3110D2

15

16

17

18

19

20

21

22

23

24

25

26

27

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1 SD

FAULT

LINP

LINN

GAIN0

GAIN1

AVCC

AGND

GVDD

PLIMIT

RINN

RINP

NC

PBTL

PVCCL2

PVCCL1

BSPL

OUTPL

PGND1

OUTNL

BSNL

BSNR

OUTNR

PGND2

OUTPR

BSPR

PVCCR1

PVCCR2

R170210k 12

VDD_AUDIO

R171610k

R1714100kR1715100k

VDD_AUDIO

VDD_AUDIO

CN710

1

2

3

4

5

6

HP_MUTE

1u

6V3

C1076

10V

C615220u

TP51 1

TP521

C870

10V220u

TP230 1

TP229 1

17mb62S

Ulas Dereli

8AUDIO_AMP&HP_AMP

26-10-2011_15:43

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

T. SHT:

F294

60R

R1701

100k

R1704680R

C1226

25V

1u

C1227

25V

1u

1u25V

C1228

Q1922N7002

SK24

D192

1k

R1941

10u

C1032

16V

HP_R

D203

C5V6

Q2102N7002

1u25V

C1074

6V3

C10781u

AMP_EN

C1172

16V10n

F296

60R

R6234k7

VDD_AUDIO

R1855

10k

12

R817

100R

BC848BQ133

1

2

3

100R

R818

VDD_AUDIO

10V220n

C602

L_AUDIO_P_OUT

L_AUDIO_N_OUT

MAIN_L

4k7

R624

C665100n

10V1

2

10V

220n

C608

AMP_EN

VDD_AUDIO

3V3_VCC

10k

R1309

10k

R616

3V3_STBY

L_AUDIO_N

L_AUDIO_P

R_AUDIO_N

PT2333U164

C3

C2

C1

B3

B2

B1

A3

A2

A1

INP

GNDA

OUTN

VDDA

VDD1

GNDB

INN

SDB

OUTP

MAIN_R

AMP_EN

VDD_AUDIO

R614

4k7R_AUDIO_N_OUT

C1229

25V

1u

10V220n

C612

C666

100n10V

1

2

4k7R613

BC848BQ160

U163 PT2333

C3

C2

C1

B3

B2

B1

A3

A2

A1

INP

GNDA

OUTN

VDDA

VDD1

GNDB

INN

SDB

OUTP

R_AUDIO_P

16V10nC729

JK6

7

6

5

4

3

2

1

3V3_VCC4k7R1149

1HP_DETECT

220n

C617

10V

60R

F283

BC858B

Q1951

2

3

47k

R1699

100nC1058

16V

AMP_MUTE BC848BQ185

1

2

3

S861 2

VDD_AUDIO

C1121

10u

16V

R1717100k

10u

C1122

16V

680RR1960

VDD_AUDIO

C1043220n25V

25V220n

C1044

25VC1046

220n

F282

60RAMP_EN

R1741

100R1

2

3

4 5

6

7

8

R4

R1

R3

R2

MAIN_L

10u

L125

L126

10u

10u

L127

L124

10u

CONNECT TO DSP_M_L GND

ANALOG VCC

POP NOISE CIRCUIT

CONNECT TO DSP_M_R GND

AUDIO AMP for 26" to 32"

AUDIO AMP for 16" to 24"

SLIM HEADPHONE OUTPUT

NCNC

NC

NC

Ü.A. DEGISTIRILECEK

30001734 KULLANILDI

NC 30049510 KULLANILDI

3V6 lik zener kullanilmali

30022132 KULLANILDI30050557 KULLANILDI

30050557 KULLANILDI

30050557 KULLANILDI

30050557 KULLANILDI

NC

NC

X2

24MHz

PANEL_VCC

100RR19681 2

4k7

R1528

12

R1524

4k7

12

CN3

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

DVD_SPDIF

OP_PIN42

R5110k1 2

R1527

4k7

12

R1533

1M

R1967100R1 2

100RR1543

1 2

10k

R1562

R1567

10k

R1568

10k

R1571

220R

12

LED2

R1563

10k

BC848BQ170

1

2

3

SCL_SYS

SDA_SYS47RR1936

1 2

R193747R1 2

CN709

1 2 3 4 5 6

Q171BC848B 1

2

3

LED1

50V

C949

27p

1 2

F259

600R1 2

IR_IN

220R

R1569

12

Q174

BC858B 1

2

3

BC858BQ173

1

2

3

220R

R1570

12

220R

R1572

12

S763V3_STBY

600R

F2491 2

KEYBOARD

100RR1970

1 2

R1358

4k7

5V_STBY

100RR1969

1 2

100RR1954

3V3_STBY

HP_DETECT

SPI_SDI_1

50V

C951

33p

10V

C630100n

1

2

CN703

1 2 3 4 5

PCM_CD1_N

TP81

TP53 1

TP54 1

TP55 1

TP561

TP571

R14k7 12

4k7R1615

12

D204

B5V1

U5MSD9WB9PT-2

J21J20J19

B4C5V3

B6C7B5C6A6A7

K6M6

H19H20

A4

Y6AA6

E5

B3A3W8Y8J9H9

AA19AA20AA18W18W17Y18W16Y17AA16Y16AA15W15

W14Y15W13Y14AA13Y13AA12W12W11Y12W10Y11

Y9W7AA10Y10

B7E6F6GPIO7

GPIO11GPIO10

GPIO143GPIO141

SPDIFI/GPIO139GPIO137

LVA4MLVA4PLVA3MLVA3PLVACKMLVACKPLVA2MLVA2PLVA1MLVA1PLVA0MLVA0P

LVB4MLVB4PLVB3MLVB3PLVBCKMLVBCKPLVB2MLVB2PLVB1MLVB1PLVB0MLVB0P

GND1GND0USB1_DMUSB1_DPUSB0_DMUSB0_DP

HWRESET

XOUTXIN

IRIN

DDCR_DADDCR_CK

DDCA_DA/UART0_TXDDCA_CK/UART0_RX

GPIO14SDOSDISCKSCZGPIO12

SAR2SAR1SAR0

PWM2PWM1PWM0

4

F248

600R

1 2

KEYBOARD

47RR793

1 2

10n

C1215

16V

KEYBOARD_ONBOARD

STBY_ON/OFF_NOT

17mb62S

Ulas Dereli

8GPIOs&USB&LVDS_OUT

16-11-2011_10:11

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

T. SHT:

4k7

R1617

12

R1357

4k7

100RR1248

1 2

SPI_CSN_1SPI_SDO

SPI_SCK

3V3_STBY

FLASH_WPN

TP41

1

TP11

1

TP15

1

TP40

1

U158MX25L512

1234 5

678VCC

HOLD#SCLK

SIGNDWP#SOCS# T

P12

1

TP14

1

100n10V

C658

1

2

3V3_VCC

R1183

4k7

3V3_STBY1N5819

D165BACKLIGHT_DIM

MECH_SWITCH

DVD_SENSE

3V3_VCC

3V3_STBY

SC_PIN8

3V3_STBY

FLASH_WPN

SPI_SCKSPI_SDI_1

SPI_CSN_1

SPI_SDO

TX/SDA_SC

DVD_WAKEUP

RX/SCL_SC

SCL_SYSSDA_SYS

3V3_VCC

IR_IN

RESET

33p

C952

50V

USB_DMUSB_DP

TX_B_4_PTX_B_4_N

TX_B_0_NTX_B_0_P

TX_B_1_NTX_B_1_P

TX_B_2_N

R11984k7

TX_B_CLK_P

TX_B_2_P

TX_B_3_NTX_B_3_P

150R

R1940

U145

AZ099-04S2

4

5

6 IO4

VDD

IO3 IO2 3

GND

IO1 1R84410R1 2

R84510R

1 2

USB_DP

USB_DM

33kR62

TX_A_CLK_P

TX_A_2_N

TX_A_1_P

TX_A_1_N

TX_A_0_P

C610

10V10u

TX_A_0_N

TX_A_CLK_N

TX_A_2_P

PANEL_VCC

R183510k

12V_VCC

DIMMING

OP_PIN43

10kR52

1 2

PANEL_VCC 33kR63

OP_PIN45PANEL_VCC

R5310k1 2

R6433k

OP_PIN45

R6533k OP_PIN27

BACKLIGHT_ON/OFF

PANEL_VCC

R5410k1 2

33kR66

CI_POWER_CTRL

R1671

4k7

12

4k7

R1672

12

R19524k71 2

LED1LED2

3V3_STBY

3V3_STBY

OP_PIN11PANEL_VCC

10kR55

1 2

R6733k

MEGA_DCR_IN

OP_PIN8

S2MEGA_DCR_OUT

PANEL_VCC

33kR72

R5610k

1 2

OP_PIN9

OP_PIN10PANEL_VCC

10kR57

1 2

33kR68

33kR69

OP_PIN7PANEL_VCC

10kR58

1 2

R7033k OP_PIN6PANEL_VCC

R5910k1 2

33kR71

OP_PIN5PANEL_VCC

10kR60

1 2

PANEL_VCC

10kR61

1 2

S4

OP_PIN8

OP_PIN11

S15 12

PANEL_VCC

33kR2

R7333k

CN1

1

2

3

4

TP6

1

TP71

TX_B_0_N

TX_A_3_N

TX_A_CLK_P

TX_A_2_P

TX_A_2_N

TX_A_1_P

TX_A_1_N

TX_A_0_P

CN139

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

TX_A_0_N

TX_A_CLK_N

TX_A_3_P

TX_B_3_P

TX_B_3_N

TX_B_CLK_P

TX_B_CLK_N

TX_B_2_P

TX_B_1_P

TX_B_1_N

TX_B_0_P

PANEL_VCC

OP_PIN9

TX_B_2_N

OP_PIN27

PANEL_VCC

CN137

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CN138

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

S13

12

OP_PIN43

PANEL_VCC

TX_A_0_N

S3

12

S14

12

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_P

TX_A_CLK_P

TX_A_3_N

TX_A_CLK_N

OP_PIN42

OP_PIN9

TP9 1

TP16 1

TX_A_3_P

TX_A_2_N

TP17 1

TP18 1

TP19 1

TP20 1

TP21 1

TP22 1

TP23 1

TP24 1

TP25 1

TX_B_CLK_N

TX_A_0_NTX_A_0_P

TX_A_1_NTX_A_1_P

TX_A_2_NTX_A_2_P

TX_A_CLK_NTX_A_CLK_P

TX_A_4_N

TX_A_3_NTX_A_3_P

TX_A_4_P

TP26 1

TP27 1

TP28 1

TP29 1

TP30 1

TP31 1

TP32 1

10kR1833

R23

10k

470R

R7

R45

2k

SW5E1

G1

G2

G3

G4

E2

12TC34

S38

560RR77

5V_VCC

560RR46

3V3_VCC

KEYBOARD_ONBOARD

TP101

4k7R1959

1 2 3V3_STBY

5V_STBY

16V

100n

C1016

D189

1N4148

R16681k

22u

6V3

C1031

10k

R1667

3V3_STBY

100nC1015

10V1

2

R1666100R

12

RESET

HP_MUTE

TP33 1

TP34 1

TP35 1

TP58 1

TP59 1

TP61

1

TP60 1

TPS2553-1

U8

4

5

6

3

2

1 IN

GND

EN

OUT

ILIM

FAULT

PANEL_VCC

OP_PIN42

OP_PIN42

TX_B_CLK_P

TX_B_CLK_N

TX_B_2_P

TX_B_2_N

TX_B_1_N

TX_B_1_P

TX_B_0_P

TX_B_0_N

TX_A_4_N

TX_B_4_N

TX_B_4_P

TX_B_3_N

TX_B_3_P

TX_A_4_P

TX_A_0_N

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_N

TX_A_2_P

TX_A_CLK_N

TX_A_CLK_P

TX_A_3_N

OP_PIN6

OP_PIN5

TX_A_3_P

OP_PIN43

OP_PIN10

OP_PIN43

OP_PIN11

PANEL_VCC

OP_PIN9

OP_PIN8

OP_PIN7

OP_PIN27

CN2

515049484746454443424140393837363534333231302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1

CN4

515049484746454443424140393837363534333231302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1

EXT KEYPAD

LED SOCKETONBOARD KEYBOARD

SERIAL FLASH

RESET

USB

USB INTERFACE

19" TO 22" DOUBLE LVDS FFC OPTIONS

TOUCH_PAD_OPTION

PANEL_VCC = 5V/12V

PANEL VCC = 5V/12V

SINGLE LVDS FFC OPTIONS

15.6" LVDS OPTION

+ -

3 BUTTONS KEYBOARD OPTION

NC

SAM BASED 30070519

LG BASED 30070519

AVDD2V5_REF

AVDD2V5_AUD

AVDD2V5_MOD

F305

1k

F307

1k

1k

F308100n16V

C1221

12V_VCC12V_VCC/STBY

12V_STBY

12V_VCC

16V100nC1222

C691u50V

220uC65

10V

3V3_VCC

3V3_STBY

S8

S7

VDD_AUDIO_PWR

VDD_AUDIO_PWR

12V_STBY

12V_VCC/STBY

S10

S19

S21

S22

1u

C1128

25V

CN706

12

34

56

78

910

1112

1314

1516

1718

1920

10kR1685

12

3V3_VCC

4k7

R1678

12

R1679100R

100RR1973

3V3_VCC

DIMMING

BACKLIGHT_ON/OFF

5V_STBY

5V_VCC

STBY_ON/OFF

16V100nC1022

1k

F306

6V310uC1081

F272

60R

BC848BQ194

1

2

3

Q193BC858B

1

2

3

Q211

BC848B1

2

3

60R

F3021 23V3_VCC

4k7R1748

1 2

BC848BQ188

1

2

3

MSD9WB9PT-2

U5

H15

H16

H17

J14

J15

J16

J17

H14

K14

N7N8

P7P8

T8

R7R8

U8

V8

E8F8G8

G9

E9F9

J8

H8

G16

G17

G15

E15

E16

E17

F16

F17

K9

L9M9N9P9R9

D10

E10

F10

G10

H10

J10

K10

L10

M10

N10

P10

R10

D11

E11

F11

G11

H11

J11

K11

L11

M11

N11

P11

R11

D12

E12

F12

G12

H12

J12

K12

L12

M12

N12

P12

R12

D13

E13

F13

G13

H13

J13

K13

L13

M13

N13

P13

R13

D14

E14

L14

M14

N14

P14

R14

D15

K15

L15

M15

N15

P15

R15

D16

K16

L16

M16

D17

K17

L17

M17

K18

L18

M18

W2W3V4V5V6

D9

D18

GND87

GND86

GND85

GND84

GND83

GND82

GND81

GND80

GND79

GND78

GND77

GND76

GND75

GND74

GND73

GND72

GND71

GND70

GND69

GND68

GND67

GND66

GND65

GND64

GND63

GND62

GND61

GND60

GND59

GND58

GND57

GND56

GND55

GND54

GND53

GND52

GND51

GND50

GND49

GND48

GND47

GND46

GND45

GND44

GND43

GND42

GND41

GND40

GND39

GND38

GND37

GND36

GND35

GND34

GND33

GND32

GND31

GND30

GND29

GND28

GND27

GND26

GND25

GND24

GND23

GND22

GND21

GND20

GND19

GND18

GND17

GND16

GND15

GND14

GND13

GND12

GND11

GND10

GND9

GND8

GND7

GND6

GND5

GND4

GND3

BYPASS

AVDD_DDR_4

AVDD_DDR_3

AVDD_DDR_2

AVDD_DDR_1

AVDD_DDR_0

AVDD_LPLL

VDDP1

VDDP0

AVDD_EAR33

AVDD_AU33

AVDD_CVBS33_1

AVDD_CVBS33_0

AVDD_DMPLL

AVDD_ALIVE_2

AVDD_ALIVE_1

AVDD_ALIVE_0

PGA_VCOM

AVDD_PGA25

AVDD_MOD25_1

AVDD_MOD25_0

AVDD_AU25

AVDD_REF25_1

AVDD_REF25_0

AVDD_ADC25_1

AVDD_ADC25_0

AVDD_126

DVDD_DDR

VDDC6

VDDC5

VDDC4

VDDC3

VDDC2

VDDC1

VDDC0

6

12V_VCC

L2

10u

R18

10k

4k7

R41

2k2

R42

17mb62S

Ulas Dereli

8POWER_1&LNBP

26-10-2011_15:44

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

T. SHT:

VDDC_1V2

C68

50V

15n

15k

R43

C12220n25V

D7

1N4001

LNB_OUT

C70470n25V

3V3_VCC

R19

10k

F295

1k

SK24

D8

C13220n25V

16V

C997100n

SDA_SYSSCL_SYS

3V3_VCC

100n16V

C1005

C14

25V220n

C1070

16V100n

C100416V100n

LNBH23LU6

274191869142930

2213211112

123781617232425263132

101528 5 20

A_GND

P_GND

I_SEL

BYP

ADDR

NC_13NC_12NC_11NC_10NC_9NC_8NC_7NC_6NC_5NC_4NC_3NC_2NC_1

DSQINPDC

VO_RXEXTMVO_TX

RSV_2RSV_1TTXSCLSDAVCC_LVCCLXV_UP

12V_VCC

S821 2

R163610k1 2

10kR1635

12

3V3_TUNER

12V_VCC

3V3_VCC

VDD_3V3

1N5819

D6

5V_VCC

DISEQC_OUT

R175022k

VDD_AUDIO_PWR

10kR1631

1 2

16V100nC1009

10u10V

C774

C974

1u6V3

AVDD_DDR

AVDD_3V3

AVSS_PGA

AVDD_2V5_PGA

AVDD2V5_ADC

BAW56

D184

12

3

10k

R1639

12

BC848BQ191

1

2

3

STBY_ON/OFF

3V3_STBY

STBY_ON/OFF_NOT

10kR1638

1 2

Q178

BC848B1

2

3

Q180BC858B

1

2

3

3V3_STBY

R164933k 12

D185

BAW56

12

3

D186

BAW56

12

3

100nC971

10V1

2

PROTECT

TP202

1

U7LM809

1

3

2RST

VCCGND

3V3_STBY

R1761100R

1

2

3

45

6

7

8

R4

R1

R3

R2

R11664k71 2

50V

C840

220p

1 23V3_VCC

4k7R1158

1 2

BACKLIGHT_DIMDIMMING

C839

50V220p

1 2

50V220p

C838

1 2

4k7R1165

1 2

R1221

1k

12

S18MEGA_DCR_IN

S16

MEGA_DCR_OUT

12V_STBY

S17

Q189BC848B

1

2

3

F277

60R

R2010k 1 2

R4020k

10kR21

R172733k 12

100nC1025

16V

C1024100n16V

3V3_STBY

VDDC_1V2

16VC1001

100n

C102910u6V3

AVDD_2V5_PGA

10uC1030

6V3

C1028

6V310u

AVDD_DDR

F270

60R

AVSS_PGA

100n16V

C1008

2V5_VCC

F271

60R

3V3_VCC

60R

F274

100nC1007

16V

1V8_VCC

1V2_VCC

C1014

16V100n

2V5_VCC

VDD_3V3

AVDD_3V3

PANEL_VCC_ON/OFF

PANEL_VCC

F290

60R

1 2

47RR1725

1 2

33k

R1734

12

22k

R1749

FDC642P

Q199

134 5 6

2

TP213

1F288

60R1 2

F289

60R1 2

10kR1693

12

C1042100n

10V1

2

5V_VCC

12V_VCC

Q190BC848B

1

2

3

5V_VCC

C7

16V

22u

12V_VCC/STBY

12V_VCC/STBY

5V_STBY

LM1117U1

1

23

4

VOUT

IN OUT

ADJ

3V3_STBY

12V_VCC/STBY

22u6V3

C990

R16774k71 2

R1676

4k7

12

C6

16V

22u

16V100nC1223

100n16V

C1224

C1225100n16V

AVDD2V5_ADC

AVDD2V5_REF

AVDD2V5_AUD

AVDD2V5_MOD

DIMMING CIRCUIT

AP211HSHORT CCT PROTECTION

LNB CIRCUIT

PANEL SUPPLY SWITCH

60R 402 ferrite secilecek

POWER SOCKET PW04 LOW POWER Option

NC

NC

ADAPTOR OVER VOLTAGE PROTECTION

NC

CN705

1

2

3

4

5

6S6

60R

F61 2

F7

60R

1 2

5V_VCC

60R

F91 2

12V_VCC

60R

F101 2

12V_VCC

60R

F111 2

F12

60R1 2

3V3_VCC

R24

100R

12

3V3_TUNER

LM1117U2

1

23

4

VOUT

IN OUT

ADJ

12V_STBYR197210k 12

100kR1769

F303

60R

1 2

5V_VCC

15u

L1231 2

S89

L116

10u

12V_STBY

12V_INV

BACKLIGHT_ON/OFF

JK9

1

2

3

4

5 7A/32VDC

FS31 2

DIMMING

12V_INV

FS4

7A/32VDC

1 2

Q197

FDC604P

134 5 6

2

TP361

TP371

TP391

TP45

1

TP239

1

6V322uC1086

TP46

1

TP243

1

TP231

1

S83

TP241

1

7A/32VDC

FS21 2

5V_VCC

TP244

1

TP238

1

Q2

FDC642P

134 5 6

2

FDC604P

Q1

134 5 6

2

C121222u6V3

C108722u6V3

C1217

10n

50V

100R

R1979

1 2 3 45678

R4

R1

R3

R2

22k

R1736

C109422u6V3

22u

C1079

6V3

R1770150k

16V

C108522u

22uC1101

6V3

STBY_ON/OFF

STBY_ON/OFF_NOT MOSFET_CONTROL

L117

10u

16V

C108922u

16V22uC1090

22uC1092

16V

22u6V3

C1097

6V322uC1033

C1102

16V22u

100RR25

1 2

C1093

6V322u

6V322uC1096

R17085k6

330R

F3001 2

10V

C1034100n

1

2

20kR1738

6V3

C1107

1u

Q198

FDC604P

134 5 6

2

C1037

16V100n

17mb62S

Ulas Dereli

8POWER_2

26-10-2011_15:44

87654321

A

B

C

D

E

F

AX M

1 2 3 4 5 6 7 8

A

B

C

D

E

F

A3PROJECT NAME :

SCH NAME :

DRAWN BY :

T. SHT:

F291

60R

1 2

10V

C1036

100n

12

22u16V

C1091

10kR1697

12

22u6V3

C1098

12V_VCC12V_VCCR169110k 12

U173

MP1484

1

2

3

4 5

6

7

8SS

EN

COMP

FBGND

SW

IN

BS

39kR1686

1V2_VCC

10nC1113

16V1

2

5n6

C1131

50V

1 2

60R

F2731 2

R17103k91 2

R1720100R

1 2

33k

R1731

12

C1048

220n

25V

12

47RR1723

1 2

12V_STBY

Q183BC848B

1

2

3

3V3_STBY

22k

R1735

R1730

10k

5V_STBY

MOSFET_CONTROL

3V3_VCC

L118

15u1 2

1kR1768

C1084

16V22u

R1737

33k

C1035

100n

10V

12

C1080

6V3

100u

12

R17093k91 2

5n650V

C1130

1 2

16V10n

C1112

1

2

D197

SS33

12

MP1583U174

5678

4321 BS

INSWGND

SSEN

COMPFB 10k

R16901 2

2V5_VCC

U175LM1117

1

23

4

VOUT

IN OUT

GND

R169210k 12

100R

R1721

12

12V_VCC

MOSFET_CONTROL

FDC642P

Q200

134 5 6

2

33k

R1733

12

12V_STBY

Q182BC848B

1

2

3

47RR1724

1 2

220n

25V

C1049

12

33k

R1732

12

60R

F2871 2

100n

16V

C1038

1

2

34

5

6

MP2012

U176EN

VIN

PVIN SW

GND

FB

7A/32VDC

FS51 2

3V3_STBY

22u16V

C1103

1V8_VCC3V3_VCC

MOSFET_CONTROLR169810k 12

5V_VCC

1k

R1728

5V_STBY

Q184BC848B

1

2

3

R172247R1 2

C1047

220n25V

12

33k

R1729

12

6k8R3

L16

10u

60R

F2861 2

C1129

50V5n6

1 2

10nC1114

16V1

2

10kR1689

12

3V3_STBY

12V_STBY 12V_STBYU23

MP1484

1

2

3

4 5

6

7

8SS

EN

COMP

FBGND

SW

IN

BS

S1

DCDC

DCDC

ADAPTER SOCKETW_ADAPTER

!

NC

INVERTER SOCKET W/ADAPTER

DCDC

DCDC

LDO

12V_STBY 12V_VCC

1V2_VCC

5V_STBY

5V_VCC

3V3_STBY

3V3_VCC

0R

DC/DC2

DC/DC4LDO1

2V5_VCC

1V8_VCC

SW1

AP211H

LDO

DC-DC4

SW2

SW3

DC-DC2

COMMON

W/ADAPTOR & W/IPS16&17&60&PW25&PW06

DC-DC1

W/ADAPTOR

DC-DC3

POWER BLOCK DIAGRAM

LDO1

LDO23V3_TUN

SW1

DC/DC1

DC/DC3

SW2

SW3

NC

2A

30068939

4A

NC

3N3

150K10UH

30068939

for 3v3 Panel Sup.

LDO2

CCFL INVERTER SOCKET

27.2 PSU