------------------------------------------------------------------------------------ Company: -- Engineer: -- -- Create Date: 01:36:48 05/15/2013 -- Design Name: -- Module Name: slicealu - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: ---- Dependencies: ---- Revision: -- Revision 0.01 - File Created-- Additional Comments: ------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity slicealu isport(a,b:in std_logic_vector(1 downto 0);sel:in std_logic_vector(2 downto 0);result:out std_logic_vector(1 downto 0)); end slicealu;architecture Behavioral of slicealu issignal t1,t2,t3,t4:std_logic; signal temp:std_logic:='0';signal t5,t6:std_logic_vector(2 downto 0); signal t7,t8:std_logic_vector(1 downto 0);component alu isport(a,b,c:in std_logic;sel:in std_logic_vector(2 downto 0); out1:out std_logic_vector(1 downto 0)); end component; begintemp