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©Silicon Library Inc, All rights reserved. SD UHSII PHY Analog Datasheet (GLOBALFOUNDRIES28SLP) SLDE-DS-0070 Rev. 1.0.1 Aug 5, 2015

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Page 1: SLDE-DS-0070 SDUHS2PHY Simplified datasheet G28SLP …€¦ ·  · 2017-11-07Microsoft Word - SLDE-DS-0070_SDUHS2PHY_Simplified_datasheet_G28SLP_Rev1.0.1.docx

©Silicon Library Inc, All rights reserved.

SD UHSII PHY Analog

Datasheet

(GLOBALFOUNDRIES28SLP)

SLDE-DS-0070 Rev. 1.0.1 Aug 5, 2015

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SLDE-DS-0070 Rev. 1.0.1

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©Silicon Library Inc, All rights reserved.

TABLE OF CONTENTS

1 INTRODUCTION ................................................................................................................................................................. 2

2 FEATURES ............................................................................................................................................................................ 3

3 BLOCK DIAGRAM .............................................................................................................................................................. 5

4 ELECTRICAL CHARACTERISTICS ............................................................................................................................... 6

4.1 OPERATING CONDITIONS ................................................................................................................................................... 6

4.2 ELECTRICAL SPECIFICATION .............................................................................................................................................. 6

4.3 TIMING SPECIFICATION ...................................................................................................................................................... 8

4.3.1 Transmitting section .................................................................................................................................................. 8

4.3.2 Receiving section ....................................................................................................................................................... 8

5 REVISION HISTORY .......................................................................................................................................................... 9

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©Silicon Library Inc, All rights reserved.

1 INTRODUCTION

SLIPSDHU2AG28SLP is a physical layer for SD UHS-II. This IP consists of two parts, one is a

synthesizable digital part (SLIPSDHU2AG28SLP_D) and the other is an analog part

(SLIPSDHU2AG28SLP_A). SLIPSDHU2AG28SLP supports 390Mbps to 1.56Gbps data rate, and both Full

Duplex/Half Duplex modes.

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©Silicon Library Inc, All rights reserved.

2 Features

SD UHS-II compliant Physical layer for device

Optimized for UHS-II Host

Supports both Full Duplex mode and Half Duplex mode

Power Dormant Mode

1.8V/1.0V power supply

Configurable analog characteristics

Driver swing voltage

Driver rise time / fall time

BGR voltage

PLL loop filter

PLL VCO gain and offset-frequency

PLL lock detector accuracy

Regulator voltage

DET threshold voltage

Built in self test

Various loopback modes

Supports metal option 6U1x_2T8x_LB and up (Two 8x metals required)

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Used devices

Core voltage RVT-NMOS/PMOS, LVT-NMOS/PMOS, Diode

1.8V NMOS/PMOS, Diode, NMOS cap, BJT

Un-silicided poly resister

No DNW required

PHY area : 1.05mm x 1.0mm = 1.05m2 (including IO)

Compliant SD4 ESD requirements, 4kV(HBM) 200V(MM)

Deliverables

Datasheet

Integration guideline

GDSII or Phantom GDSII

Layer map table

CDL netlist for LVS

LEF

Verilog behavior model

Liberty timing model

DRC/LVS/ERC results

GLOBALFOUNDREIS 28nm SLP process

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3 Block Diagram

Figure 1 SLIPSDHU2AG28SLP_A Block Diagram

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4 Electrical Characteristics

4.1 Operating Conditions

Item Symbol Min Typ Max Unit Notes

1.8V Supply Voltage Vddh 1.8

-10%

1.8 1.8

+10%

V Delivered from AVDD18 pads

1.0V Supply Voltage Vddl 0.90 1.0 1.2 V Delivered from SOC core

through internal VDD ports

Junction Temperature Tj -40 27 125 degC

4.2 Electrical Specification

Item Spec

Unit Notes Min Max

Tx Output Impedance 35 65 ohm

Rx Input Impedance 74 126 ohm

Input Capacitance (RCLK) 10 pF

Input Capacitance (D0, D1) 2 pF

EIDL Differential Voltage -10 10 mV

EIDL Common Mode Voltage -10 10 mV

Tx Differential Voltage 125 330 mV

Tx Rise/Fall Time

(Range A) 200 ps

Tx Rise/Fall Time

(Range B) 100 ps

Tx Common Mode Voltage 150 250 mV

Tx Inter Skew 0.35 UI

Tx Data Jitter 0.35 UI

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Tx Data Eye Diagram

Data signal must

satisfy UHS-II

eye mask.

Rx Differential Voltage 135 mV

Rx Common Mode Voltage 50 400 mV

Rx Common Mode Voltage for EIDL -110 160 mV

Rx Total Jitter 0.4 UI

RCLK Differential Voltage 125 330 mV

Rise/Fall Time of Differential Signal 0.2 Trclk

RCLK Common Mode Voltage 150 280 mV

RCLK Total Jitter 0.3 UI

RCLK Duty Cycle 42.5 57.5 %

Return Loss

D0, D1 must

satisfy UHS-II

Return Loss Mask

Reference clock (PHY_PLL_REFCLK) total

jitter

230

ps

pk-p

k

When ref clock frequency is

52MHz and the PHY operates in

Range B.

SSC is excluded.

Defined at input pin of IP

3.5

%

pk-p

k

Other ref clock frequency in

Range B

SSC is excluded.

Defined at input pin of IP

7

%

pk-p

k

PHY operates in Range A

SSC is excluded.

Defined at input pin of IP

Reference clock (PHY_PLL_REFCLK) duty

cycle 30 70 %

Defined at input pin of IP

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4.3 Timing Specification

4.3.1 Transmitting section

Figure 2 Parallel data timing diagram of transmitting section

Item Symbol Min Max Unit

Data setup time Tsu-tx 0.7 ns

Data hold time Thld-tx 0.2 ns

4.3.2 Receiving section

Dn[0]

Dn[1]

Dn[2]

Dn[3]

Dn[4]

Dn[5]

Dn[6]

Dn[7]

Dn[8]

Dn[9]

Dn+1[0]

Dn+1[1]

Dn+1[3]

Dn+1[6]

Dn+1[8]

Dn+1[2]

Dn+1[4]

Dn+1[5]

Dn+1[7]

Dn+1[9]

Figure 3 Parallel data timing diagram of receiving section

Item Symbol Min Max Unit

Output delay time Td-rx -0.3 0.7 ns

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5 REVISION HISTORY

Date Rev. Changes Made Section Effected

September 2, 2013 0.1.0 Initial Release -

October 3, 2013 0.1.1 Corrected typo 2

March 26, 2014 1.0.0 Corrected 1.8V supply voltage range 5.1

Aug 5, 2015 1.0.1 Phy parameter 7

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©Silicon Library Inc, All rights reserved.

SD UHSII PHY IP Datasheet

(GLOBALFOUNDRIES28SLP)

©Silicon Library Inc, All rights reserved.

Duplication of this document is strictly prohibited without express written approval of Silicon Library

Inc

The contents of this document are subject to change without prior notice.

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©Silicon Library Inc, All rights reserved.

Silicon Library Inc.

203 MCII

2-3227 Mita, Tama-ku,

Kawasaki, Kanagawa, 214-0034 Japan

Phone: +81-50-5527-7974

Silicon Library’s website can be found at:

http://www.siliconlib.com