Proceedings of 2014 RAECS UIET Panjab University Chandigarh, 06 08 March, 2014

978-1-4799-2291-8/14/$31.00 2014 IEEE

Designs of All Digital Phase Locked Loop A REVIEW

Aastha Singhal Charu Madhu Vijay Kumar Department of Electronics and Communication

University Institute of Engineering and Technology, Panjab University Chandigarh, India.

Abstract Phase Locked Loop (PLL) is a feedback system that is configured as frequency multipliers, tracking generators, demodulators and clock recovery circuits. Today the most challenging requirement engineers face is design of fast locking PLL with low jitter. Many analog techniques are proposed to fulfill the demand but they result in increasing complexity of design and long lock in time. In this paper, review of advantages of an All-Digital phase locked loop (ADPLL) over an analog phase locked loop (APLL) in terms of stability, programmability is studied. Various approaches to design the blocks of ADPLL till now adopted are presented in this paper. Keywords- Phase Locked Loop (PLL); all digital phase locked loop (ADPLL); analog phase locked loop (APLL)

I. INTRODUCTION Phase Locked Loop (PLL) is a closed loop feedback system

that is capable to track the fixed phase relationship between phase of output and the reference clock. It is widely used for clock recovery, as a frequency synthesizer, jitter attenuator and synchronization of chips in GPS receivers [1]. The foundation of PLL was led in 1918 with the invention of super heterodyne but it uses large number of tuned stages. In early 1930s attempt of comparing frequency of oscillator with input of detector is carried out which results into introduction of PLL in 1932 by de Belle size, French Engineer [2].Since then the basic PLL block diagram has nearly remained same but time to time lot of researches and advancements has been done on various parameters of PLL such as the lock time, the phase noise, jitter, loop bandwidth, output frequency and acquisition time. When certain parameters are improved, others factors may get worse.PLL can be configured in following three ways- Analog PLL (all blocks are analog), Hybrid PLL (combination of both analog and digital circuit) and All Digital PLL (all blocks are implemented digitally).The paper is organized as follows: Section II presents Prior work using APLL. Section III gives Overview of ADPLL architecture. Section IV presents mathematical modelling of ADPLL and finally conclusion is drawn in section V.

II. PRIOR WORK USING APLL There are three building blocks of PLL - Phase Detector,

Loop filter and VCO (Voltage Controlled Oscillator) [1]. Phase detector compares the phase of each input, proportional

to the phase difference between them generates an error signal which alters the input of VCO to make its output frequency equal to input frequency. PLL has three operating states-frequency running, capture and lock state. In free running feedback loop is open and VCO is oscillating in its natural frequency. In capture mode, feedback loop is closed and VCO vary the feedback frequency to make it equal to reference frequency. In lock state, the phase error is zero i.e. both the frequency are perfectly matched.

Traditionally, analog approaches were adopted to design PLL. In 2007, Greg Paul [3] had used ferroelectric capacitor in

VCO replacing linear capacitor as a storage element which leads to reduction in cycle to cycle jitter because of its non-linear dielectric constant behavior.

Interpolate compensation [4] method was used in which compensator and interpolative loop were implemented which detects the jitter during the sampling of reference input signal.

Jitter reduction circuit was proposed [5] which was based on autocorrelation of jittered signal.

In 2010, Jie Wu [6] introduces the usage of digital circuitry to reduce noise from VCO which was difficult to avoid using analog technique. This was the first time when DDSC (Digital distributed synchronous clock) with voltage controlled crystal oscillators (VCXO) was implemented. This design shows jitter cleaning properties but problem in this design was it was unable to compare the reference clock with feedback clock completely due to inaccuracy of DAC.

In analog PLL, many algorithms were designed and modelled [7], [8] to generate mathematical relations to check maximum noise level from various components of PLL and deducing the transfer function for system.

In [9], [10] sub sampling PLL was used to lessen the impact of jitter to a factor of 0.73 ps. In this no frequency divider was used during the locked state. During locking period PD/CP is not multiplied by N2 factor which leads to low noise.

Above analog techniques were proposed to reduce jitter in PLL but they result into higher switching and lock-in time, complexity of circuit was also increased and PLL becomes sensitive to process parameters so they need to restore for new technology every time.

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Because of the need of the circuit with small size, high performance, low cost and immunity to noise there is a need to digitalize various blocks of PLL which is implemented using ADPLL.

Fig.1 Basic block diagram of ADPLL

III. OVERVIEW OF ADPLL ARCHITECTURE An All Digital Phase Locked Loop (ADPLL) composed of

components purely in digital format. All the components of ADPLL are analogous to analog PLL. The phase detector is replaced by digital phase frequency detector or time to digital convertor. The phase error is in digital representation. Digital filter is used instead of analog filter where frequency is controlled by a control word. The voltage controlled oscillator (VCO) is replaced by digitally controlled oscillator (DCO).General block diagram of ADPLL is shown in Fig.1 [13].Various techniques used to design these blocks are describe as below.

A. PHASE-FREQUENCY DETECTOR (PFD) A PFD detects phase/frequency error between reference

(V1) and feedback clock signal (V2) and generates a signed binary code (Vd). In late nineties, EX-OR gate as shown in Fig-2(a) was used for phase detection but it was level triggered mechanism which results into lack of sensitivity to edges. To eliminate this drawback the edge triggered JK mechanism was employed as given in Fig-2(b). It was sensitive to the edges and hence instantaneous corrective action can be achieved. These were the basic means to design the detector. In 2003, Digital pulse amplifier (DPA) [14], [16] had been proposed to enlarge phase error when it is so small that it is difficult to detect. DPA minimizes the dead zone and make it more easily detectable by D-Flip Flop, these amplifiers has AND gates connected in cascaded network to increase width of pulse.

Fig.2 (a) XOR implementation (b) PD based on edge triggered JK

The design of DPA proposed was as shown in Fig-3 [16]. In 2006, chang-hong shan [15] introduce another method of designing ADPLL which is based on Double edge triggered flip flop. Takamoto Watanabe in [17] high speed with phase lock at seventh reference cycle was intended in which a ring delay line (RDL) with 32 inverters were assembled and taken as a time base for designing the PFD. Martin kumm in 2010 designed [18] the Hilbert transform based PFD in which input signal are firstly converted into analytic signals using Hilbert transform and then phase error was obtained using Cartesian to polar conversion. To build phase error, zero delay circuits were employed. In [12], [19] PFD along with a time to digital convertor (TDC) was used which together forms P2D (Phase to Digital) convertor as shown below in Fig-4 [12]. The PFD sense the difference of reference frequency and DCO divided clock and then converts the phase error into off-time width (t) and further TDC digitalize t into set of binary digits with fixed resolution of TDC. Dynamic logic PFD was adopted in [12] instead of static PFD as number of transistors are decreased from 44 to 16 hence power and dead zone were reduced. In reference [20] Nyquist- rate phase detector was proposed and designed using HDL.

Fig.3 Proposed design of PFD with DPA

Fig.4 Phase to digital convertor

B. DIGITAL LOOP FILTER (DLF) The code generated by phase frequency detector is

processed by loop filter so as to generate a control word for digitally controlled oscillator. DLF may be designed using PI, PD or PID controller i.e. loop filter consist of integral, proportional, differential or delay elements [21]. Type of loop filter is important property of PLL as type-1 is suitable for lock time but it has low noise immunity [11]. In order to remove glitches from PFD to reduce power consumption and generating digital codes proportional to the output of PFD a controller is designed in [16], two types of deglitching filter

(a)

(b)

circuit were proposed as shown in Fig-5(a) and 5(b).Second method was suitable for every digital circuit but consumes more power as compared to first method.

Fig.5 (a) First deglitching filter circuit (b) Second deglitching filter circuit

Double edge triggered based DLF had been proposed [15] to achieve low power. In this adder was designed by the combination of DETDFF and a full adder as shown in Fig-6 [15]. After get modulated through PI controller it is passed to adder which provides the control word of DCO. One of the most important and simplest digital loop filters is the K counter [13] shown in Fig 7[13]. This filter always works in combination with EXOR or the JK-flip-flop phase detector. In [19], [12],[22],[23] designed PI integral based loop filter as shown in Fig 8 [12] which consist of proportional and integral path from second order charge pump PLL using bilinear transformation is proposed. Using this design phase margin is calculated for stability analysis.

Fig.6 Design of DLF based on DETDFF

Fig.7 K counter loop filter

Fig.8 Logical configuration of Digital LPF

C. DIGITAL CONTROLLED OSCILLATOR (DCO)

DCO is similar to analog VCO except for DCO frequency is tuned digitally whereas VCO is tuned by analog signal from charge pump. It is the heart of Phase locked loop which changes its output frequency in accordance to the control word from loop filter. Yu Ming Chung [12] and V. Kratyuk [19] used ring oscillator for frequency tuning instead of LC oscillator as later was more bulky and performs tuning through switching on and off the tank capacitor which further leads to power consumption. Fig-9 shows the proposed design of DCO which consist of 5 delay cells, frequency was tuned according to the current passes through these delay cell. One of the typical methods to design DCO was using combination of VCO and DAC (Digital to Analog convertor) [23]. From the output of digital loop filter digital code was obtained which was converted into control voltage (Vc) by DAC fed into the VCO for controlling the frequency. In [13] basic configuration of DCO is given by K.Lata which is increment-decrement counter which works on the principle that if fref is more than fdiv the counter will increment the frequency of fdiv and vice versa. Logical block of the counter is shown in Fig 10.Bohan Wu, 2013[22] proposed two methods output frequency detection and frequency averaging method to achieve fast Locking and remove non-idealities such as DCO estimation error.

Fig.9 DCO with delay cell decrement

Fig.10 Logical block of increment-counter

(a)

(b)

In 2012, S.Sreekumar uses NCO(Numerically Controlled Oscillator) [20] in his design which will take error voltage (Vn), and then shift its output frequency from its free-running value closer to reference frequency so to make phase error zero and thus keep the PLL in lock state. In reference [16] ring oscillator based DCO is proposed consisting of 64 buffers with different combinations of digital code having different path corresponds to different clock period and clock frequency. This was executed using binary frequency search algorithm.

IV. MATHEMATICAL MODELLING OF ADPLL Various properties of ADPLL such as working range,

stability, lock-in range [ 18],[26] , loop bandwidth and variables based on noise sources [24] can be analyzed in either phase domain or z-domain [11], [21].

A. PHASE DOMAIN MODEL OF LINEAR PLL

Block diagram of PLL as shown in Fig-11(a) [18], presents three main components of PLL in phase domain and transfer functions of all the blocks is given in Fig-11(b).

Phase Detector (PD): It detects the phase difference (v (t)) between the input signal Vi (t) and the feedback signal Vo (t).

Loop filter: It has transfer function of F(s) which depends on type and order of filter used. It is used to minimize the phase difference (t) by varying the frequency of VCO. Here [18] type 1 PI controller loop filter is used with gains of proportional and integral path KI and KP respectively.

VCO: Voltage Controlled Oscillator is having transfer function of Ko/s whose output frequency oscillator is a function of the voltage of its input signal.VCO acts like an integrator.

Fig.11 (a) General block diagram of PLL

Fig.11 (b) Phase domain model of PLL

Transfer function of loop filter:

F(s) = KP + K

Gain of phase detector and VCO is considered as Kd and KO respectively. The phase error can be given as:

E(s) ==

K K F

Resulting value of phase error can be given as

E(s) ==

K K K K K K

When compared with general second order equation

E(s) =

Comparing both the above equations

Wn (natural frequency) =Ko Ki Kd (damping ratio) = K KK

K/

Natural frequency varies the settling time so it is

responsible for fast locking. It is generally kept high but should be low enough so to achieve phase filtering efficiently.Damping factor affects overshoot so to maintain trade off between both = 0.707 (approx) [19].

B. Z-DOMAIN MODEL OF PLL Phase or continuous time domain modeling of PLL is

applied to analog design of PLL, but for digital systems z-domain modeling is more accurate and proper description. So far a lot of work has been done in analysis of ADPLL using Z-domain. Block diagram of z-domain model is as shown in Fig-12 [21]. In this phase detector is represented by summing node, gain block (Kd) and a delay block of z-1 as frequency of DCO output is dependent on events a step earlier [21]. Loop filter is implemented using first order PI elements where Ki and Kp are gains of integral path and proportional path. All the blocks of ADPLL can be analyzed by performing bilinear transformation of s-domain analysis by replacing s by (1-z-1). Z-domain transfer function of loop filter:

F (z) = KP +

K =

KKK

Transfer function of DCO is

D (z) = K

Open loop equation can be given as:

L (z) =Kd*Kf*Ko*z-1*F (z)*D (z)

Closed loop transfer function is given by:

H (z) = LL

Fig.12 Z-domain model of PLL

V. CONCLUSION In this paper, a detailed analysis of various techniques for

designing the phase detector, digital loop filter and digital controlled oscillator in ADPLL is provided. Among all the methods to design detector, PFD with TDC is the best approach as the amount of glitches using this method is less. Digital loop filter is designed using bilinear transformation of RC loop filter.DCO structure based on ring oscillator is preferred for low power and low complex design. Finally, if we use PFD, TDC and digital loop filter together in ADPLL, various parameters such as lock-in time, power consumption and stability can be evaluated and comparison with the results of existing ADPLL structures can be carried out.

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[7] Siwiec, K., Borejko, T. and Pleskacz, W.A.: CAD tool for PLL design, IEEE 14th International Symposium on design and diagnostics of electronic circuits and systems (DDECS), April 2011, pp.283-286. [8] Telba, A.A.: Modelling and simulation of wideband low jitter frequency synthesizer, IEEE International Conference on Multimedia, signal processing and communication technologies, March 2009, pp.317-319. [9] Sogo,K.,Toya,A. and Kikkawa,T.: A ring VCO-based Sub-sampling PLL CMOS circuit with 0.73 ps jitter and 20.4 mW power consumption, Asia and South pacific conference on design automation conference (ASP-DAC), Jan 2013, pp. 101-102. [10] Xiang Gao, Klumperink,E. A.M., Bohsali,M. and Nauta,B.: A Low Noise Sub-Sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2, IEEE Journal of solid state circuits, vol.44, No.12, December 2009, pp. 3253-3263. [11] Mendel, S., Vogel, C.: A z-domain model and analysis of phase-domain All- Digital Phase Locked Loops, IEEE, 2007. [12] Yu-Ming Chung and Chia-Ling Wei, An All-Digital Phase-Locked loop for Digital power management integrated chips, IEEE International Symposium on circuits and systems, May 2009, pp. 2413-2416. [13] Lata, K. and Kumar, M.: ADPLL Design and Implementation on FPGA, 2013 International Conference on Intelligent Systems and Signal Processing (ISSP), March 2013, pp.272-277. [14] Ching-Che Chung and Chen-Yi Lee: An All-Digital Phase-Locked loop for High- Speed Clock generation, IEEE Journal of solid-state circuits, vol. 38, No.2, February 2003, pp.347-351. [15] Chang-hong Shan, Zhong-ze Chen, Yan Wang: An All-Digital Phase-Locked loop based on Double Edge Triggered Flip-flop, IEEE, 2006. [16] Watanabe, T. and Yamauchi, S.: An All-Digital PLL for Frequency multiplication by 4 to 1022 with seven cycle lock time, IEEE Journal of solid-state circuits, vol. 38, No.2, February 2003, pp.198-204. [17] Abadian, A., Lotfizad, M., Majd, N.E., Ghoushchi, M.B.G and Mirzaie, H.: A new low- power and low-complexity All Digital PLL (ADPLL) in 180 nm and 32 nm, IEEE International Conference on electronics, circuits and systems, December 2010, pp.305-310. [18] Kumm, M., Klingbeil, H. and Zipf, P.: An FPGA-based linear All-Digital Phase-Locked loop, IEEE Transactions on circuits and systems-I, Regular papers, vol.57, No.9, September2010, PP.2487-2497. [19] Kratyk,V., Hanumolu,P.K, Moon,U. and Mayaram,K.: A Design Procedure for All-Digital Phase-Locked loops based on a charge pump phase locked loop analogy, IEEE Transactions on circuits and systems-II, Express Briefs,vol.54, No.3 March 2007. [20] Sreekumar, S., Geetha and Snoop, M.K.: FPGA Implementation of ADPLL, International journal of emerging technology and advanced engineering, vol.2, issue 6, June, 2012. [21] Xin Chen, Jun Yang and Xiao-ying Deng: A Contribution to the discrete z-domain analysis of ADPLL, IEEE International Conference on ASIC, October 2007, pp.185-188. [22] Bohan Wu, Weixin Gai and Te Han: A Novel Frequency Search Algorithm to achieve fast locking without phase tracking in ADPLL, IEEE International Symposium on Circuits and systems (ISCAS), May 2013, pp.2464-2467. [23] Xin Chen, Ju Yang and Long- Xing shi: A fast-locking All-digital Phase-Locked Loop via Feed- forward compensation technique, IEEE Transactions on very large scale integration(VLSI) systems, vol.19, No.5, May 2011,pp.857-868. [24] Bo Jiang and Tian Xia: ADPLL Variables Determinations based on phase-noise, spur and locking time, IEEE International SOC Conference, September 2012, pp.39-44. [25] Jiancheng Li, Tao Xu, Zhaowen Zhuang and Yongfeng Guan, High performance All Digital Phase Locked Loop Mathematics Modelling and Design, IEEE International Conference on Information and Automation, June 2008, pp.1395-1399.

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