simplifying mso-based debug of designs with xilinx fpgas
DESCRIPTION
Simplifying MSO-based debug of designs with Xilinx FPGAs. 1) Route nets out to FPGA pins. 1 signal per FPGA pin; usually pin limited Requires design change to view new signals Manual management of physical and logical signal mapping to MSO digital channels and labels - PowerPoint PPT PresentationTRANSCRIPT
Page 1
Simplifying MSO-based debug
of designs with Xilinx FPGAs
Page 2
1) Route nets out to FPGA pins
1 signal per FPGA pin; usually pin limited
Requires design change to view new signals
Manual management of physical and logical signal mapping to MSO digital channels and labels
Equal time investment for each iteration
Pins
FPGA
Probepoints
Agilent 9000 or 7000 Series
ExternalMSO
Page 3
Manual Setup of Physical Connection Single pin example
Connects to pod 1 channel 8 of the MSO
Goes to pin 10 of the mictor
connect
Pin 6 of the FPGA
FPGA Probe footprint
Oscilloscope
Page 4
Manual Setup of Signal/Bus Names on MSO
Determine which logic channel is
connected to that pin
Determine to which
connector pin it was routed
Look at schematic
FPGAProbe
footprint
Hand type eachname in MSO for
every signal routed to debug pins
Signal namein FPGA
Oscilloscope
Page 5
World’s First (& only) Integrated FPGA Oscilloscope Application
Incremental Real Time Internal Measurements …without:
• Stopping FPGA
• Changing the design
• Modifying design timing
Quick MSO Setup
• FPGA pins to MSO digital channels
• Signal and bus names
MSO FPGA Dynamic Probe
Application
Page 6
MSO FPGA Dynamic Probe Application
Options for Xilinx
– With 9000 Series MSOs
– With 6000/7000 Series MSOs
Page 7
Datasheets, Design guide, FAQ, & Resource Calculator
Options for Xilinx
– With 8000 Series MSOs www.agilent.com/find/8000-Xilinx
– With 6000 Series MSOs www.agilent.com/find/6000-Xilinx
Page 8
FPGA Dynamic Probe for Xilinx
ATC
2
Insert ATC2 core with Xilinx Core
Inserter
FPGA
PC Board
FPGA Dynamic Probe SW application supported all
Agilent MSOs
JTAG
Control access to new signals via
JTAG
USB or Parallel
Probe core output
Page 9
ATC2
Selectio
n M
UX
4 -128
4 - 1284 - 128
4 - 128
Output to FPGA pins for debug
Agilent Trace Core (ATC2)
4 -128
Change signal bank selection from MSO`
JTA
G S
ele
ct
• Up to 64 signal banks
• All banks have identical width (4 to 128 signals wide)
clkclk Up to 16 digital channelson MSOs
Page 10
Core Types for MSO
State Core (most common usage)
• Best for functional debug in one time domain
• Minimal impact on timing• MSO timing (asynchronous measurement)• Measured on each FPGA clock cycle
– State trigger– Trigger on pattern + clock edge
– State waveform display– Post-processing MSO feature
Timing Core
• Best for measurements across multiple time domains• Almost no impact on design timing
• Measurements include skew from routing path variancesGlitch detection
• Measured per MSO timing sample rate
Page 11
State Cores…always have multiple pipeline stages to minimize timing impact
buffer, the router can use timing solely within the ATC2 core tomove across the chip
The thick lines show the FF's and routes added by ATC2Since there is a FF "in the fabric" in addition to one at the I/O
Output PinPro
be p
oin
t
Customer Logic
ATC2 (1 signal)FF FF
FF
FF
Page 12
Technology Walk Through (Xilinx Example)
Xilinx Core Inserter
• Create core & put it in design
Agilent FPGA Dynamic Probe
• Pin and signal/bus setups
• Core control
• Taking measurements
Page 13
Measure in 4 different parts of communication system in a few
seconds
Demo #1- Packet Flow Demo
(MSO_comm_v9.bit)
Page 14
Target System – Xilinx XC2V250
JTAG
Mictor Connector (plug MSO cable into EVEN side)
Page 15
1. Insert ATC2 core in FPGA with Xilinx ChipScope Pro
2. FPGA Dynamic Probe SW application integrated
with Infiniium
3. Control access to new signals via
JTAG
4. Probe core output
Page 16
Define 1st Bank to View Transmit Side
“Serial to Monitor” State Machine
“Serial from Monitor” State Machine
8B/10BEncoder
Serial Packets
Serial Acks
RAM
Micro BlazeuP
Bank 0 Bank 3 Bank 2 Bank 1
TIDState
Ack IDStateTID out
MasterStateMach.
DataIn &Out
MUX
External RAM
To MSO digital Connection(15 Pins for Debug + clk)
TIDState
Ack IDState
MasterStateMachine
External Data IN
Agi le
nt
Tra
ce C
ore
2
TID Out
Monitor
JTAG to MSO or PC
Xilinx FPGA
8 7
Page 17
Define 2nd Bank to View Receive Side
“Serial to Monitor” State Machine
“Serial from Monitor” State Machine
8B/10BEncoder
Serial Packets
Serial Acks
RAM
Micro BlazeuP
Bank 0 Bank 3 Bank 2 Bank 1
TIDState
Ack IDStateTID out
MasterStateMach.
DataIn &Out
MUX
External RAM
Ack IDState
MasterStateMachine
Agi le
nt
Tra
ce C
ore
2
TID Out
Monitor
JTAG to MSO or PC
Xilinx FPGA
5 3
7
To MSO digital Connection(15 Pins for Debug + clk)
External Data IN
Page 18
“Serial to Monitor” State Machine
“Serial from Monitor” State Machine
8B/10BEncoder
Serial Packets
Serial Acks
RAM
Micro BlazeuP
Bank 0 Bank 3 Bank 2 Bank 1
TIDState
Ack IDStateTID out
MasterStateMach.
DataIn &Out
MUX
External RAM
TIDState
Ack IDState
MasterStateMachine
Agi le
nt
Tra
ce C
ore
2
TID Out
Monitor
JTAG to MSO
Xilinx FPGA
10
5
Define 3rd Bank to View 8B/10B Encoder
To MSO digital Connection(15 Pins for Debug + clk)
External Data IN
Page 19
4th Bank to View Master State Machine
“Serial to Monitor” State Machine
“Serial from Monitor” State Machine
8B/10BEncoder
Serial Packets
Serial Acks
RAM
Micro BlazeuP
Bank 0 Bank 3 Bank 2 Bank 1
TIDState
Ack IDStateTID out
MasterStateMach.
DataIn &Out
MUX
External RAM
TIDState
Ack IDState
MasterStateMachine
Agi le
nt
Tra
ce C
ore
2
TID Out
Monitor
JTAG to MSO
Xilinx FPGA
To MSO digital Connection(15 Pins for Debug + clk)
15
External Data IN
Page 20
“Serial to Monitor” State Machine
“Serial from Monitor” State Machine
8B/10BEncoder
Serial Packets
Serial Acks
RAM
Micro BlazeuP
Bank 0 Bank 3 Bank 2 Bank 1
TIDState
Ack IDStateTID out
MasterStateMach.
DataIn &Out
MUX
External RAM
TIDState
Ack IDState
MasterStateMachine
Agi le
nt
Tra
ce C
ore
2
TID Out
Monitor
JTAG to MSO
Xilinx FPGA
8 7 10
5
155 3
7
4 Signal Banks
To MSO digital Connection(15 Pins for Debug + clk)
External Data IN
Page 21
ChipScope Pro
ILA & logic analyzer viewer
Core Inserter
• Post-synthesis insertion
Core Generator
• Pre-synthesis core generation
Preferred design flow:
Page 22
TimingConstraints
Bitstream
Design Entry
Synthesis
Translate (LUTs and nets)
Map (LUTs into Slices)
Place&Route (FPGA resources)
ISEPlace&Route (FPGA resources)
ISE
Static Timing Analysis
ISE
Static Timing Analysis
ISE
Functional Simulation
Insert ATC 2 CoresXilinx Core Inserter
Program FPGA
ISE Impact
Program FPGA
ISE Impact
PROM FPGA
Minor Design ModificationsFPGA Editor
FPGA Editor
.bit
.edf .ngo .cdc
.edf
.v .vhd
.ucf
.mcs
.ncf .pcf
.sfp .sdc Post-synthesis Simulation
Timing Simulation
Inserting ATC2 Cores
Page 23
Set Core Parameters
Select Capture
Mode
# of debug pins # of signal banks Pin compression
ATC2 pin location
Xilinx Core Inserter
Page 24
Xilinx Core Inserter: Specify Signal Bank Grouping
Select Bank
Add signals
into each desired
Bank
Page 25
Enable Integrated FPGA Dynamic Probe Application
Page 28
Auto Pin mapping
ATC
3
ATC2 with auto-setup
FPGAPC Board
JTAG
1. Send “training
pattern” over a ATC2 pin one at
a time
Look for test pattern on each pin
Map physical connection between core & scope
Page 37
Triggering on Valid StatesATCK (clock) + Pattern guarantees valid state
CLK output
data outputs
Validstate
Validstate
Validstate
This design transitions on positive clock edge, so data should be stable on negative clock edges.
Page 38
Trigger on Bus2 = 02H and D15 (atck) falling edge
clk
B2
Page 39
Symbols Readouts
Page 40
Transforming Timing (asynchronous) Waveforms… into State (synchronous) Waveforms
Invalid state (happens on rising edge when design is transitioning)
Page 41
State Clock: D15 is the ATCK, data will be stable on the falling edge
Page 42
Resulting State Waveforms
Invalid states are filtered out (post-processing)
Page 43
Measure in 2 different parts of Xilinx system in a
few seconds
Demo #2- Up down counter
(MSO_up_down_20MHz.bit)
Page 44
Target System – Xilinx XC2V250
JTAG
Mictor Connector (plug MSO cable into ODD side)
Page 45
1. Insert ATC2 core in FPGA with Xilinx
ChipScope Pro
2. FPGA Dynamic Probe SW application runs on
PC
3. Control access to new signals via
JTAG
4. Probe core output
PC and MSO 6000 connect via
LAN/USB/GPIB/etc
Page 46
8 bit Count Up Design
8 bit Count Down Design
Bank 0 Bank 1
MUX
Agi le
nt
Tra
ce C
ore
2
Xilinx FPGA8 8
ATC2 core configured with 2 Signal Banks
JTAG to MSO To MSO digital Connection(8Pins for Debug + clk)
Page 47
Run the MSO FPGA Dynamic Application on PCPC connects to MSO6000 via LAN, USB, or GPIB
Page 48
FPGA Dynamic Probe
Page 50
Auto Pin Mapping
ATC
3
ATC2 with auto-setup
FPGAPC Board
JTAG
1. Send “training
pattern” over a ATC2 pin one at
a time
2. Look for test pattern on each pin
3. Map physical connection between core & scope
Page 51
Pin Mapping
MSO signals do not connect here. ATCK (clock) should be routed to any other place assessed by MSO digital channels.
Page 52
Select Bank 0 (count up & clock)
Page 53
Count Up
Bus & Signal names
Page 54
Select New Set of Internal Signals for Measurement
Page 55
Resulting Measurement
Time correlation with external events
Bus & Signal names
Page 56
State Triggering: Pattern + ATCK edgeEliminates the potential of triggering on invalid states when FPGA design is transitioning
State Triggering
Page 57
Measuring Valid States
Valid states on falling clock edge
Invalid state (FPGA design is transitioning on positive clock edge
Page 58
N5397A 8000 Series FPGA Dynamic Probe for Xilinx
Page 59
N5406A 6000 Series FPGA Dynamic Probe for Xilinx