silicon photonics at leti...leti photonics workshop | ségolène olivier | february 1st, 2017 | 4 si...

Leti Photonics Workshop | Ségolène OLIVIER | February 1st, 2017

SILICON PHOTONICS AT LETI

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SILICON PHOTONICS APPLICATIONS


> 2 kmTransport

MetroAccess

l=1550 nm100G 400G Metro

10G AccessSmall form factor optical

transceivers modules

TELECOM

1m – 10 kmRoutersSwitches

l=1310 nm100G 400G 1 Tb/s

Rack-to-RackBoard-to-Board

Mid-Board

DATACOM

< 1mPhotonic Integrated

Circuits on Chip

l=1310 nm> 1 Tb/s

Photonic transceiverson Chip

COMPUTERCOM

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Electronics

Photonics

CMOS-based photonic ICs

CMOS-based electronic driver ICs

Advanced CMOS analogand digital circuits

Passive circuitryModulatorPhotodetectorMux/DemuxLaser

CMOS compatible technology

Co-integration of CMOS-based Photonic ICs and

CMOS-based electronic ICs

Si photonics PICs :Low power consumption

high bandwidthsmall footprint

low cost

Increasing the number of WDM channels

Increasing the bit rate per channel

Increasing the number of bits per symbol : advanced modulation formats

(PAM4, PAM8, PDM-QPSK)

200-400 Gb/s

High number of fibers

Scalable for 1 Tb/s

and beyond

> 6 fibers

BENEFITS OF SILICON PHOTONICS


| 4Leti Photonics Workshop | Ségolène OLIVIER | February 1st, 2017

SI PHOTONICS BUILDING BLOCKS

Losses < -2.5 dBFeedback < -30 dBInsertion loss: 1.5 dB/mm

Efficiency: VpLp< 2.5 V.cmData rate > 25 Gb/s

Losses < -4 dB

Responsivity > 0.6 A/WDark current < 10 nABandwidth: 40 GHz

4 channels spaced by 800 GHzCross-talk < 20 dBLosses < 3 dB

Full 200 mm R&D platform for Photonic Integrated Circuits at 25 Gbaud/s

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TECHNOLOGY KEY

PROCESS FEATURES

• 200 mm Si photonics platform Substrates : 8’’ SOI 310nm,

compatible with ST foundry 190 steps 24 litho levels 40 metro/control steps

• Process building blocks Multilevel silicon patterning PN Silicon junctions PiN Germanium junctions Integrated resistance (heater) Planarized BEOL : 2 AlCu routing levels UBM for flip-chip assembly


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MPW OFFER ON 200 MM

SOI PLATFORM

http://www.europractice-ic.com http://www.cmp.imag.fr

Full-platform Photonic Integrated Circuits:passives, modulator, photodetector, localized heater, BEOL

Si310-PH platform with Si310-PHMP2M platform with

Passive Integrated Circuits with localized heaters


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HYBRID III-V ON SILICON LASERS

III-V Laser

stack

DFB grating Fiber grating

coupler

III-V laser

stack

Si

waveguide

Cross-sectionLongitudinal view

Molecular

bonding

interface

Phase shift l/4

Enhanced scalability, reduced packaging complexity, reduced link power budget


• Thick SiO2 spacer layer ≈ 100 nm• High gain• III-V to Si adiabatic coupling

Adiabatic taper in Si waveguide

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III-V/SI HYBRID INTEGRATION TECHNOLOGY

Metallization of lasers,

modulators and detectors

Processing of III-V

dies/wafer

Back-end: 100mm or 200 mm fab

III-V die or wafer molecular

bonding on processed SOI

200 or 300 mm fab

Heterostructure

3µm- thick

InP substrate

removal

Growth of the III-V wafers

Processing of SOI wafers

(modulators, detectors,

passive waveguides, etc.)

200/300-mm SOI

100mm fab

200/300 mm fab

+


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TUNABLE LASER @ 1.55 µm

FOR METRO AND ACCESS NETWORKS

Double-ring tunable laser architecture


G-H. Duan et al., “New Advances on Heterogeneous Integration of III-V on Silicon”, Invited paper, J. Lightwave Technology, 2015

• CW operation (>60°C) @ l ~ 1.55 µm

• Pfiber : 6 to >10 dBm with SOA

• SMSR > 45 dB

• Tunability : > 35 nm

10

20

30

40

50

60

1530

1540

1550

1560

1570

1580

-6 -5 -4 -3 -2 -1 0

Heater 2 (V)

VHeater 1 = 0 V, Ilaser= 150 mA, T = 20°C

Lambda (nm)

SMSR (dB)

Eye diagram at 10 Gb/s

• 10 Gb/s operation

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INTEGRATED LASER AND MODULATOR

Co-integration of hybrid III-V/Si DBR laser + Si Mach-Zehnder modulator

• Laser drive current : 100 mA• Laser wavelength : 1303.5 nm

• MZM length : 4 mm• Voltage sweep : 2.5 Vpp in push-pull


T. Ferrotti et al., « Co-integrated 1.3 µm hybrid III-V/Silicontunable laser and silicon Mach-Zehnder modulatoroperating at 25 Gb/s », Opt. Exp. , 30379 (2016)

25 Gb/s Transmissionover 10 kmER=4.7 dB

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COMPATIBILITY WITH CMOS

INDUSTRIAL FOUNDRY

Metallic interconnections needed for driving the active devices

Si Bulk

Si

ModulatorWaveguide

BOX

Hybrid laser

Grating coupler Photodiode

SiO2

SiN

500

nm

1 µm

X

Y

Z

Metal 1

Metal 2

Metal 3

Metal 4

≈ 3µmIII-V

Si Bulk

Si

ModulatorWaveguide

BOX

Hybrid laser


SiO2

SiN

300

nm

X

Y

Z

Metal 1

Metal 2

Metal 3

Metal 4

≈ 3µmIII-V


Typical Front-side hybrid III-V/Si Laser realized by direct bonding

Si Bulk

III-V

Si

ModulatorWaveguide

BOX

Hybrid laser Grating

coupler

Photo-

diode

SiO2

SiN

500

nm

1 µm

X

Y

Z

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Si Bulk

III-V

SiModulatorWaveguide

Hybrid laser


SiO2

SiN

≈ 3µm

500

nm

Metal 4Metal 3Metal 2Metal 1

X

Y

Z

Compatibility between hybrid III-V/Si laser and

4-level metal interconnects


COMPATIBILITY WITH CMOS

INDUSTRIAL FOUNDRY

Back-side III-V on Si laser integration scheme

J. Durel et al., « First demonstration of a back-side integrated heterogeneoushybrid III-V/Si DBR lasers for Si-Photonics applications », IEDM (2016)

• Threshold : 45 mA

• Output power > 1 mW @ 200 mA

• SMSR > 35 dB

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100G SILICON PHOTONICS MODULES

• EIC = 65nm CMOS quad-TIA from STMicroelectronics• 3D integration of electronic and photonic ICs using copper pillars

4x25 Gb/s WDM photoreceiver module with flip-chipped TIA

Copper pillars


Eye diagams at 25 Gb/s on 2 receiver channels

S. Bernabe et al., « A fully packaged 25 Gbps/channel WDM photoreceivermodule based on a Silicon Photonic Integrated Circuit and a flip-chippedCMOS quad transimpedance amplifier », Proc. Of IEEE OIC, 2016

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FUTURE DIRECTIONS

• Advanced high-speed & low-power consumption photonic devices at 50G


• Technology evolution

• Full process of hybrid III-V/Si lasers in 200 mm wafer format• Introduction of SiN layer on III-V/SOI platform for CWDM applications

• 100G, 400G to 1 Tb/s WDM transmitter circuits at 1.55 and 1.31 µm for

• Coherent transceivers for metro networks• Mid-board transceivers for datacenters• Optical Networks on Chip

• Longer-term directions

• Non-linear circuits based on SiN or GaAs on SOI platform for Pb/s data traffic• Ge lasers on Silicon• Quantum integrated photonic circuits for perfectly secured communication networks

Leti, technology research institute

Commissariat à l’énergie atomique et aux énergies alternatives

Minatec Campus | 17 rue des Martyrs | 38054 Grenoble Cedex | France

www.leti.fr

SILICON PHOTONICS LAB

• Core team : 35 people• Patent porfolio > 60• Publications > 10/year• Conference board

member: OIC, GFP, ECTC, ESTC

Thank you for your attention !

The Silicon Photonics team

Contacts :

[email protected]

[email protected]

mailto:[email protected]

mailto:[email protected]

silicon photonics at leti...leti photonics workshop | ségolène olivier | february 1st, 2017 | 4 si...

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